Triang3l
e37e3ef382
[GPU] Display swap output in the trace viewer
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Resolve output is unreliable because resolving may be done to a subregion of a texture and even to 3D textures, and to any color format
2022-07-01 19:50:19 +03:00
Triang3l
28670d8ec2
[UI] Presenter: Rename display size to aspect ratio
2022-07-01 12:50:45 +03:00
Triang3l
7e691d5ef1
[DXBC] Handle NaN in not equal alpha test as passed
2022-06-30 22:15:01 +03:00
Triang3l
a11b070fee
[GPU] Align texture extents in loading to host buffer texel size accessed by the shader
2022-06-29 23:38:06 +03:00
Triang3l
243683d2e9
[GPU] Cleanup Texture::MarkAsUsed conditionals
2022-06-28 22:04:26 +03:00
Triang3l
382710bab7
[GPU] Normalize sampler clamp modes
2022-06-28 21:58:58 +03:00
Triang3l
cedc94679b
[GPU] Don't drop the rest of the command list if IssueDraw fails
2022-06-28 21:40:06 +03:00
Triang3l
ec008463b6
[GPU] CrYCb/YCrCb border colors
2022-06-26 18:56:50 +03:00
Triang3l
2606fa5709
[GPU] Apply BaseMap MipFilter via samplers as it may be overridden
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Make it have no effect on the texture resource as a resource may be used with samplers with different overrides. Also make sure magnification vs. minification is not undefined with it on Direct3D 12.
2022-06-26 18:41:38 +03:00
Triang3l
086a070fa9
[GPU] Explicitly cast bit field values in std::min/max
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According to the integral promotion rules https://eel.is/c++draft/conv.prom#5.sentence-1 bit fields can be promoted to `int` if it's wide enough to store their value, and then otherwise, to `unsigned int`. Hopefully fixes Clang building (the `width_div_8` case).
2022-06-26 16:54:11 +03:00
Triang3l
e0b890fe5c
[DXBC] Remove alphatest/A2C with [earlydepthstencil]
2022-06-26 15:31:08 +03:00
Triang3l
b787f2dec1
[GPU] GPR count limit is 128, not 64
2022-06-26 14:45:49 +03:00
Triang3l
4812b4ba8b
[D3D12] Fix outdated color system constants comment [ci skip]
2022-06-25 20:31:05 +03:00
Triang3l
aa45d7b47d
[D3D12] More descriptive pipeline creation call comment [ci skip]
2022-06-25 15:13:11 +03:00
Triang3l
f4a634c617
[XeSL] xesl_write*Store > xesl_*Store
2022-06-24 23:37:29 +03:00
Triang3l
7a4732e14f
[GPU] XeSL swap shaders
2022-06-24 23:24:30 +03:00
Triang3l
b7737d70ca
[D3D12] Update RequestSwapTexture resource state comment [ci skip]
2022-06-23 22:59:53 +03:00
Triang3l
e9f129f67f
[GPU] Safer and more correct depth bias conversion
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Float24-as-float32 depth bias is now in the increments of 8, because conversion of the depth to float24 directly in the pixel shaders may destroy the bias qualitatively otherwise if it's too small.
2022-06-22 21:14:40 +03:00
Triang3l
a7885ae1a4
[GPU] Fix CPU-side float24 conversion broken recently
2022-06-22 20:47:44 +03:00
Triang3l
cbf0476d42
[D3D12] Don't round float24 depth when it's known to be exact
2022-06-22 13:14:38 +03:00
Triang3l
7869b080d3
[D3D12] Truncate depth to float24 in EDRAM range ownership transfers and resolves by default
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Doesn't ruin the "greater or equal" depth test in subsequent rendering passes if precision is lost, unlike rounding to the nearest
2022-06-22 12:53:09 +03:00
Triang3l
e2f632f8fa
[D3D12] Use udiv by constant tile size + minor transfer cleanup
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Drivers compile that to a multiplication and a shift anyway.
2022-06-20 22:39:30 +03:00
Triang3l
207e11c8d2
[GPU] Separate range arguments for fixed16 RG and RGBA in GetResolveInfo
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On Vulkan, when snorm16 in unsupported, these formats may be emulated as float16, which natively can represent a wide range of numbers including -32 to 32 with blending. However, R16G16_SNORM and R16G16B16A16_SNORM are two separate formats, which may have different support on the device.
2022-06-20 12:29:45 +03:00
Triang3l
3b4845511d
[Vulkan] Don't require an explicit uint64_t cast for SetDeviceObjectName
2022-06-20 12:25:52 +03:00
Triang3l
67ff108f53
[Vulkan] Explain why CreateShaderModule takes uint32_t* [ci skip]
2022-06-20 12:22:41 +03:00
Triang3l
b61953374e
[GPU] Make resolve EDRAM binding DS 0 and rename it
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Ordering the descriptor sets by the change frequency on Vulkan, in increasing order (the opposite of D3D12 root signatures). The EDRAM binding never changes there (always one storage buffer), while the destination buffer binding may become changeable in the future (to split dispatches if exceeding `maxStorageBufferRange`, for example).
2022-06-20 12:15:52 +03:00
Triang3l
9b83d3d0f4
[GPU] XeSL resolve shaders + host depth store width fix
2022-06-19 17:50:21 +03:00
Triang3l
166be463be
[XeSL] Metal Shading Language definitions
2022-06-16 21:39:16 +03:00
Triang3l
820b7ba217
[GPU] Fix GetActiveTextureHostSwizzle return type
2022-06-12 18:50:38 +03:00
Triang3l
78d1eb8bf8
[GPU] TextureCache::GetActiveTextureHostSwizzle
2022-06-09 21:34:21 +03:00
Triang3l
56f72da137
[GPU] More exact PWL texture/RT gamma conversion
2022-06-07 21:26:34 +03:00
Triang3l
55a91afcc7
[D3D12] Don't decompress unaligned BC textures if supported
2022-06-02 22:48:03 +03:00
Triang3l
84fcd5defa
[GPU] Fix resolve destination offset and extent calculation
2022-06-02 21:47:30 +03:00
Triang3l
a9a072bf00
[GPU] Explain why a 32x32x4bpp linear texture takes 2 pages, not 1 [ci skip]
2022-06-01 13:00:23 +03:00
Triang3l
8bd244f277
[GPU] Better explanation for exact texture memory extent calculation [ci skip]
2022-06-01 12:55:16 +03:00
Triang3l
d1ad10b98c
[GPU] Primitive reset comment typo correction [ci skip]
2022-05-31 23:23:53 +03:00
Triang3l
efd7ef212a
[D3D12] 128 megatexel limit explanation based on the spec [ci skip]
2022-05-31 23:23:10 +03:00
Triang3l
25594c918c
[GPU] Fix tiled texture memory extent calculation
2022-05-31 23:17:33 +03:00
Rick Gibbed
a3e5ea8575
[Base] Fix missing include in utf8.cc.
2022-05-27 17:56:14 -05:00
Triang3l
a4840e1992
[GPU] FIXME comment for 1bpb/2bpb texture tiled extent
2022-05-24 22:33:27 +03:00
Triang3l
8701c9f24e
[D3D12] Texture load code cleanup and resolution scaling fixes
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The resolution scale is now taken into account when copying from the mip tail.
2022-05-24 22:28:42 +03:00
Triang3l
75c185e759
[GPU] Move texture load shader info to common
2022-05-24 22:24:33 +03:00
Triang3l
c1f15c86a3
[GPU] Decompress GBGR/BGRG into RGBB, not RGB1
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While the alpha of the texture data is not used at all (replaced with blue using the view swizzle), still make the shader code state the intention more explicitly if the format is decompressed for use as signed. Unsigned 1.0 is 0xFF, while signed 1.0 is 0x7F.
2022-05-23 12:31:45 +03:00
Triang3l
cf3069eb13
[GPU] Signedness in Cr_Y1_Cb_Y0_REP/Y1_Cr_Y0_Cb_REP comment [ci skip]
2022-05-22 22:11:59 +03:00
Triang3l
ef808e9def
[GPU] _REP explanation in Cr_Y1_Cb_Y0_REP/Y1_Cr_Y0_Cb_REP comment [ci skip]
2022-05-22 21:46:11 +03:00
Triang3l
6735dbd941
[GPU] Calculate, not store, texture load host X blocks per thread
2022-05-22 21:21:54 +03:00
Triang3l
888d5044e0
[GPU] 2x1-subsampled texture RGBA8 conversion shader
2022-05-22 21:07:38 +03:00
Triang3l
d3561d2f47
[D3D12] Pre-swizzle 2x1-subsampled formats
2022-05-22 20:31:48 +03:00
Triang3l
5de825e3a0
[GPU] Prevent multiple evaluation of XE_TEXTURE_LOAD_TRANSFORM arguments
2022-05-22 19:48:23 +03:00
Triang3l
2f0a884438
[GPU] Add k prefix to texture load group size constants
2022-05-22 19:35:25 +03:00