Alvin Chang 6ffe9b6669 target/riscv: Add textra matching condition for the triggers ... According to RISC-V Debug specification, the optional textra32 and textra64 trigger CSRs can be used to configure additional matching conditions for the triggers. For example, if the textra.MHSELECT field is set to 4 (mcontext), this trigger will only match or fire if the low bits of mcontext/hcontext equal textra.MHVALUE field. This commit adds the aforementioned matching condition as common trigger matching conditions. Currently, the only legal values of textra.MHSELECT are 0 (ignore) and 4 (mcontext). When textra.MHSELECT is 0, we pass the checking. When textra.MHSELECT is 4, we compare textra.MHVALUE with mcontext CSR. The remaining fields, such as textra.SBYTEMASK, textra.SVALUE, and textra.SSELECT, are hardwired to zero for now. Thus, we skip checking them here. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240826024657.262553-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-10-02 15:11:51 +10:00
..
insn_trans	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
kvm	target/riscv/kvm: Fix the group bit setting of AIA	2024-10-02 15:11:51 +10:00
tcg	target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule	2024-10-02 15:11:51 +10:00
Kconfig	target/riscv: Restrict semihosting to TCG	2024-07-22 09:38:11 +01:00
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00
arch_dump.c	target/riscv: Fix format for comments	2023-05-05 10:49:50 +10:00
bitmanip_helper.c	target/riscv: rvk: add support for zbkx extension	2022-04-29 10:47:45 +10:00
common-semi-target.h	semihosting: Split out common-semi-target.h	2022-06-28 04:35:07 +05:30
cpu-param.h	license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later	2024-09-20 10:11:59 +03:00
cpu-qom.h	target/riscv: Remove the deprecated 'any' CPU type	2024-09-13 20:11:13 +02:00
cpu.c	target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension	2024-10-02 15:11:51 +10:00
cpu.h	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
cpu_bits.h	target/riscv: Preliminary textra trigger CSR writting support	2024-10-02 15:11:51 +10:00
cpu_cfg.h	target/riscv: Add a property to set vl to ceil(AVL/2)	2024-10-02 15:11:51 +10:00
cpu_helper.c	target/riscv: Implement privilege mode filtering for cycle/instret	2024-07-18 12:08:44 +10:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2023-05-05 10:49:50 +10:00
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	2023-09-11 11:45:55 +10:00
csr.c	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
debug.c	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
debug.h	target/riscv: Add textra matching condition for the triggers	2024-10-02 15:11:51 +10:00
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	2024-06-26 23:02:35 +10:00
gdbstub.c	riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()	2024-06-03 11:12:12 +10:00
helper.h	target/riscv: Raise exceptions on wrs.nto	2024-06-03 11:12:11 +10:00
insn16.decode	target/riscv: Add zcmop extension	2024-07-18 12:00:42 +10:00
insn32.decode	target/riscv: Add amocas.[b|h] for Zabha	2024-07-18 12:00:42 +10:00
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	2022-09-07 09:18:32 +02:00
internals.h	target: Set TCGCPUOps::cpu_exec_halt to target's has_work implementation	2024-07-11 11:41:34 +01:00
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	2023-08-31 19:47:43 +02:00
machine.c	target/riscv: Save counter values during countinhibit update	2024-07-18 12:08:44 +10:00
meson.build	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
monitor.c	target/riscv: remove break after g_assert_not_reached()	2024-09-24 13:53:35 +02:00
op_helper.c	target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR	2024-07-18 12:08:45 +10:00
pmp.c	exec/cpu: Extract page-protection definitions to page-protection.h	2024-05-06 11:17:15 +02:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add asserts for out-of-bound access	2024-08-06 14:20:16 +10:00
pmu.h	target/riscv: More accurately model priv mode filtering.	2024-07-18 12:08:45 +10:00
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	2024-03-12 14:03:00 +01:00
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	2024-06-03 11:12:11 +10:00
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	2024-06-03 11:12:12 +10:00
time_helper.c	target/riscv: Stop timer with infinite timecmp	2024-10-02 15:11:51 +10:00
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2023-05-05 10:49:49 +10:00
trace-events	target/riscv: Add ePMP CSR access functions	2021-05-11 20:02:06 +10:00
trace.h	trace: switch position of headers to what Meson requires	2020-08-21 06:18:24 -04:00
translate.c	target/riscv: Move gen_cmpxchg before adding amocas.[b|h]	2024-07-18 12:00:42 +10:00
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
vector_helper.c	target/riscv: Add a property to set vl to ceil(AVL/2)	2024-10-02 15:11:51 +10:00
vector_internals.c	target/riscv: Fix the element agnostic function problem	2024-06-03 11:12:12 +10:00
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	2024-03-22 15:20:02 +10:00
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2023-02-07 08:19:23 +10:00
zce_helper.c	target/riscv: add support for Zcmt extension	2023-05-05 10:49:50 +10:00