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target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension 

FCSR is a part of F extension. Print it to log if FPU option is enabled.

Signed-off-by: Maria Klauchek <m.klauchek@syntacore.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20240902103433.18424-1-m.klauchek@syntacore.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Maria Klauchek 2024-09-02 13:34:33 +03:00 committed by Alistair Francis
parent 2d2e3bdc69
commit af0b5b7b2a
1 changed files with 6 additions and 0 deletions
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6
target/riscv/cpu.c
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@ -823,6 +823,12 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
}
if (flags & CPU_DUMP_FPU) {
target_ulong val = 0;
RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
if (res == RISCV_EXCP_NONE) {
qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
csr_ops[CSR_FCSR].name, val);
}
for (i = 0; i < 32; i++) {
qemu_fprintf(f, " %-8s %016" PRIx64,
riscv_fpr_regnames[i], env->fpr[i]);