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target-arm queue: 

* Fix KVM SVE ID register probe code
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Merge tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * Fix KVM SVE ID register probe code

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# gpg: Signature made Mon 01 Aug 2022 08:35:24 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full]

* tag 'pull-target-arm-20220801' of https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Move sve probe inside kvm >= 4.15 branch
  target/arm: Set KVM_ARM_VCPU_SVE while probing the host
  target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-08-01 12:00:08 -07:00
parent b15bdb1d83 5265d24c98
commit 0e0c2cf6de
1 changed files with 22 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
target/arm/kvm64.c
View File

@ -507,7 +507,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
bool sve_supported; bool sve_supported;
bool pmu_supported = false; bool pmu_supported = false;
uint64_t features = 0; uint64_t features = 0;
uint64_t t;
int err; int err;
/* Old kernels may not know about the PREFERRED_TARGET ioctl: however /* Old kernels may not know about the PREFERRED_TARGET ioctl: however
@ -528,10 +527,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
struct kvm_vcpu_init init = { .target = -1, }; struct kvm_vcpu_init init = { .target = -1, };
/* /*
* Ask for Pointer Authentication if supported. We can't play the * Ask for SVE if supported, so that we can query ID_AA64ZFR0,
* SVE trick of synthesising the ID reg as KVM won't tell us * which is otherwise RAZ.
* whether we have the architected or IMPDEF version of PAuth, so */
* we have to use the actual ID regs. sve_supported = kvm_arm_sve_supported();
if (sve_supported) {
init.features[0] |= 1 << KVM_ARM_VCPU_SVE;
}
/*
* Ask for Pointer Authentication if supported, so that we get
* the unsanitized field values for AA64ISAR1_EL1.
*/ */
if (kvm_arm_pauth_supported()) { if (kvm_arm_pauth_supported()) {
init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS |
@ -673,25 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
ARM64_SYS_REG(3, 3, 9, 12, 0)); ARM64_SYS_REG(3, 3, 9, 12, 0));
} }
}
sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; if (sve_supported) {
/*
/* Add feature bits that can't appear until after VCPU init. */ * There is a range of kernels between kernel commit 73433762fcae
if (sve_supported) { * and f81cb2c3ad41 which have a bug where the kernel doesn't
t = ahcf->isar.id_aa64pfr0; * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); * enabled SVE support, which resulted in an error rather than RAZ.
ahcf->isar.id_aa64pfr0 = t; * So only read the register if we set KVM_ARM_VCPU_SVE above.
*/
/* err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
* There is a range of kernels between kernel commit 73433762fcae ARM64_SYS_REG(3, 0, 0, 4, 4));
* and f81cb2c3ad41 which have a bug where the kernel doesn't expose }
* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
* SVE support, so we only read it here, rather than together with all
* the other ID registers earlier.
*/
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
ARM64_SYS_REG(3, 0, 0, 4, 4));
} }
kvm_arm_destroy_scratch_host_vcpu(fdarray); kvm_arm_destroy_scratch_host_vcpu(fdarray);