mirror of https://github.com/xemu-project/xemu.git
target/arm: Move sve probe inside kvm >= 4.15 branch
The test for the IF block indicates no ID registers are exposed, much less host support for SVE. Move the SVE probe into the ELSE block. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220726045828.53697-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -679,18 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0,
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ARM64_SYS_REG(3, 3, 9, 12, 0));
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}
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}
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if (sve_supported) {
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't expose
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* SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled
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* SVE support, which resulted in an error rather than RAZ.
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* So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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if (sve_supported) {
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/*
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* There is a range of kernels between kernel commit 73433762fcae
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* and f81cb2c3ad41 which have a bug where the kernel doesn't
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* expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has
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* enabled SVE support, which resulted in an error rather than RAZ.
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* So only read the register if we set KVM_ARM_VCPU_SVE above.
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*/
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err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0,
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ARM64_SYS_REG(3, 0, 0, 4, 4));
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}
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}
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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