From 0dd14e9555225a2b1f56ccdab5eb99d1684869b9 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 1 Aug 2022 16:21:17 +0100 Subject: [PATCH 1/3] target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features Indication for support for SVE will not depend on whether we perform the query on the main kvm_state or the temp vcpu. Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index d16d4ea250..bb1516b3d5 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -675,7 +675,7 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; + sve_supported = kvm_arm_sve_supported(); /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { From b9e8d68a3982a470b1d42abda90fcd46c01b52bc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 1 Aug 2022 16:21:18 +0100 Subject: [PATCH 2/3] target/arm: Set KVM_ARM_VCPU_SVE while probing the host Because we weren't setting this flag, our probe of ID_AA64ZFR0 was always returning zero. This also obviates the adjustment of ID_AA64PFR0, which had sanitized the SVE field. The effects of the bug are not visible, because the only thing that ID_AA64ZFR0 is used for within qemu at present is tcg translation. The other tests for SVE within KVM are via ID_AA64PFR0.SVE. Reported-by: Zenghui Yu Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index bb1516b3d5..43cd7eb890 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -507,7 +507,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) bool sve_supported; bool pmu_supported = false; uint64_t features = 0; - uint64_t t; int err; /* Old kernels may not know about the PREFERRED_TARGET ioctl: however @@ -528,10 +527,17 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) struct kvm_vcpu_init init = { .target = -1, }; /* - * Ask for Pointer Authentication if supported. We can't play the - * SVE trick of synthesising the ID reg as KVM won't tell us - * whether we have the architected or IMPDEF version of PAuth, so - * we have to use the actual ID regs. + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, + * which is otherwise RAZ. + */ + sve_supported = kvm_arm_sve_supported(); + if (sve_supported) { + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; + } + + /* + * Ask for Pointer Authentication if supported, so that we get + * the unsanitized field values for AA64ISAR1_EL1. */ if (kvm_arm_pauth_supported()) { init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | @@ -675,20 +681,13 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) } } - sve_supported = kvm_arm_sve_supported(); - - /* Add feature bits that can't appear until after VCPU init. */ if (sve_supported) { - t = ahcf->isar.id_aa64pfr0; - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - ahcf->isar.id_aa64pfr0 = t; - /* * There is a range of kernels between kernel commit 73433762fcae * and f81cb2c3ad41 which have a bug where the kernel doesn't expose * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, so we only read it here, rather than together with all - * the other ID registers earlier. + * SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. */ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, ARM64_SYS_REG(3, 0, 0, 4, 4)); From 5265d24c981dfdda8d29b44f7e84a514da75eedc Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 1 Aug 2022 16:21:18 +0100 Subject: [PATCH 3/3] target/arm: Move sve probe inside kvm >= 4.15 branch The test for the IF block indicates no ID registers are exposed, much less host support for SVE. Move the SVE probe into the ELSE block. Signed-off-by: Richard Henderson Message-id: 20220726045828.53697-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/kvm64.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 43cd7eb890..9b9dd46d78 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -679,18 +679,18 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, ARM64_SYS_REG(3, 3, 9, 12, 0)); } - } - if (sve_supported) { - /* - * There is a range of kernels between kernel commit 73433762fcae - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled - * SVE support, which resulted in an error rather than RAZ. - * So only read the register if we set KVM_ARM_VCPU_SVE above. - */ - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, - ARM64_SYS_REG(3, 0, 0, 4, 4)); + if (sve_supported) { + /* + * There is a range of kernels between kernel commit 73433762fcae + * and f81cb2c3ad41 which have a bug where the kernel doesn't + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has + * enabled SVE support, which resulted in an error rather than RAZ. + * So only read the register if we set KVM_ARM_VCPU_SVE above. + */ + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, + ARM64_SYS_REG(3, 0, 0, 4, 4)); + } } kvm_arm_destroy_scratch_host_vcpu(fdarray);