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stella
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Added rule for recompiling the M6502.m4 script to the Makefile, because I'm 

tired of doing it manually every time it changes.

Tweaked the handling of JSR, RTI and RTS commands, so they don't erroneously
mark associated addresses as CODE when in fact they're never actually
executed.

Several parts of the Distella code were marking areas as DATA, even though
it depending on knowing the values for the X and Y registers (which it
doesn't, as it's a static analysis).  As such, these areas are now marked
as ROW instead, since that's as precise as a static analysis can do.  The
processing blocks are left there, though, in case Distella is improved in
a future release.

All the above changes allow for better disassembly with less
'false positives' (ie, areas marked as CODE or DATA when they really aren't).


git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2172 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba
This commit is contained in:
stephena 2010-11-07 22:52:42 +00:00
parent ea8d329e0c
commit 773092142e
5 changed files with 40 additions and 21 deletions
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4
Makefile
View File

@ -188,6 +188,10 @@ uninstall:
rm -f "$(DESTDIR)$(DATADIR)/icons/mini/stella.png"
rm -f "$(DESTDIR)$(DATADIR)/icons/large/stella.png"
# Special rule for M6502.ins, generated from m4 (there's probably a better way to do this ...)
src/emucore/M6502.ins: src/emucore/M6502.m4
m4 src/emucore/M6502.m4 > src/emucore/M6502.ins
# Special rule for Win32 icon stuff (there's probably a better way to do this ...)
src/win32/stella_icon.o: src/win32/stella.ico src/win32/stella.rc
$(WINDRES) --include-dir src/win32 src/win32/stella.rc src/win32/stella_icon.o

20
src/debugger/DiStella.cxx
View File

@ -453,7 +453,9 @@ void DiStella::disasm(uInt32 distart, int pass)
}
}
else if(ad > 0xfff)
{
mark(ad, CartDebug::DATA);
}
}
else if (pass == 3)
{
@ -521,7 +523,11 @@ void DiStella::disasm(uInt32 distart, int pass)
labfound = mark(ad, CartDebug::REFERENCED);
if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE))
{
mark(ad, CartDebug::DATA);
// Since we can't know what address is being accessed unless we also
// know the current X value, this is marked as ROW instead of DATA
// The processing is left here, however, in case future versions of
// the code can somehow track access to CPU registers
mark(ad, CartDebug::ROW);
}
else if (pass == 3)
{
@ -561,7 +567,11 @@ void DiStella::disasm(uInt32 distart, int pass)
labfound = mark(ad, CartDebug::REFERENCED);
if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE))
{
mark(ad, CartDebug::DATA);
// Since we can't know what address is being accessed unless we also
// know the current Y value, this is marked as ROW instead of DATA
// The processing is left here, however, in case future versions of
// the code can somehow track access to CPU registers
mark(ad, CartDebug::ROW);
}
else if (pass == 3)
{
@ -688,7 +698,11 @@ void DiStella::disasm(uInt32 distart, int pass)
labfound = mark(ad, CartDebug::REFERENCED);
if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE))
{
mark(ad, CartDebug::DATA);
// Since we can't know what address is being accessed unless we also
// know the current X value, this is marked as ROW instead of DATA
// The processing is left here, however, in case future versions of
// the code can somehow track access to CPU registers
mark(ad, CartDebug::ROW);
}
else if (pass == 3)
{

1
src/emucore/M6502.cxx
View File

@ -196,6 +196,7 @@ inline uInt8 M6502::peek(uInt16 address, uInt8 flags)
myHitTrapInfo.message = "RTrap: ";
myHitTrapInfo.address = address;
}
//cerr << "addr = " << HEX4 << address << ", flags = " << Debugger::to_bin_8(flags) << endl;
#endif
uInt8 result = mySystem->peek(address, flags);

20
src/emucore/M6502.ins
View File

@ -14,7 +14,7 @@
// See the file "License.txt" for information on usage and redistribution of
// this file, and for a DISCLAIMER OF ALL WARRANTIES.
//
// $Id: M6502.m4 2158 2010-10-21 21:16:55Z stephena $
// $Id: M6502.m4 2163 2010-10-24 14:55:42Z stephena $
//============================================================================
/**
@ -24,7 +24,7 @@
'm4 M6502.m4 > M6502.ins'
@author Bradford W. Mott
@version $Id: M6502.m4 2158 2010-10-21 21:16:55Z stephena $
@version $Id: M6502.m4 2163 2010-10-24 14:55:42Z stephena $
*/
#ifndef NOTSAMEPAGE
@ -2116,7 +2116,7 @@ break;
case 0x20:
{
uInt8 low = peek(PC++, DISASM_CODE);
peek(0x0100 + SP, DISASM_DATA);
peek(0x0100 + SP, DISASM_NONE);
// It seems that the 650x does not push the address of the next instruction
// on the stack it actually pushes the address of the next instruction
@ -3597,10 +3597,10 @@ case 0x40:
peek(PC, DISASM_NONE);
}
{
peek(0x0100 + SP++, DISASM_DATA);
PS(peek(0x0100 + SP++, DISASM_DATA));
PC = peek(0x0100 + SP++, DISASM_CODE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8);
peek(0x0100 + SP++, DISASM_NONE);
PS(peek(0x0100 + SP++, DISASM_NONE));
PC = peek(0x0100 + SP++, DISASM_NONE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8);
}
break;
@ -3610,9 +3610,9 @@ case 0x60:
peek(PC, DISASM_NONE);
}
{
peek(0x0100 + SP++, DISASM_DATA);
PC = peek(0x0100 + SP++, DISASM_CODE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8);
peek(0x0100 + SP++, DISASM_NONE);
PC = peek(0x0100 + SP++, DISASM_NONE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8);
peek(PC++, DISASM_CODE);
}
break;

16
src/emucore/M6502.m4
View File

@ -637,7 +637,7 @@ define(M6502_JMP, `{
define(M6502_JSR, `{
uInt8 low = peek(PC++, DISASM_CODE);
peek(0x0100 + SP, DISASM_DATA);
peek(0x0100 + SP, DISASM_NONE);
// It seems that the 650x does not push the address of the next instruction
// on the stack it actually pushes the address of the next instruction
@ -838,16 +838,16 @@ define(M6502_RRA, `{
}')
define(M6502_RTI, `{
peek(0x0100 + SP++, DISASM_DATA);
PS(peek(0x0100 + SP++, DISASM_DATA));
PC = peek(0x0100 + SP++, DISASM_CODE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8);
peek(0x0100 + SP++, DISASM_NONE);
PS(peek(0x0100 + SP++, DISASM_NONE));
PC = peek(0x0100 + SP++, DISASM_NONE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8);
}')
define(M6502_RTS, `{
peek(0x0100 + SP++, DISASM_DATA);
PC = peek(0x0100 + SP++, DISASM_CODE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8);
peek(0x0100 + SP++, DISASM_NONE);
PC = peek(0x0100 + SP++, DISASM_NONE);
PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8);
peek(PC++, DISASM_CODE);
}')