From 773092142e60789b5cbbde46118b98646845c859 Mon Sep 17 00:00:00 2001 From: stephena Date: Sun, 7 Nov 2010 22:52:42 +0000 Subject: [PATCH] Added rule for recompiling the M6502.m4 script to the Makefile, because I'm tired of doing it manually every time it changes. Tweaked the handling of JSR, RTI and RTS commands, so they don't erroneously mark associated addresses as CODE when in fact they're never actually executed. Several parts of the Distella code were marking areas as DATA, even though it depending on knowing the values for the X and Y registers (which it doesn't, as it's a static analysis). As such, these areas are now marked as ROW instead, since that's as precise as a static analysis can do. The processing blocks are left there, though, in case Distella is improved in a future release. All the above changes allow for better disassembly with less 'false positives' (ie, areas marked as CODE or DATA when they really aren't). git-svn-id: svn://svn.code.sf.net/p/stella/code/trunk@2172 8b62c5a3-ac7e-4cc8-8f21-d9a121418aba --- Makefile | 4 ++++ src/debugger/DiStella.cxx | 20 +++++++++++++++++--- src/emucore/M6502.cxx | 1 + src/emucore/M6502.ins | 20 ++++++++++---------- src/emucore/M6502.m4 | 16 ++++++++-------- 5 files changed, 40 insertions(+), 21 deletions(-) diff --git a/Makefile b/Makefile index 72c1082a9..26e855d08 100644 --- a/Makefile +++ b/Makefile @@ -188,6 +188,10 @@ uninstall: rm -f "$(DESTDIR)$(DATADIR)/icons/mini/stella.png" rm -f "$(DESTDIR)$(DATADIR)/icons/large/stella.png" +# Special rule for M6502.ins, generated from m4 (there's probably a better way to do this ...) +src/emucore/M6502.ins: src/emucore/M6502.m4 + m4 src/emucore/M6502.m4 > src/emucore/M6502.ins + # Special rule for Win32 icon stuff (there's probably a better way to do this ...) src/win32/stella_icon.o: src/win32/stella.ico src/win32/stella.rc $(WINDRES) --include-dir src/win32 src/win32/stella.rc src/win32/stella_icon.o diff --git a/src/debugger/DiStella.cxx b/src/debugger/DiStella.cxx index 11f6020c9..b474ed215 100644 --- a/src/debugger/DiStella.cxx +++ b/src/debugger/DiStella.cxx @@ -453,7 +453,9 @@ void DiStella::disasm(uInt32 distart, int pass) } } else if(ad > 0xfff) + { mark(ad, CartDebug::DATA); + } } else if (pass == 3) { @@ -521,7 +523,11 @@ void DiStella::disasm(uInt32 distart, int pass) labfound = mark(ad, CartDebug::REFERENCED); if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE)) { - mark(ad, CartDebug::DATA); + // Since we can't know what address is being accessed unless we also + // know the current X value, this is marked as ROW instead of DATA + // The processing is left here, however, in case future versions of + // the code can somehow track access to CPU registers + mark(ad, CartDebug::ROW); } else if (pass == 3) { @@ -561,7 +567,11 @@ void DiStella::disasm(uInt32 distart, int pass) labfound = mark(ad, CartDebug::REFERENCED); if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE)) { - mark(ad, CartDebug::DATA); + // Since we can't know what address is being accessed unless we also + // know the current Y value, this is marked as ROW instead of DATA + // The processing is left here, however, in case future versions of + // the code can somehow track access to CPU registers + mark(ad, CartDebug::ROW); } else if (pass == 3) { @@ -688,7 +698,11 @@ void DiStella::disasm(uInt32 distart, int pass) labfound = mark(ad, CartDebug::REFERENCED); if (pass == 2 && !check_bit(ad & myAppData.end, CartDebug::CODE)) { - mark(ad, CartDebug::DATA); + // Since we can't know what address is being accessed unless we also + // know the current X value, this is marked as ROW instead of DATA + // The processing is left here, however, in case future versions of + // the code can somehow track access to CPU registers + mark(ad, CartDebug::ROW); } else if (pass == 3) { diff --git a/src/emucore/M6502.cxx b/src/emucore/M6502.cxx index 83a6320c1..6db746b7a 100644 --- a/src/emucore/M6502.cxx +++ b/src/emucore/M6502.cxx @@ -196,6 +196,7 @@ inline uInt8 M6502::peek(uInt16 address, uInt8 flags) myHitTrapInfo.message = "RTrap: "; myHitTrapInfo.address = address; } +//cerr << "addr = " << HEX4 << address << ", flags = " << Debugger::to_bin_8(flags) << endl; #endif uInt8 result = mySystem->peek(address, flags); diff --git a/src/emucore/M6502.ins b/src/emucore/M6502.ins index 41623269d..2bcf5a2ab 100644 --- a/src/emucore/M6502.ins +++ b/src/emucore/M6502.ins @@ -14,7 +14,7 @@ // See the file "License.txt" for information on usage and redistribution of // this file, and for a DISCLAIMER OF ALL WARRANTIES. // -// $Id: M6502.m4 2158 2010-10-21 21:16:55Z stephena $ +// $Id: M6502.m4 2163 2010-10-24 14:55:42Z stephena $ //============================================================================ /** @@ -24,7 +24,7 @@ 'm4 M6502.m4 > M6502.ins' @author Bradford W. Mott - @version $Id: M6502.m4 2158 2010-10-21 21:16:55Z stephena $ + @version $Id: M6502.m4 2163 2010-10-24 14:55:42Z stephena $ */ #ifndef NOTSAMEPAGE @@ -2116,7 +2116,7 @@ break; case 0x20: { uInt8 low = peek(PC++, DISASM_CODE); - peek(0x0100 + SP, DISASM_DATA); + peek(0x0100 + SP, DISASM_NONE); // It seems that the 650x does not push the address of the next instruction // on the stack it actually pushes the address of the next instruction @@ -3597,10 +3597,10 @@ case 0x40: peek(PC, DISASM_NONE); } { - peek(0x0100 + SP++, DISASM_DATA); - PS(peek(0x0100 + SP++, DISASM_DATA)); - PC = peek(0x0100 + SP++, DISASM_CODE); - PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8); + peek(0x0100 + SP++, DISASM_NONE); + PS(peek(0x0100 + SP++, DISASM_NONE)); + PC = peek(0x0100 + SP++, DISASM_NONE); + PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8); } break; @@ -3610,9 +3610,9 @@ case 0x60: peek(PC, DISASM_NONE); } { - peek(0x0100 + SP++, DISASM_DATA); - PC = peek(0x0100 + SP++, DISASM_CODE); - PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8); + peek(0x0100 + SP++, DISASM_NONE); + PC = peek(0x0100 + SP++, DISASM_NONE); + PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8); peek(PC++, DISASM_CODE); } break; diff --git a/src/emucore/M6502.m4 b/src/emucore/M6502.m4 index 9d05aefff..92448bebd 100644 --- a/src/emucore/M6502.m4 +++ b/src/emucore/M6502.m4 @@ -637,7 +637,7 @@ define(M6502_JMP, `{ define(M6502_JSR, `{ uInt8 low = peek(PC++, DISASM_CODE); - peek(0x0100 + SP, DISASM_DATA); + peek(0x0100 + SP, DISASM_NONE); // It seems that the 650x does not push the address of the next instruction // on the stack it actually pushes the address of the next instruction @@ -838,16 +838,16 @@ define(M6502_RRA, `{ }') define(M6502_RTI, `{ - peek(0x0100 + SP++, DISASM_DATA); - PS(peek(0x0100 + SP++, DISASM_DATA)); - PC = peek(0x0100 + SP++, DISASM_CODE); - PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8); + peek(0x0100 + SP++, DISASM_NONE); + PS(peek(0x0100 + SP++, DISASM_NONE)); + PC = peek(0x0100 + SP++, DISASM_NONE); + PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8); }') define(M6502_RTS, `{ - peek(0x0100 + SP++, DISASM_DATA); - PC = peek(0x0100 + SP++, DISASM_CODE); - PC |= ((uInt16)peek(0x0100 + SP, DISASM_CODE) << 8); + peek(0x0100 + SP++, DISASM_NONE); + PC = peek(0x0100 + SP++, DISASM_NONE); + PC |= ((uInt16)peek(0x0100 + SP, DISASM_NONE) << 8); peek(PC++, DISASM_CODE); }')