zilmar
|
a8c8e751fc
|
Core: log the block code to the asm log file
|
2024-10-24 12:11:15 +10:30 |
|
zilmar
|
885d31f275
|
Core: Update Map_MemoryStack to pass gp by reference
|
2024-10-24 12:01:14 +10:30 |
|
zilmar
|
440894992a
|
Core: remove the BreakPoint in handling ExitReason_CheckPCAlignment
|
2024-10-24 11:58:53 +10:30 |
|
zilmar
|
65ede5e3e8
|
Core: If jumping to an unaligned address then generate an exception
|
2024-10-24 10:31:48 +10:30 |
|
zilmar
|
4a42466559
|
Core: In compiling a block be able to trace the time to compile
|
2024-10-24 10:04:45 +10:30 |
|
zilmar
|
5750d3df80
|
Core: Have only one function to do what R4300iOp::ExecuteOps and R4300iOp::ExecuteCPU was doing
|
2024-10-24 09:59:41 +10:30 |
|
zilmar
|
c39582b9ed
|
Core: Make sure CX86RecompilerOps::SPECIAL_AND can not write to R0
|
2024-10-17 18:42:45 +10:30 |
|
zilmar
|
a38467cc19
|
Core: Reset Memory Stack Pos In recompiler after running interpter code at non rdram location
|
2024-10-17 18:40:37 +10:30 |
|
zilmar
|
f708e5c0b2
|
Core: Check recompiler memory based on the function size
|
2024-10-17 15:05:48 +10:30 |
|
zilmar
|
45e52e1d2a
|
Core: in SPECIAL_SYSCALL, SPECIAL_BREAK only exit the block is the stage is PIPELINE_STAGE_NORMAL
|
2024-10-17 14:12:46 +10:30 |
|
zilmar
|
a2e479a705
|
Core: Handle paths with non-ASCII characters
|
2024-10-10 18:01:10 +10:30 |
|
zilmar
|
c176f61aac
|
Core: Normalize Plugin dir
|
2024-10-10 10:12:53 +10:30 |
|
zilmar
|
30090e5db7
|
Core: in CX86Ops::CX86Ops set setLogger to nullptr if not logging
|
2024-10-03 16:22:42 +09:30 |
|
zilmar
|
9e53b161a4
|
Cote Update PeripheralInterfaceHandler::PI_DMA_WRITE to handle misaligned, end of page test
|
2024-10-03 14:38:04 +09:30 |
|
zilmar
|
08e1b3b39b
|
fix up clang formatting
|
2024-09-26 18:54:54 +09:30 |
|
zilmar
|
62bf10e505
|
Core: Have fpu ops check the input of fs and ft at the same time
|
2024-09-26 16:38:25 +09:30 |
|
zilmar
|
dc4fa211b0
|
Core: Clean up RDRAM/RI Registers
|
2024-09-26 12:59:32 +09:30 |
|
zilmar
|
544d6ba1b9
|
Core: Normalize Path for RomList_RomListCache
|
2024-09-26 07:30:26 +09:30 |
|
zilmar
|
aaa6fc8082
|
Core: Add $(Platform) to the output directory
|
2024-09-05 17:54:58 +09:30 |
|
zilmar
|
6816ff4435
|
RSP: Disable a lot of ops that are not functioning correctly in the recompiler
|
2024-07-20 17:05:11 +09:30 |
|
zilmar
|
73c9174ce9
|
Core: Remove Memory exception filer
|
2024-06-13 11:50:06 +09:30 |
|
zilmar
|
91f9cdaaa7
|
Core: Change the Program counter to be 64bit
|
2024-06-06 14:09:12 +09:30 |
|
zilmar
|
77ac4744a5
|
Core: Make sure fpu stack is being cleared
|
2024-05-23 11:52:58 +09:30 |
|
zilmar
|
0ff0d5234c
|
Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify
|
2024-05-23 11:43:19 +09:30 |
|
zilmar
|
ec714cd90d
|
Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax)
|
2024-05-23 11:41:15 +09:30 |
|
zilmar
|
3baaa829de
|
Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables
|
2024-05-16 16:34:17 +09:30 |
|
zilmar
|
ae21e10a8d
|
Core: Increase the minimal amount of free space in recompiler memory
|
2024-05-16 16:15:28 +09:30 |
|
zilmar
|
a1f46356fb
|
Core: remove usage of g_RecompPos
|
2024-05-16 16:08:23 +09:30 |
|
zilmar
|
7f18773b5b
|
Core: Add CX86RegInfo::GetFPStatusReg
|
2024-05-16 15:51:04 +09:30 |
|
zilmar
|
13bd420b2a
|
Core: Sync FP status register in advanced block linking
|
2024-05-16 15:45:38 +09:30 |
|
zilmar
|
703a09d034
|
Core: Remove protecting memory option
|
2024-05-09 17:56:28 +09:30 |
|
zilmar
|
f478f16269
|
Core: Clear FP Status flag in recompiler on BC1FL and BC1TL
|
2024-05-09 10:55:38 +09:30 |
|
zilmar
|
4c23e7af2c
|
Core: Remove ChangeFPURegFormat, Load_FPR_ToTop
|
2024-05-02 17:21:01 +09:30 |
|
zilmar
|
c786bc3251
|
Core: Force Fpu exception in recompiler
|
2024-05-02 16:34:13 +09:30 |
|
zilmar
|
b3e8b760e6
|
Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function
|
2024-05-02 15:48:43 +09:30 |
|
zilmar
|
dd0f7ad776
|
Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword
|
2024-05-02 15:46:03 +09:30 |
|
zilmar
|
046f27ce98
|
Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT
|
2024-04-25 20:47:02 +09:30 |
|
zilmar
|
627b4d6103
|
Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv
|
2024-04-25 20:41:03 +09:30 |
|
zilmar
|
b92e6bd752
|
Core: get to COP1_S_ROUND_L and COP1_S_CVT_L to use COP1_S_CVT
|
2024-04-25 20:22:47 +09:30 |
|
zilmar
|
d658477cf4
|
Core: get CX86RecompilerOps::Compile_Branch to clear status flags
|
2024-04-18 17:31:19 +09:30 |
|
zilmar
|
b313640831
|
Core: In CX86RegInfo::Map_TempReg allow it to use FPStatusReg if it is unprotected
|
2024-04-18 17:28:23 +09:30 |
|
zilmar
|
1172b6e04d
|
Core: get CX86RecompilerOps::SW_Const on 0x04300000 to call MIPSInterfaceHandler directly
|
2024-04-18 17:21:39 +09:30 |
|
zilmar
|
38738b783d
|
Core: get CX86RecompilerOps::COP1_S_CVT to handle NewFormat == CRegInfo::FPU_Qword
|
2024-04-18 17:11:45 +09:30 |
|
zilmar
|
7dc53e51cf
|
Core: Get CompileCheckFPUInput to better handle 64bit value check
|
2024-04-18 17:00:29 +09:30 |
|
zilmar
|
a9875b7d61
|
Core: Get COP1_D_CMP to map eax before CompileInitFpuOperation
|
2024-04-18 16:58:18 +09:30 |
|
zilmar
|
3203322d8b
|
Core: Get COP1_D_CVT_L to use COP1_S_CVT
|
2024-04-18 16:56:30 +09:30 |
|
zilmar
|
9e73771815
|
Core: Use the new COP1_S_CVT in COP1_D_ROUND_L, COP1_D_TRUNC_L, COP1_D_CEIL_L, COP1_D_FLOOR_L
|
2024-04-18 16:51:53 +09:30 |
|
zilmar
|
fe87142657
|
Core: CX86RecompilerOps::COP1_S_CMP should allocate eax before calling CompileInitFpuOperation
|
2024-04-18 16:42:48 +09:30 |
|
zilmar
|
4071b52810
|
Core: CX86RegInfo::UnMap_X86reg should fail on a protected register
|
2024-04-18 16:41:03 +09:30 |
|
zilmar
|
79f7aa9927
|
Core: CX86RegInfo::UnMap_FPStatusReg should unprotect register before trying to free it
|
2024-04-18 16:34:49 +09:30 |