François Berder
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560c49ba2d
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Core: Fix N64 disk IPL load address check (#2401)
The IPL load address check always evaluated to false due
to a wrong operator.
Signed-off-by: Francois Berder <fberder@outlook.fr>
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2024-03-21 17:52:09 +10:30 |
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zilmar
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45fb2ad965
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Core: In X86RecompilerOps::CompileCheckFPUResult64 make sure RegPointer is protected
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2024-03-21 17:44:53 +10:30 |
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zilmar
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2811b63ff0
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Core: Update CX86RecompilerOps::COP1_D_CVT_S and CX86RecompilerOps::COP1_D_CVT_W
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2024-03-21 17:41:29 +10:30 |
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zilmar
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33d2722841
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Core: fix up CX86RecompilerOps::COP1_D_FLOOR_W
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2024-03-21 17:40:14 +10:30 |
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zilmar
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9a9c2e5439
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Core: Update CX86RecompilerOps::COP1_D_CEIL_W
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2024-03-21 17:32:12 +10:30 |
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zilmar
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401efae0d9
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Core: fix up CX86RecompilerOps::COP1_D_ROUND_W
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2024-03-21 17:28:16 +10:30 |
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zilmar
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772a20f07d
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Core: Update CX86RecompilerOps::COP1_D_SQRT
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2024-03-21 17:15:10 +10:30 |
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zilmar
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87c732b65d
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Core: update CX86RecompilerOps::COP1_D_NEG
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2024-03-21 17:14:00 +10:30 |
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zilmar
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ece5e30a80
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Core: create a function to handle .d recompiler opcodes that use fd and fs
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2024-03-21 17:13:16 +10:30 |
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zilmar
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5133d47502
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Core: Make the FPU double ops to be modularized so it is a simple function call for an opcode
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2024-03-14 18:12:58 +10:30 |
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zilmar
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98b1bddc64
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Core: Get COP1_D_ADD, COP1_D_SUB, COP1_D_DIV, COP1_D_ABS, COP1_D_SQRT
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2024-03-07 21:12:57 +10:30 |
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zilmar
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97ec1f533b
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Core: Make sure precision is set to 53bit
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2024-03-07 20:52:24 +10:30 |
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zilmar
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190c408019
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Core: Fix clang formatting in x86/x86RecompilerOps.cpp
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2024-02-29 16:06:56 +10:30 |
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zilmar
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f7aa6ef6cb
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Core: Fix up CX86RecompilerOps::COP1_D_MUL so it can work with exceptions
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2024-02-29 15:16:29 +10:30 |
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zilmar
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25dc3ed36f
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Core: CRegisters::TriggerAddressException should only generate a TLB_MOD on writes
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2024-02-29 15:13:14 +10:30 |
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zilmar
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d2649f7a13
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Core: Some clean up recompiler ops
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2024-02-22 19:56:23 +10:30 |
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zilmar
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fae0b81e21
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Core: Have CX86RegInfo::Map_TempReg generate a BreakPoint if it mapping a protected register
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2024-02-22 19:41:10 +10:30 |
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zilmar
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e082cd55df
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Core: Get COP1_D_TRUNC_W to work in recompiler
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2024-02-15 21:08:49 +10:30 |
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zilmar
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2559d23592
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Core: Make sure CX86RecompilerOps::CompileInitFpuOperation clears flag for FE_INVALID
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2024-02-15 21:02:27 +10:30 |
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zilmar
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46f6fae40f
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Core: get CompileCheckFPUInput to be able to handle 32bit and 64bit
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2024-02-15 21:00:12 +10:30 |
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zilmar
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2014237ed6
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Core: Update Round.w.s, trunc.w.s, ceil.w.s, floor.w.s to work with exceptions in the recompiler
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2024-02-08 19:34:14 +10:30 |
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zilmar
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ad1a2a2d9a
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Core: Update neg.s for the recompiler
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2024-02-01 18:17:03 +10:30 |
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zilmar
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b6671adf5d
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Core: Update abs.s for recompiler
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2024-02-01 18:15:33 +10:30 |
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zilmar
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bc3fe0fe16
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Core: Handle FP Status Reg being mapped better
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2024-01-25 18:46:39 +10:30 |
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zilmar
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7707f9c7b2
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Core: Fix up mov.s and mov.d for correct behaviour in the recompiler
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2024-01-25 16:25:06 +10:30 |
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zilmar
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272144dc37
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Core: check timer on cop1 unusable
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2024-01-25 16:23:03 +10:30 |
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zilmar
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f0f44c67f4
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Core: Make mov.s the same as mov.d
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2024-01-25 15:32:56 +10:30 |
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zilmar
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7ed94b653e
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Core: Get CX86RecompilerOps::COP1_S_CVT_D to be able to work with exceptions
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2024-01-18 17:09:27 +10:30 |
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zilmar
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2231e8d6c0
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Core: Remove usage of fpclassify from R4300iOp::CheckFPUResult64
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2024-01-18 16:53:14 +10:30 |
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zilmar
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71067ccdc4
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Rsp: Change how SP_SEMAPHORE_REG to how it use to be before adding multithread RSP
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2024-01-11 18:17:05 +10:30 |
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zilmar
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5c56f9df83
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RSP: Update the size of the skip in the length for DMA
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2024-01-11 17:50:23 +10:30 |
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zilmar
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4dc3e35bb4
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Core: Update CX86RecompilerOps::COP1_S_SQRT to work with fpu exceptions
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2024-01-04 16:51:11 +10:30 |
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zilmar
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f8089f565e
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Core: Unmap FPU_Float with writing to m_FPR_UDW
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2024-01-04 14:40:42 +10:30 |
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zilmar
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552b8f744a
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Core: update Format_Name to match FPU_STATE
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2024-01-04 13:11:21 +10:30 |
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zilmar
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6ca8333d39
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Core: Get CX86RecompilerOps::COP1_S_CMP to work with exceptions
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2024-01-04 12:39:51 +10:30 |
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zilmar
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c9d2bbd221
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Core: CX86RecompilerOps::COP1_CF should be able use the mapped FPStatusReg if is mapped
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2024-01-04 12:37:06 +10:30 |
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zilmar
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0998f0ff0e
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Core: Add being able to get FPU_FloatLow from CX86RegInfo::FPRValuePointer
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2024-01-04 12:32:55 +10:30 |
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zilmar
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23cff4d7c5
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Core: Add x86 asm opcode Jnp
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2024-01-04 12:31:26 +10:30 |
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zilmar
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91a8a828d7
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Core: CX86RegInfo::FPRValuePointer when the format is FPU_Dword it should be using m_FPR_UW
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2024-01-04 12:01:21 +10:30 |
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zilmar
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320769d991
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Core: CX86Ops::OrConstToVariable should be a dword_ptr not a word_ptr
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2024-01-04 10:33:07 +10:30 |
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zilmar
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dafa1fb24d
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Core: Have COP1_W_CVT_S handle the initialization of exceptions
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2023-12-28 11:19:06 +10:30 |
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zilmar
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17288c90c0
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Core: Reset pipeline in CX86RecompilerOps::CompileCheckFPUResult32
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2023-12-28 10:23:18 +10:30 |
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zilmar
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e2306e3541
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Core: Get COP1_S_CVT_W to handle inexact
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2023-12-28 09:21:53 +10:30 |
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zilmar
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8399fdb893
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Core: Clear the Divide-by-zero flag
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2023-12-21 21:24:33 +10:30 |
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zilmar
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d14a639a62
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Core: Implement COP1_S_DIV with fpu exceptions
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2023-12-21 14:11:29 +10:30 |
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zilmar
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8e54ec8c8e
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Core: CompileCheckFPUInput32 and CompileCheckFPUResult32 should not be updating esp since using callthis
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2023-12-21 14:10:21 +10:30 |
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zilmar
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b263ee10b0
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Core: In CX86RecompilerOps::CompileLoadMemoryValue instead of checking write to rt being 0 instead use WritesGPR() since LDC1 F0 rt is 0 but it is not writing to r0
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2023-12-21 10:41:16 +10:30 |
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zilmar
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1810bfda5c
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Core: Handle unaligned CX86RecompilerOps::CompileLoadMemoryValue for 64bit ops
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2023-12-21 10:38:49 +10:30 |
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zilmar
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2c1610cfe2
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Core: fix up some of the commented out debugging code in CX86RecompilerOps::PreCompileOpcode
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2023-12-21 10:37:27 +10:30 |
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zilmar
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6610ae3058
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Core: Have R4300iInstruction in CRecompilerOpsBase
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2023-12-21 10:34:03 +10:30 |