Commit Graph

4611 Commits

Author SHA1 Message Date
zilmar 1924030266 RSP: Move compile functions into CRSPRecompilerOps 2024-08-02 22:00:01 +09:30
zilmar 2904d3641d RSP: Create RSP system class and move all interpter ops in to RSPOp class 2024-08-02 09:00:38 +09:30
zilmar dab432e7bd RSP: clean up LDV 2024-07-20 19:10:36 +09:30
zilmar 9d7b391487 RSP: Fix up LSV in the recompiler 2024-07-20 17:09:41 +09:30
zilmar 7c2655c544 RSP: Remove some unused functions and turn Reordering and Sections off by default 2024-07-20 17:08:20 +09:30
zilmar 6816ff4435 RSP: Disable a lot of ops that are not functioning correctly in the recompiler 2024-07-20 17:05:11 +09:30
zilmar 13fb8cd2da RSP: In Compile_Opcode_SQV Cheat the op instead of causing an unknown opcode 2024-07-12 15:23:59 +09:30
zilmar 564926163c RSP: in Compile_Opcode_SSV cheat the op instead of generating an unknown opcode 2024-07-12 15:07:23 +09:30
zilmar 8c6856f1c8 RSP: Have Compile_SW handle DMEM overflow better 2024-07-12 15:04:18 +09:30
zilmar 6e4852fc78 RSP: have Compile_LW handle DMEM overflow better 2024-07-12 15:02:46 +09:30
zilmar e43d697476 RSP: Handle lwu inside IsRegisterConstant 2024-07-12 15:01:05 +09:30
zilmar 7b013c3deb RSP: Reset secondary buffer to start on ResetJumpTables 2024-07-12 14:59:16 +09:30
zilmar e2243fe8eb RSP: Make sure RSP block ends with a ret 2024-07-06 19:36:10 +09:30
zilmar 9b38977b31 RSP: Fix up recompiler jumps JAL, BLTZAL, BGEZAL 2024-07-06 19:33:10 +09:30
zilmar 4125774be8 RSP: Add Vector_VRNDN and fix up compile jump table 2024-07-06 19:08:20 +09:30
zilmar 2a149beb69 RSP: Clean up #ifdef in Recompiler 2024-07-06 19:04:50 +09:30
zilmar 38599b79fe RSP: Compile_Cop2_MF check for write to r0 2024-07-06 18:53:19 +09:30
zilmar 1af8570315 RSP: Set max log size as 300mb 2024-07-06 18:51:55 +09:30
zilmar 0e0f0f7618 RSP: JALR update rd after updating the PC 2024-06-27 16:57:31 +09:30
zilmar 06eea03d7d RSP: DelaySlotAffectBranch should clamp PC 2024-06-27 16:34:19 +09:30
zilmar 661ec98bb3 RSP: User crc32 for crc of imem 2024-06-27 16:25:13 +09:30
zilmar 96a4c2c926 RSP: Used the wrong reg for write to r0 check on some ops 2024-06-20 21:41:52 +09:30
zilmar abfb896142 RSP: Add Compile_Vector_VRNDP, Compile_Vector_VMULQ, Compile_Opcode_LWV 2024-06-20 19:22:57 +09:30
zilmar 90c0beb01e RSP: Add Compile_Vector_Reserved 2024-06-20 17:34:37 +09:30
zilmar 35aeeb6285 RSP: Handle writing to r0 better in recompiler 2024-06-20 17:28:51 +09:30
zilmar bb042406be RSP: Add const to mmx and sse terms 2024-06-13 20:50:54 +09:30
zilmar 303af24bde RSP: Better handle delay slot at 0xFFC 2024-06-13 14:54:44 +09:30
zilmar c3d6ed1a0c RSP: Have the code be able to loop 2024-06-13 14:23:59 +09:30
zilmar 7161a6f591 RSP: Handle break in delay slot 2024-06-13 12:55:23 +09:30
zilmar d3411809f7 RSP: Get Recompiler to use LWU 2024-06-13 12:34:28 +09:30
zilmar 73c9174ce9 Core: Remove Memory exception filer 2024-06-13 11:50:06 +09:30
Summate 65a9097980
Allowing a paste into a number field to be trimmed automatically (#2414)
The specific issue I experienced is that Excel/LibreOffice Calc add a newline when you copy the contents of a single cell. This is bad behavior and they should provide a copy option that does not do that, but alas, it's much harder to get that into those applications. This behavior made it impossible to paste an otherwise-valid hex address into the Project64 fields without first putting it into Notepad, deleting the newline, recopying, and then doing the paste from there. If the field was simply text, you can go into the field edit and shift + home to select all and then do a copy, but that does not work for a formula. When you edit the file, it shows the formula instead. Therefore, you have absolutely no way of working around this except pasting it somewhere else and removing the newline manually.

In principle, there's no reason why you wouldn't trim the ends at least. Whitespace on either end is useless to you. However, content being after the newline should be rejected as it was before.

There were two secondary issues in the pasting code that are fixed here: One is that it only sort of collapsed single spaces. So if you had more than one space, spaces still would have ended up in the result. Actually I think the semantics were slightly more insidious, <space><number> would have turned into <number><same number> effectively. The only thing it did was remove the space by duplicating the number. If you had two spaces, then it would have ended up with e.g. <space><number><same number>. The only case where this wouldn't have happened is a space at the end which would have been preserved in the paste.

Secondly, it mutated the clipboard data directly. This would have lead to confusing results where multiple pastes would have had clipboard data in the clipboard itself move from, for example, two spaces to a single space to no spaces at all. The better solution is to preprocess to figure out how big we ultimately want our space-less result to be and stamp out the copy ourselves skipping anything we don't want. Leave the clipboard alone.

If it's desired to preserve single spaces only in the middle, the code will need to be modified a bit.

Co-authored-by: Summate <summate.ssbm@gmail.com>
2024-06-06 14:22:26 +09:30
MegaMech 0761ad4a83
Fix implementation of quad3d for f3dex 0.95 on pj64 video plugin (#2427)
* Update ucode01.cpp

* Fix quad3d implementation for f3dex 0.95

* Fix compile
2024-06-06 14:20:46 +09:30
zilmar 91f9cdaaa7 Core: Change the Program counter to be 64bit 2024-06-06 14:09:12 +09:30
zilmar 77ac4744a5 Core: Make sure fpu stack is being cleared 2024-05-23 11:52:58 +09:30
zilmar 0ff0d5234c Core: In R4300iOp::CheckFPUInput64 check values directly instead of using fpclassify 2024-05-23 11:43:19 +09:30
zilmar ec714cd90d Core: in CX86RecompilerOps::CompileCheckFPUResult64 protect RegPointer before Map_TempReg(asmjit::x86::eax) 2024-05-23 11:41:15 +09:30
zilmar 3baaa829de Core: Remove g_TLBLoadAddress, g_TLBStoreAddress global variables 2024-05-16 16:34:17 +09:30
zilmar ae21e10a8d Core: Increase the minimal amount of free space in recompiler memory 2024-05-16 16:15:28 +09:30
zilmar a1f46356fb Core: remove usage of g_RecompPos 2024-05-16 16:08:23 +09:30
zilmar 7f18773b5b Core: Add CX86RegInfo::GetFPStatusReg 2024-05-16 15:51:04 +09:30
zilmar 13bd420b2a Core: Sync FP status register in advanced block linking 2024-05-16 15:45:38 +09:30
zilmar 703a09d034 Core: Remove protecting memory option 2024-05-09 17:56:28 +09:30
zilmar f478f16269 Core: Clear FP Status flag in recompiler on BC1FL and BC1TL 2024-05-09 10:55:38 +09:30
zilmar 4c23e7af2c Core: Remove ChangeFPURegFormat, Load_FPR_ToTop 2024-05-02 17:21:01 +09:30
zilmar c786bc3251 Core: Force Fpu exception in recompiler 2024-05-02 16:34:13 +09:30
zilmar b3e8b760e6 Core: get COP1_S_TRUNC_L, COP1_S_CEIL_L, COP1_S_FLOOR_L, COP1_W_CVT_S, COP1_W_CVT_D, COP1_L_CVT_S, COP1_L_CVT_D to use COP1_S_CVT function 2024-05-02 15:48:43 +09:30
zilmar dd0f7ad776 Core: Have CX86RecompilerOps::COP1_S_CVT be able to handle the old format of FPU_Dword and FPU_Qword 2024-05-02 15:46:03 +09:30
zilmar 046f27ce98 Core: fix up some bugs in CX86RecompilerOps::COP1_S_CVT 2024-04-25 20:47:02 +09:30
zilmar 627b4d6103 Core: Get CompileCheckFPUInput check InvalidValueMax, InvalidMinValue in conv 2024-04-25 20:41:03 +09:30