2023-06-15 11:39:44 +00:00
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#include "cpu/RSPOpcode.h"
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2023-06-29 01:33:55 +00:00
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#include "RspTypes.h"
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2016-01-27 09:11:59 +00:00
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2021-01-19 05:58:59 +00:00
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extern uint32_t CompilePC, NextInstruction, JumpTableSize;
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extern bool ChangedPC;
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2016-01-27 09:11:59 +00:00
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2023-06-01 11:46:23 +00:00
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#define CompilerWarning \
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if (ShowErrors) DisplayError
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2023-06-01 11:46:23 +00:00
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#define High16BitAccum 1
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#define Middle16BitAccum 2
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#define Low16BitAccum 4
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#define EntireAccum (Low16BitAccum | Middle16BitAccum | High16BitAccum)
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bool WriteToAccum(int Location, int PC);
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bool WriteToVectorDest(DWORD DestReg, int PC);
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bool UseRspFlags(int PC);
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bool DelaySlotAffectBranch(DWORD PC);
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bool CompareInstructions(DWORD PC, RSPOpcode * Top, RSPOpcode * Bottom);
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bool IsOpcodeBranch(DWORD PC, RSPOpcode RspOp);
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bool IsOpcodeNop(DWORD PC);
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2023-06-29 02:59:07 +00:00
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bool IsNextInstructionMmx(DWORD PC);
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bool IsRegisterConstant(DWORD Reg, DWORD * Constant);
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void RSP_Element2Mmx(int MmxReg);
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void RSP_MultiElement2Mmx(int MmxReg1, int MmxReg2);
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2023-06-01 11:46:23 +00:00
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#define MainBuffer 0
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#define SecondaryBuffer 1
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DWORD RunRecompilerCPU(DWORD Cycles);
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void BuildRecompilerCPU(void);
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void CompilerRSPBlock(void);
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void CompilerToggleBuffer(void);
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bool RSP_DoSections(void);
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typedef struct
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{
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DWORD StartPC, CurrPC; // Block start
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struct
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{
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DWORD TargetPC; // Target for this unknown branch
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DWORD * X86JumpLoc; // Our x86 DWORD to fill
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} BranchesToResolve[200]; // Branches inside or outside block
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DWORD ResolveCount; // Branches with NULL jump table
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} RSP_BLOCK;
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extern RSP_BLOCK CurrentBlock;
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typedef struct
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{
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bool bIsRegConst[32]; // bool toggle for constant
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DWORD MipsRegConst[32]; // Value of register 32-bit
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DWORD BranchLabels[250];
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DWORD LabelCount;
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DWORD BranchLocations[250];
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DWORD BranchCount;
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} RSP_CODE;
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extern RSP_CODE RspCode;
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#define IsRegConst(i) (RspCode.bIsRegConst[i])
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#define MipsRegConst(i) (RspCode.MipsRegConst[i])
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typedef struct
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{
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bool mmx, mmx2, sse; // CPU specs and compiling
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bool bFlags; // RSP flag analysis
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bool bReOrdering; // Instruction reordering
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bool bSections; // Microcode sections
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bool bDest; // Vector destination toggle
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bool bAccum; // Accumulator toggle
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bool bGPRConstants; // Analyze GPR constants
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bool bAlignVector; // Align known vector loads
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bool bAudioUcode; // Audio microcode analysis
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} RSP_COMPILER;
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extern RSP_COMPILER Compiler;
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#define IsMmxEnabled (Compiler.mmx)
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#define IsMmx2Enabled (Compiler.mmx2)
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#define IsSseEnabled (Compiler.sse)
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