Guest memory is now mapped into a shared memory/file mapping, for use
with fastmem.
64-bit and 128-bit arguments are passed by register/value instead of by
reference/address.
LDL/LDR/SDL/SDR now use 64-bit GPRs instead of SSE.
These have no meaning in x64 (apart from throwing compiler warnings),
and we don't do 32-bit anymore. Also saves needing to include
`Pcsx2Defs.h` in files which don't otherwise need it.
Another small piece of #3451
Moves all VTLB pointer manipulation into dedicated classes for the purpose, which should allow the algorithm to be changed much more easily in the future (only have to change the class and recVTLB.cpp assembly since it obviously can't use the class)
Also some of the functions that manipulated the VTLB previously used POINTER_SIGN_BIT (which 1 << 63 on 64-bit) while others used a sign-extended 0x80000000. Now they all use the same one (POINTER_SIGN_BIT)
Note: recVTLB.cpp was updated to keep it compiling but the rest of the x86-64 compatibility changes were left out
Also, Cache.cpp seems to assume VTLB entries are both sides of the union at the same time, which is impossible. Does anyone know how this actually worked (and if this patch breaks it) or if it never worked properly in the first place?
Allocate memory in an x86-64-compatible way
Another part of #3451
Note: While this shouldn't change how anything works, it's been the #1 source of breakage of 32-bit builds in #3451 (it was the cause for the failure of win32 to allocate memory and the failure of linux-32 afterward) so we should definitely make sure it gets tested
see #3523 for more information
Add GoemonUnloadTlb function that invalidate TLB cache.
Currently the function is only used on the interpreter. It fixes TLB error after a reload of data.
Next step: porting to the recompiler
When a tlb miss is detected current instruction must be skipped. We need
to immediately switch to the handler
Typical instruction bug case:
lw a0, 0x8(a0)
a0 mustn't be loaded if we have a miss
v2: create a dedicated exception for tlb miss
v3:
* rename exception to CancelInstruction
* add a basic state machine on the exec loop so we keep same behavior
for eeloadReplaceOSDSYS and eeGameStarting
v4: remove assert
VTLB does some nonsense with signed integers for the pointers.
We've got to make sure to set the signed bit in the correct bit on 64bit pointers so it works.
This has no functional change on x86_32, it's mostly just changing a few pointer to u32 conversions to uptr and sptr.
I can not yet confirm if this runs on x86_64, but compiling is enough of an issue currently.
Tlb mapping is stored @0x3d5580 (GoemonTlb[150])
The function that will populate the tlb is around pc = 0x356250, ra = 0x33ad48
The idea is to add a callback on 0x33ad48 block that will populate the tlb based on
ee mem content.
Note: The hack is based on previous Virtual PS2 => Physical PS2 LUT
note: automatic gamefixes are done after done after the init that why code was splitted.
note2: The LUT is 4MB and only used for only 1 game. So I only allocate it when the gamefix is
enabled
* Fix some issue with the new debugger on linux
* Enable the previous tlb miss fix on the interpreter
* disable the building of po by default. It pollute too much my env.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5914 96395faa-99c1-11dd-bbfe-3dabce05a288
Currenty code isn't activated because it will crash any game that do a tlb miss (with the recompiler)
However if you activate the code with the interpreter, the exception will be fired and new tlb setting
will be loaded => got nice picture with "Bouken Jidai Katsugeki"
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5911 96395faa-99c1-11dd-bbfe-3dabce05a288
Translators note: I save previous translation but a careful review is mandatory
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@5366 96395faa-99c1-11dd-bbfe-3dabce05a288
Threading VU1 took a lot of rewrites and new code to make possible (MTGS, microVU, gifUnit...), but we finally got to the point where it was feasible, and now we've done it! (so now everyone can stop complaining that pcsx2 only takes advantages of 2 cores :p).
The speedups in the games that benefit from it are great if you have a cpu with 3+ cores (generally a 10~45% speedup), however games that are GS limited can be a slowdown (especially on dual core cpu's).
The option can be found in the speedhacks section as "MTVU (Multi-Threaded microVU1)". And when enabled it should should show the VU thread-time percentage on the title bar window (Like we currently do for EE/GS/UI threads).
It is listed as a speedhack because in order for threading VU1 to have been a speedup, we need to assume that games will not send gif packets containing Signal/Finish/Label commands from path 1 (vu1's xgkick). The good news is very-few games ever do this, so the compatibility of MTVU is very high (a game that does do this will likely hang).
Note: vs2010 builds and Linux builds need to be updated to include "MTVU.h" and "MTVU.cpp".
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4865 96395faa-99c1-11dd-bbfe-3dabce05a288
Note: Once DoA2 is ingame (start of fight), you can switch to the EE Rec until the fight is over with good speed! Hopefully one day someone will be brave enough to implement it on the rec side so you dont have to mess about :P
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@4309 96395faa-99c1-11dd-bbfe-3dabce05a288
* Added some bounds checking to debug builds for VTLB mappings.
* Fixed a VU mapping bug that caused boot crashing
* Fixed some startup, shutdown, and reset resource management.
git-svn-id: http://pcsx2.googlecode.com/svn/branches/newHostVM@4021 96395faa-99c1-11dd-bbfe-3dabce05a288
* Includes a minor tweak to DMAC.h - removed tDMA_TADR / tDMA_MADR / etc. and replaced them with a single tDMAC_ADDR class.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3644 96395faa-99c1-11dd-bbfe-3dabce05a288
* Now using SSE for all hardware register reads and writes (mainly MFIFO stuff) [don't expect a speedup, really -- its more of a code simplification in this case].
* [refactoring] Changed the EE Memory (vtlb) to use the u128 type instead of u64 for the 128-bit loads/stores (see mem128_t typedef)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3626 96395faa-99c1-11dd-bbfe-3dabce05a288
* Added __fi and __ri, which are abbreviations for __forceinline and __releaseinline.
* Added some static qualifiers to functions in mVU, MMI ops, and others where appropriate.
* Removed some unnecessary __fastcall qualifiers (since GCC gets funny sometimes when you combine __fastcall and inlining).
* Made _1mb, _16mb, _1gb values common to all emulation code (moved from newVif/mvu to Common.h) -- they're useful! :)
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3624 96395faa-99c1-11dd-bbfe-3dabce05a288
* Some minor exception/error handling fixes and improvements.
DevNote: the BOOT2 elf loader fix is still a hackfix. I documented the proper fix for mimicking PS2 BOOT2 parsing, but not in a mood to do the full proper implementation right now.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3442 96395faa-99c1-11dd-bbfe-3dabce05a288
I also re-implemented R5900 runtime exception handling for TLB Miss and such (devbuilds only, for now).
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3335 96395faa-99c1-11dd-bbfe-3dabce05a288
* Added DX11 support. DX11 enabled cards now give a +~40% speedup
* New SSE-X instructions we invented for PCSX2. Give a +200% speedup even on old CPUs.
* Full 64bit support. If you have 64 bit windows, be prepared for a 300% speed up.
* Implemented new DMAC, so far we have ~15 games that show improvements.
* Added support for USB-enabled vibrators. Feel the full pleasure of gaming, now also with PCSX2!
* SPU2-X now decodes Dolby Digital 7.1!
* Please test to find any bugs in the 24-thread code, it's a bit complex so some tiny bugs might have crept in.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@3000 96395faa-99c1-11dd-bbfe-3dabce05a288
Connor McLaughlin