mirror of https://github.com/PCSX2/pcsx2.git
Reverted all changes for now :( The roundmode approach is fine for the ADD and SUB opcodes, but without fixing all arithmetic opcodes, we'll still get wrong results. As usual with pcsx2 the last commit made some games worse due to that...
git-svn-id: http://pcsx2-playground.googlecode.com/svn/trunk@421 a6443dda-0b58-4228-96e9-037be469359c
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@ -84,10 +84,6 @@ static u32 PCSX2_ALIGNED16(s_pos[4]) = { 0x7fffffff, 0xffffffff, 0xffffffff, 0xf
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static u32 fpucw = 0x007f;
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static u32 fpucw = 0x007f;
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static u32 fpucws = 0;
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static u32 fpucws = 0;
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static u32 chop = 0x0000FFC0;
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static u32 nearest = 0x00009FC0; //might use the global one later
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void recCOP1_BC1()
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void recCOP1_BC1()
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{
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{
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recCP1BC1[_Rt_]();
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recCP1BC1[_Rt_]();
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@ -645,9 +641,7 @@ int recCommutativeOp(int info, int regd, int op)
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void recADD_S_xmm(int info)
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void recADD_S_xmm(int info)
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{
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{
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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SSE_LDMXCSR ((uptr)&chop);
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ClampValues2(recCommutativeOp(info, EEREC_D, 0));
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ClampValues2(recCommutativeOp(info, EEREC_D, 0));
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SSE_LDMXCSR ((uptr)&nearest);
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//REC_FPUOP(ADD_S);
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//REC_FPUOP(ADD_S);
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}
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}
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@ -1519,9 +1513,7 @@ FPURECOMPILE_CONSTCODE(MSUBA_S, XMMINFO_WRITEACC|XMMINFO_READACC|XMMINFO_READS|X
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void recMUL_S_xmm(int info)
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void recMUL_S_xmm(int info)
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{
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{
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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SSE_LDMXCSR ((uptr)&chop);
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ClampValues(recCommutativeOp(info, EEREC_D, 1));
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ClampValues(recCommutativeOp(info, EEREC_D, 1));
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SSE_LDMXCSR ((uptr)&nearest);
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}
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}
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FPURECOMPILE_CONSTCODE(MUL_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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FPURECOMPILE_CONSTCODE(MUL_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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@ -1529,9 +1521,7 @@ FPURECOMPILE_CONSTCODE(MUL_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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void recMULA_S_xmm(int info)
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void recMULA_S_xmm(int info)
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{
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{
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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//AND32ItoM((uptr)&fpuRegs.fprc[31], ~(FPUflagO|FPUflagU)); // Clear O and U flags
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SSE_LDMXCSR ((uptr)&chop);
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ClampValues(recCommutativeOp(info, EEREC_ACC, 1));
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ClampValues(recCommutativeOp(info, EEREC_ACC, 1));
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SSE_LDMXCSR ((uptr)&nearest);
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}
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}
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FPURECOMPILE_CONSTCODE(MULA_S, XMMINFO_WRITEACC|XMMINFO_READS|XMMINFO_READT);
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FPURECOMPILE_CONSTCODE(MULA_S, XMMINFO_WRITEACC|XMMINFO_READS|XMMINFO_READT);
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@ -1617,9 +1607,7 @@ void recSUBop(int info, int regd)
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void recSUB_S_xmm(int info)
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void recSUB_S_xmm(int info)
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{
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{
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SSE_LDMXCSR ((uptr)&chop);
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recSUBop(info, EEREC_D);
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recSUBop(info, EEREC_D);
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SSE_LDMXCSR ((uptr)&nearest);
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}
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}
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FPURECOMPILE_CONSTCODE(SUB_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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FPURECOMPILE_CONSTCODE(SUB_S, XMMINFO_WRITED|XMMINFO_READS|XMMINFO_READT);
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