mirror of https://github.com/PCSX2/pcsx2.git
Cleanup commit:
- Remove code dealing with "PROCESS_EE_MMX" ( not used without "EEINST_MMX" ) git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2454 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
parent
c91b68c6a0
commit
b26d7fad2f
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@ -35,7 +35,7 @@
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#define MODE_NOFRAME 0x40 // when allocating x86regs, don't use ebp reg
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#define MODE_NOFRAME 0x40 // when allocating x86regs, don't use ebp reg
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#define MODE_8BITREG 0x80 // when allocating x86regs, use only eax, ecx, edx, and ebx
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#define MODE_8BITREG 0x80 // when allocating x86regs, use only eax, ecx, edx, and ebx
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#define PROCESS_EE_MMX 0x01
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//#define PROCESS_EE_MMX 0x01 // removed
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#define PROCESS_EE_XMM 0x02
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#define PROCESS_EE_XMM 0x02
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// currently only used in FPU
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// currently only used in FPU
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@ -201,18 +201,12 @@ static const int MEM_XMMTAG = 0x8000; // mmreg is xmmreg
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#define EEINST_LIVE1 2 // if cur var's next 32 bits are needed
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#define EEINST_LIVE1 2 // if cur var's next 32 bits are needed
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#define EEINST_LIVE2 4 // if cur var's next 64 bits are needed
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#define EEINST_LIVE2 4 // if cur var's next 64 bits are needed
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#define EEINST_LASTUSE 8 // if var isn't written/read anymore
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#define EEINST_LASTUSE 8 // if var isn't written/read anymore
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//#define EEINST_MMX 0x10 // removed
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#define EEINST_XMM 0x20 // var will be used in xmm ops
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#define EEINST_XMM 0x20 // var will be used in xmm ops
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#define EEINST_USED 0x40
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#define EEINST_USED 0x40
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// MMX is disabled by setting this to 0, which seems a general speedup and fixes several
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// random tlb miss problems.
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#define EEINST_MMX 0
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#define EEINSTINFO_COP1 1
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#define EEINSTINFO_COP1 1
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#define EEINSTINFO_COP2 2
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#define EEINSTINFO_COP2 2
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#define EEINSTINFO_MMX EEINST_MMX
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#define EEINSTINFO_XMM EEINST_XMM
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struct EEINST
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struct EEINST
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{
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{
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File diff suppressed because it is too large
Load Diff
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@ -59,24 +59,6 @@ void recADDI_(int info)
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EEINST_SETSIGNEXT(_Rt_);
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EEINST_SETSIGNEXT(_Rt_);
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EEINST_SETSIGNEXT(_Rs_);
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EEINST_SETSIGNEXT(_Rs_);
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if ( info & PROCESS_EE_MMX ) {
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if ( _Imm_ != 0 ) {
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if ( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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PADDDMtoR(EEREC_T, (uptr)recGetImm64(0, _Imm_));
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if ( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(EEREC_T, _Rt_, 0);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else {
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// just move and sign extend
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if ( !EEINST_HASLIVE1(_Rs_) ) {
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if ( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRMMXtoMMX(EEREC_T, _Rt_, EEREC_S, _Rs_);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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else if ( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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}
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return;
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}
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if ( _Rt_ == _Rs_ ) {
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if ( _Rt_ == _Rs_ ) {
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if ( EEINST_ISLIVE1(_Rt_) )
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if ( EEINST_ISLIVE1(_Rt_) )
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{
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{
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@ -125,18 +107,6 @@ void recDADDI_(int info)
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{
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{
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pxAssert( !(info&PROCESS_EE_XMM) );
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pxAssert( !(info&PROCESS_EE_XMM) );
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if( info & PROCESS_EE_MMX ) {
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if( _Imm_ != 0 ) {
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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PADDQMtoR(EEREC_T, (uptr)recGetImm64(-(_Imm_ < 0), _Imm_));
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}
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else {
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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}
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return;
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}
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if( _Rt_ == _Rs_ ) {
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if( _Rt_ == _Rs_ ) {
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ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
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ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
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ADC32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
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ADC32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
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@ -184,22 +154,7 @@ extern u32 s_sltone;
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void recSLTIU_(int info)
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void recSLTIU_(int info)
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{
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{
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if( info & PROCESS_EE_MMX ) {
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MOV32ItoR(EAX, 1);
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if( EEINST_ISSIGNEXT(_Rs_) ) {
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recSLTmemconstt(EEREC_T, EEREC_S, (uptr)recGetImm64(0, ((s32)_Imm_)^0x80000000), 0);
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EEINST_SETSIGNEXT(_Rt_);
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return;
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}
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if( info & PROCESS_EE_MODEWRITES ) {
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MOVQRtoM((u32)&cpuRegs.GPR.r[_Rs_], EEREC_S);
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if( mmxregs[EEREC_S].reg == MMX_GPR+_Rs_ ) mmxregs[EEREC_S].mode &= ~MODE_WRITE;
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}
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mmxregs[EEREC_T].mode |= MODE_WRITE; // in case EEREC_T==EEREC_S
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}
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if( info & PROCESS_EE_MMX ) MOVDMtoMMX(EEREC_T, (u32)&s_sltone);
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else MOV32ItoR(EAX, 1);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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j8Ptr[0] = JB8( 0 );
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j8Ptr[0] = JB8( 0 );
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@ -209,17 +164,15 @@ void recSLTIU_(int info)
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j8Ptr[1] = JB8(0);
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j8Ptr[1] = JB8(0);
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x86SetJ8(j8Ptr[2]);
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x86SetJ8(j8Ptr[2]);
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if( info & PROCESS_EE_MMX ) PXORRtoR(EEREC_T, EEREC_T);
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XOR32RtoR(EAX, EAX);
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else XOR32RtoR(EAX, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[1]);
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x86SetJ8(j8Ptr[1]);
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if( !(info & PROCESS_EE_MMX) ) {
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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EEINST_SETSIGNEXT(_Rt_);
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EEINST_SETSIGNEXT(_Rt_);
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}
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}
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@ -233,24 +186,8 @@ void recSLTI_const()
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void recSLTI_(int info)
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void recSLTI_(int info)
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{
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{
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if( info & PROCESS_EE_MMX) {
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if( EEINST_ISSIGNEXT(_Rs_) ) {
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recSLTmemconstt(EEREC_T, EEREC_S, (uptr)recGetImm64(0, _Imm_), 1);
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EEINST_SETSIGNEXT(_Rt_);
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return;
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}
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if( info & PROCESS_EE_MODEWRITES ) {
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MOVQRtoM((u32)&cpuRegs.GPR.r[_Rs_], EEREC_S);
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if( mmxregs[EEREC_S].reg == MMX_GPR+_Rs_ ) mmxregs[EEREC_S].mode &= ~MODE_WRITE;
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}
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mmxregs[EEREC_T].mode |= MODE_WRITE; // in case EEREC_T==EEREC_S
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}
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// test silent hill if modding
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// test silent hill if modding
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if( info & PROCESS_EE_MMX ) MOVDMtoMMX(EEREC_T, (u32)&s_sltone);
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MOV32ItoR(EAX, 1);
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else MOV32ItoR(EAX, 1);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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CMP32ItoM( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ], _Imm_ >= 0 ? 0 : 0xffffffff);
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j8Ptr[0] = JL8( 0 );
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j8Ptr[0] = JL8( 0 );
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@ -260,17 +197,15 @@ void recSLTI_(int info)
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j8Ptr[1] = JB8(0);
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j8Ptr[1] = JB8(0);
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x86SetJ8(j8Ptr[2]);
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x86SetJ8(j8Ptr[2]);
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if( info & PROCESS_EE_MMX ) PXORRtoR(EEREC_T, EEREC_T);
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XOR32RtoR(EAX, EAX);
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else XOR32RtoR(EAX, EAX);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[0]);
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x86SetJ8(j8Ptr[1]);
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x86SetJ8(j8Ptr[1]);
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if( !(info & PROCESS_EE_MMX) ) {
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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if( EEINST_ISLIVE1(_Rt_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
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else EEINST_RESETHASLIVE1(_Rt_);
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else EEINST_RESETHASLIVE1(_Rt_);
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}
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EEINST_SETSIGNEXT(_Rt_);
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EEINST_SETSIGNEXT(_Rt_);
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}
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}
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@ -284,21 +219,6 @@ void recANDI_const()
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void recLogicalOpI(int info, int op)
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void recLogicalOpI(int info, int op)
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{
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{
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if( info & PROCESS_EE_MMX ) {
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SetMMXstate();
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if( _ImmU_ != 0 ) {
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if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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LogicalOpMtoR(EEREC_T, (uptr)recGetImm64(0, _ImmU_), op);
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}
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else {
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if( op == 0 ) PXORRtoR(EEREC_T, EEREC_T);
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else if( EEREC_T != EEREC_S ) MOVQRtoR(EEREC_T, EEREC_S);
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}
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return;
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}
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if ( _ImmU_ != 0 )
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if ( _ImmU_ != 0 )
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{
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{
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if( _Rt_ == _Rs_ ) {
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if( _Rt_ == _Rs_ ) {
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@ -58,76 +58,7 @@ REC_SYS_DEL(BGEZALL, 31);
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void recSetBranchEQ(int info, int bne, int process)
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void recSetBranchEQ(int info, int bne, int process)
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{
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{
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if( info & PROCESS_EE_MMX ) {
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if( info & PROCESS_EE_XMM ) {
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int t0reg;
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SetMMXstate();
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if( process & PROCESS_CONSTS ) {
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if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) {
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_deleteMMXreg(_Rt_, 1);
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mmxregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_T);
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}
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_flushConstReg(_Rs_);
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PCMPEQDMtoR(t0reg, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
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if( t0reg != EEREC_T ) _freeMMXreg(t0reg);
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}
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else if( process & PROCESS_CONSTT ) {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_) ) {
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_deleteMMXreg(_Rs_, 1);
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mmxregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_S);
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}
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_flushConstReg(_Rt_);
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PCMPEQDMtoR(t0reg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
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if( t0reg != EEREC_S ) _freeMMXreg(t0reg);
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}
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else {
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if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_) ) {
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_deleteMMXreg(_Rs_, 1);
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mmxregs[EEREC_S].inuse = 0;
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t0reg = EEREC_S;
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PCMPEQDRtoR(t0reg, EEREC_T);
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}
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else if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) {
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_deleteMMXreg(_Rt_, 1);
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mmxregs[EEREC_T].inuse = 0;
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t0reg = EEREC_T;
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PCMPEQDRtoR(t0reg, EEREC_S);
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}
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else {
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t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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MOVQRtoR(t0reg, EEREC_S);
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PCMPEQDRtoR(t0reg, EEREC_T);
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}
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if( t0reg != EEREC_S && t0reg != EEREC_T ) _freeMMXreg(t0reg);
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}
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PMOVMSKBMMXtoR(EAX, t0reg);
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_eeFlushAllUnused();
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CMP8ItoR( EAX, 0xff );
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if( bne ) j32Ptr[ 1 ] = JE32( 0 );
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else j32Ptr[ 0 ] = j32Ptr[ 1 ] = JNE32( 0 );
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}
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else if( info & PROCESS_EE_XMM ) {
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int t0reg;
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int t0reg;
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if( process & PROCESS_CONSTS ) {
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if( process & PROCESS_CONSTS ) {
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@ -430,28 +430,6 @@ void recMOVZtemp_const()
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void recMOVZtemp_consts(int info)
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void recMOVZtemp_consts(int info)
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{
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{
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if( info & PROCESS_EE_MMX ) {
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u32* mem;
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int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
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PXORRtoR(t0reg, t0reg);
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PCMPEQDRtoR(t0reg, EEREC_T);
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PMOVMSKBMMXtoR(EAX, t0reg);
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CMP8ItoR(EAX, 0xff);
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j8Ptr[ 0 ] = JNE8( 0 );
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if( g_cpuFlushedConstReg & (1<<_Rs_) )
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mem = &cpuRegs.GPR.r[_Rs_].UL[0];
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else
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mem = recGetImm64(g_cpuConstRegs[_Rs_].UL[1], g_cpuConstRegs[_Rs_].UL[0]);
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MOVQMtoR(EEREC_D, (uptr)mem);
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x86SetJ8( j8Ptr[ 0 ] );
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_freeMMXreg(t0reg);
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return;
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}
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
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OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
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OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
||||||
j8Ptr[ 0 ] = JNZ8( 0 );
|
j8Ptr[ 0 ] = JNZ8( 0 );
|
||||||
|
@ -464,11 +442,6 @@ void recMOVZtemp_consts(int info)
|
||||||
|
|
||||||
void recMOVZtemp_constt(int info)
|
void recMOVZtemp_constt(int info)
|
||||||
{
|
{
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
if( EEREC_D != EEREC_S ) MOVQRtoR(EEREC_D, EEREC_S);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( _hasFreeXMMreg() ) {
|
if( _hasFreeXMMreg() ) {
|
||||||
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||||
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
MOVQMtoR(t0reg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
|
||||||
|
@ -487,22 +460,6 @@ void recMOVZtemp_(int info)
|
||||||
{
|
{
|
||||||
int t0reg = -1;
|
int t0reg = -1;
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
|
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
PXORRtoR(t0reg, t0reg);
|
|
||||||
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
||||||
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
||||||
CMP8ItoR(EAX, 0xff);
|
|
||||||
j8Ptr[ 0 ] = JNE8( 0 );
|
|
||||||
|
|
||||||
MOVQRtoR(EEREC_D, EEREC_S);
|
|
||||||
x86SetJ8( j8Ptr[ 0 ] );
|
|
||||||
|
|
||||||
_freeMMXreg(t0reg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( _hasFreeXMMreg() )
|
if( _hasFreeXMMreg() )
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||||
|
|
||||||
|
@ -550,29 +507,6 @@ void recMOVNtemp_const()
|
||||||
|
|
||||||
void recMOVNtemp_consts(int info)
|
void recMOVNtemp_consts(int info)
|
||||||
{
|
{
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
|
|
||||||
u32* mem;
|
|
||||||
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
PXORRtoR(t0reg, t0reg);
|
|
||||||
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
||||||
|
|
||||||
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
||||||
CMP8ItoR(EAX, 0xff);
|
|
||||||
j8Ptr[ 0 ] = JE8( 0 );
|
|
||||||
|
|
||||||
if( g_cpuFlushedConstReg & (1<<_Rs_) )
|
|
||||||
mem = &cpuRegs.GPR.r[_Rs_].UL[0];
|
|
||||||
else
|
|
||||||
mem = recGetImm64(g_cpuConstRegs[_Rs_].UL[1], g_cpuConstRegs[_Rs_].UL[0]);
|
|
||||||
|
|
||||||
MOVQMtoR(EEREC_D, (uptr)mem);
|
|
||||||
x86SetJ8( j8Ptr[ 0 ] );
|
|
||||||
|
|
||||||
_freeMMXreg(t0reg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
OR32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
||||||
j8Ptr[ 0 ] = JZ8( 0 );
|
j8Ptr[ 0 ] = JZ8( 0 );
|
||||||
|
@ -603,22 +537,6 @@ void recMOVNtemp_(int info)
|
||||||
{
|
{
|
||||||
int t0reg=-1;
|
int t0reg=-1;
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
|
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
PXORRtoR(t0reg, t0reg);
|
|
||||||
PCMPEQDRtoR(t0reg, EEREC_T);
|
|
||||||
PMOVMSKBMMXtoR(EAX, t0reg);
|
|
||||||
CMP8ItoR(EAX, 0xff);
|
|
||||||
j8Ptr[ 0 ] = JE8( 0 );
|
|
||||||
|
|
||||||
MOVQRtoR(EEREC_D, EEREC_S);
|
|
||||||
x86SetJ8( j8Ptr[ 0 ] );
|
|
||||||
|
|
||||||
_freeMMXreg(t0reg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( _hasFreeXMMreg() )
|
if( _hasFreeXMMreg() )
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||||
|
|
||||||
|
|
|
@ -310,7 +310,6 @@ void recMULT_const()
|
||||||
void recMULTUsuper(int info, int upper, int process);
|
void recMULTUsuper(int info, int upper, int process);
|
||||||
void recMULTsuper(int info, int upper, int process)
|
void recMULTsuper(int info, int upper, int process)
|
||||||
{
|
{
|
||||||
pxAssert( !(info&PROCESS_EE_MMX) );
|
|
||||||
if( _Rd_ ) EEINST_SETSIGNEXT(_Rd_);
|
if( _Rd_ ) EEINST_SETSIGNEXT(_Rd_);
|
||||||
EEINST_SETSIGNEXT(_Rs_);
|
EEINST_SETSIGNEXT(_Rs_);
|
||||||
EEINST_SETSIGNEXT(_Rt_);
|
EEINST_SETSIGNEXT(_Rt_);
|
||||||
|
@ -333,7 +332,7 @@ void recMULTsuper(int info, int upper, int process)
|
||||||
|
|
||||||
//void recMULT_process(int info, int process)
|
//void recMULT_process(int info, int process)
|
||||||
//{
|
//{
|
||||||
// if( EEINST_ISLIVE64(XMMGPR_HI) || !(info&PROCESS_EE_MMX) ) {
|
// if( EEINST_ISLIVE64(XMMGPR_HI) ) {
|
||||||
// recMULTsuper(info, 0, process);
|
// recMULTsuper(info, 0, process);
|
||||||
// }
|
// }
|
||||||
// else {
|
// else {
|
||||||
|
@ -376,28 +375,19 @@ void recMULTsuper(int info, int upper, int process)
|
||||||
void recMULT_(int info)
|
void recMULT_(int info)
|
||||||
{
|
{
|
||||||
//recMULT_process(info, 0);
|
//recMULT_process(info, 0);
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 0, 0);
|
||||||
recMULTsuper(info, 0, 0);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 0, 0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recMULT_consts(int info)
|
void recMULT_consts(int info)
|
||||||
{
|
{
|
||||||
//recMULT_process(info, PROCESS_CONSTS);
|
//recMULT_process(info, PROCESS_CONSTS);
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 0, PROCESS_CONSTS);
|
||||||
recMULTsuper(info, 0, PROCESS_CONSTS);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 0, PROCESS_CONSTS);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recMULT_constt(int info)
|
void recMULT_constt(int info)
|
||||||
{
|
{
|
||||||
//recMULT_process(info, PROCESS_CONSTT);
|
//recMULT_process(info, PROCESS_CONSTT);
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 0, PROCESS_CONSTT);
|
||||||
recMULTsuper(info, 0, PROCESS_CONSTT);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 0, PROCESS_CONSTT);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
// don't set XMMINFO_WRITED|XMMINFO_WRITELO|XMMINFO_WRITEHI
|
// don't set XMMINFO_WRITED|XMMINFO_WRITELO|XMMINFO_WRITEHI
|
||||||
|
@ -417,82 +407,17 @@ void recMULTUsuper(int info, int upper, int process)
|
||||||
EEINST_SETSIGNEXT(_Rs_);
|
EEINST_SETSIGNEXT(_Rs_);
|
||||||
EEINST_SETSIGNEXT(_Rt_);
|
EEINST_SETSIGNEXT(_Rt_);
|
||||||
|
|
||||||
if( (info & PROCESS_EE_MMX) ) {
|
|
||||||
|
|
||||||
if( !_Rd_ ) {
|
|
||||||
// need some temp reg
|
|
||||||
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
pxAssert( EEREC_D == 0 );
|
|
||||||
info |= PROCESS_EE_SET_D(t0reg);
|
|
||||||
}
|
|
||||||
|
|
||||||
if( process & PROCESS_CONSTS ) {
|
|
||||||
u32* ptempmem = _eeGetConstReg(_Rs_);
|
|
||||||
if( EEREC_D != EEREC_T ) MOVQRtoR(EEREC_D, EEREC_T);
|
|
||||||
PMULUDQMtoR(EEREC_D, (u32)ptempmem);
|
|
||||||
}
|
|
||||||
else if( process & PROCESS_CONSTT ) {
|
|
||||||
u32* ptempmem = _eeGetConstReg(_Rt_);
|
|
||||||
if( EEREC_D != EEREC_S ) MOVQRtoR(EEREC_D, EEREC_S);
|
|
||||||
PMULUDQMtoR(EEREC_D, (u32)ptempmem);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( EEREC_D == EEREC_S ) PMULUDQRtoR(EEREC_D, EEREC_T);
|
|
||||||
else if( EEREC_D == EEREC_T ) PMULUDQRtoR(EEREC_D, EEREC_S);
|
|
||||||
else {
|
|
||||||
MOVQRtoR(EEREC_D, EEREC_S);
|
|
||||||
PMULUDQRtoR(EEREC_D, EEREC_T);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
recWritebackHILOMMX(info, EEREC_D, 1, upper);
|
|
||||||
|
|
||||||
if( !_Rd_ ) _freeMMXreg(EEREC_D);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
if( info & PROCESS_EE_MODEWRITES ) {
|
|
||||||
MOVQRtoM((u32)&cpuRegs.GPR.r[_Rs_].UL[0], EEREC_S);
|
|
||||||
if( mmxregs[EEREC_S].reg == MMX_GPR+_Rs_ ) mmxregs[EEREC_S].mode &= ~MODE_WRITE;
|
|
||||||
}
|
|
||||||
if( info & PROCESS_EE_MODEWRITET ) {
|
|
||||||
MOVQRtoM((u32)&cpuRegs.GPR.r[_Rt_].UL[0], EEREC_T);
|
|
||||||
if( mmxregs[EEREC_T].reg == MMX_GPR+_Rt_ ) mmxregs[EEREC_T].mode &= ~MODE_WRITE;
|
|
||||||
}
|
|
||||||
_deleteMMXreg(MMX_GPR+_Rd_, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
if( process & PROCESS_CONSTS ) {
|
if( process & PROCESS_CONSTS ) {
|
||||||
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rs_].UL[0] );
|
||||||
|
MUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
MOVD32MMXtoR(EDX, EEREC_T);
|
|
||||||
MUL32R(EDX);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
MUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
}
|
}
|
||||||
else if( process & PROCESS_CONSTT) {
|
else if( process & PROCESS_CONSTT) {
|
||||||
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
||||||
|
MUL32M( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
MOVD32MMXtoR(EDX, EEREC_S);
|
|
||||||
MUL32R(EDX);
|
|
||||||
}
|
|
||||||
else
|
|
||||||
MUL32M( (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||||||
MOVD32MMXtoR(EAX, EEREC_S);
|
MUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
MOVD32MMXtoR(EDX, EEREC_T);
|
|
||||||
MUL32R(EDX);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
||||||
MUL32M( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
recWritebackHILO(info, 1, upper);
|
recWritebackHILO(info, 1, upper);
|
||||||
|
@ -526,26 +451,17 @@ void recMULT1_const()
|
||||||
|
|
||||||
void recMULT1_(int info)
|
void recMULT1_(int info)
|
||||||
{
|
{
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 1, 0);
|
||||||
recMULTsuper(info, 1, 0);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 1, 0);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recMULT1_consts(int info)
|
void recMULT1_consts(int info)
|
||||||
{
|
{
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 1, PROCESS_CONSTS);
|
||||||
recMULTsuper(info, 1, PROCESS_CONSTS);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 1, PROCESS_CONSTS);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recMULT1_constt(int info)
|
void recMULT1_constt(int info)
|
||||||
{
|
{
|
||||||
if( (g_pCurInstInfo->regs[XMMGPR_HI]&EEINST_LIVE2) || !(info&PROCESS_EE_MMX) ) {
|
recMULTsuper(info, 1, PROCESS_CONSTT);
|
||||||
recMULTsuper(info, 1, PROCESS_CONSTT);
|
|
||||||
}
|
|
||||||
else recMULTUsuper(info, 1, PROCESS_CONSTT);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
EERECOMPILE_CODE0(MULT1, XMMINFO_READS|XMMINFO_READT|(_Rd_?XMMINFO_WRITED:0) );
|
EERECOMPILE_CODE0(MULT1, XMMINFO_READS|XMMINFO_READT|(_Rd_?XMMINFO_WRITED:0) );
|
||||||
|
|
|
@ -61,55 +61,22 @@ void recSLL_const()
|
||||||
|
|
||||||
void recSLLs_(int info, int sa)
|
void recSLLs_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg, t0reg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
rtreg = EEREC_T;
|
if ( sa != 0 )
|
||||||
rdreg = EEREC_D;
|
{
|
||||||
|
SHL32ItoR( EAX, sa );
|
||||||
|
}
|
||||||
|
|
||||||
|
if( EEINST_ISLIVE1(_Rd_) ) {
|
||||||
|
CDQ( );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
if ( sa != 0 )
|
|
||||||
{
|
|
||||||
SHL32ItoR( EAX, sa );
|
|
||||||
}
|
|
||||||
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
CDQ( );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
|
|
||||||
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
EEINST_RESETHASLIVE1(_Rd_);
|
||||||
PSLLDItoR(rdreg, sa);
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ( sa != 0 ) {
|
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
|
|
||||||
// it is a signed shift
|
|
||||||
PSLLDItoR(rdreg, sa);
|
|
||||||
MOVQRtoR(t0reg, rdreg);
|
|
||||||
PSRADItoR(t0reg, 31);
|
|
||||||
|
|
||||||
// take lower dword of rdreg and lower dword of t0reg
|
|
||||||
PUNPCKLDQRtoR(rdreg, t0reg);
|
|
||||||
_freeMMXreg(t0reg);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) _signExtendGPRtoMMX(rdreg, _Rd_, 0);
|
|
||||||
else EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -129,55 +96,19 @@ void recSRL_const()
|
||||||
|
|
||||||
void recSRLs_(int info, int sa)
|
void recSRLs_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
rtreg = EEREC_T;
|
if ( sa != 0 ) SHR32ItoR( EAX, sa);
|
||||||
rdreg = EEREC_D;
|
|
||||||
|
if( EEINST_ISLIVE1(_Rd_) ) {
|
||||||
|
CDQ( );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
if ( sa != 0 ) SHR32ItoR( EAX, sa);
|
|
||||||
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
CDQ( );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
|
|
||||||
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
EEINST_RESETHASLIVE1(_Rd_);
|
||||||
PSRLDItoR(rdreg, sa);
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ( sa != 0 ) {
|
|
||||||
// rdreg already sign extended
|
|
||||||
PSLLQItoR(rdreg, 32);
|
|
||||||
PSRLQItoR(rdreg, 32+sa);
|
|
||||||
// t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
//
|
|
||||||
// // it is a signed shift
|
|
||||||
// PSRLDItoR(rdreg, sa);
|
|
||||||
// MOVQRtoR(t0reg, rdreg);
|
|
||||||
// PSRADItoR(t0reg, 31);
|
|
||||||
//
|
|
||||||
// take lower dword of rdreg and lower dword of t0reg
|
|
||||||
// PUNPCKLDQRtoR(rdreg, t0reg);
|
|
||||||
// _freeMMXreg(t0reg);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) _signExtendGPRtoMMX(rdreg, _Rd_, 0);
|
|
||||||
else EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -197,60 +128,19 @@ void recSRA_const()
|
||||||
|
|
||||||
void recSRAs_(int info, int sa)
|
void recSRAs_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg, t0reg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
rtreg = EEREC_T;
|
if ( sa != 0 ) SAR32ItoR( EAX, sa);
|
||||||
rdreg = EEREC_D;
|
|
||||||
|
if( EEINST_ISLIVE1(_Rd_) ) {
|
||||||
|
CDQ();
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
||||||
}
|
}
|
||||||
else {
|
else {
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
if ( sa != 0 ) SAR32ItoR( EAX, sa);
|
|
||||||
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
CDQ();
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
|
||||||
}
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
|
|
||||||
if( EEINST_ISSIGNEXT(_Rt_) && EEINST_HASLIVE1(_Rt_) ) {
|
|
||||||
PSRADItoR(rdreg, sa);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
EEINST_RESETHASLIVE1(_Rd_);
|
||||||
PSRADItoR(rdreg, sa);
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if ( sa != 0 ) {
|
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
|
|
||||||
// it is a signed shift
|
|
||||||
PSRADItoR(rdreg, sa);
|
|
||||||
MOVQRtoR(t0reg, rdreg);
|
|
||||||
PSRADItoR(rdreg, 31);
|
|
||||||
|
|
||||||
// take lower dword of rdreg and lower dword of t0reg
|
|
||||||
PUNPCKLDQRtoR(t0reg, rdreg);
|
|
||||||
|
|
||||||
// swap regs
|
|
||||||
mmxregs[t0reg] = mmxregs[rdreg];
|
|
||||||
mmxregs[rdreg].inuse = 0;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) _signExtendGPRtoMMX(rdreg, _Rd_, 0);
|
|
||||||
else EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -273,17 +163,11 @@ void recDSLLs_(int info, int sa)
|
||||||
int rtreg, rdreg;
|
int rtreg, rdreg;
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
||||||
rtreg = EEREC_T;
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
||||||
rdreg = EEREC_D;
|
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
||||||
}
|
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
||||||
else {
|
SetMMXstate();
|
||||||
_addNeededMMXreg(MMX_GPR+_Rt_);
|
|
||||||
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
||||||
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
|
||||||
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
||||||
SetMMXstate();
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
||||||
PSLLQItoR(rdreg, sa);
|
PSLLQItoR(rdreg, sa);
|
||||||
|
@ -307,17 +191,11 @@ void recDSRLs_(int info, int sa)
|
||||||
int rtreg, rdreg;
|
int rtreg, rdreg;
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
||||||
rtreg = EEREC_T;
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
||||||
rdreg = EEREC_D;
|
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
||||||
}
|
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
||||||
else {
|
SetMMXstate();
|
||||||
_addNeededMMXreg(MMX_GPR+_Rt_);
|
|
||||||
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
||||||
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
|
||||||
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
||||||
SetMMXstate();
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
||||||
PSRLQItoR(rdreg, sa);
|
PSRLQItoR(rdreg, sa);
|
||||||
|
@ -341,17 +219,11 @@ void recDSRAs_(int info, int sa)
|
||||||
int rtreg, rdreg, t0reg;
|
int rtreg, rdreg, t0reg;
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
||||||
rtreg = EEREC_T;
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
||||||
rdreg = EEREC_D;
|
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
||||||
}
|
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
||||||
else {
|
SetMMXstate();
|
||||||
_addNeededMMXreg(MMX_GPR+_Rt_);
|
|
||||||
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
||||||
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
|
||||||
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
||||||
SetMMXstate();
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
||||||
|
|
||||||
|
@ -397,26 +269,16 @@ void recDSLL32_const()
|
||||||
|
|
||||||
void recDSLL32s_(int info, int sa)
|
void recDSLL32s_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
||||||
rtreg = EEREC_T;
|
if ( sa != 0 )
|
||||||
rdreg = EEREC_D;
|
{
|
||||||
}
|
SHL32ItoR( EAX, sa );
|
||||||
else {
|
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
|
|
||||||
if ( sa != 0 )
|
|
||||||
{
|
|
||||||
SHL32ItoR( EAX, sa );
|
|
||||||
}
|
|
||||||
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
|
|
||||||
return;
|
|
||||||
}
|
}
|
||||||
|
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 0 );
|
||||||
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EAX );
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
PSLLQItoR(rdreg, sa+32);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recDSLL32_(int info)
|
void recDSLL32_(int info)
|
||||||
|
@ -434,25 +296,14 @@ void recDSRL32_const()
|
||||||
|
|
||||||
void recDSRL32s_(int info, int sa)
|
void recDSRL32s_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
||||||
rtreg = EEREC_T;
|
if ( sa != 0 ) SHR32ItoR( EAX, sa );
|
||||||
rdreg = EEREC_D;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
||||||
if ( sa != 0 ) SHR32ItoR( EAX, sa );
|
|
||||||
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
|
if( EEINST_ISLIVE1(_Rd_) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], 0 );
|
||||||
else EEINST_RESETHASLIVE1(_Rd_);
|
else EEINST_RESETHASLIVE1(_Rd_);
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
PSRLQItoR(rdreg, sa+32);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recDSRL32_(int info)
|
void recDSRL32_(int info)
|
||||||
|
@ -470,61 +321,16 @@ void recDSRA32_const()
|
||||||
|
|
||||||
void recDSRA32s_(int info, int sa)
|
void recDSRA32s_(int info, int sa)
|
||||||
{
|
{
|
||||||
int rtreg, rdreg, t0reg;
|
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
||||||
rtreg = EEREC_T;
|
CDQ( );
|
||||||
rdreg = EEREC_D;
|
if ( sa != 0 ) SAR32ItoR( EAX, sa );
|
||||||
}
|
|
||||||
else {
|
|
||||||
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
|
|
||||||
CDQ( );
|
|
||||||
if ( sa != 0 ) SAR32ItoR( EAX, sa );
|
|
||||||
|
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
if( EEINST_ISLIVE1(_Rd_) ) MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
if( EEINST_ISLIVE1(_Rd_) ) MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
|
||||||
else EEINST_RESETHASLIVE1(_Rd_);
|
else EEINST_RESETHASLIVE1(_Rd_);
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( rtreg != rdreg ) MOVQRtoR(rdreg, rtreg);
|
|
||||||
|
|
||||||
if( EEINST_ISSIGNEXT(_Rt_) && EEINST_HASLIVE1(_Rt_) ) {
|
|
||||||
PSRADItoR(rdreg, 31);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
if( !EEINST_ISLIVE1(_Rd_) ) {
|
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
|
||||||
if( sa ) PSRADItoR(rdreg, sa);
|
|
||||||
PUNPCKHDQRtoR(rdreg, rdreg);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
|
|
||||||
t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
MOVQRtoR(t0reg, rtreg);
|
|
||||||
|
|
||||||
// it is a signed shift
|
|
||||||
if( sa ) {
|
|
||||||
PSRADItoR(rdreg, sa);
|
|
||||||
PSRADItoR(t0reg, 31);
|
|
||||||
|
|
||||||
// take higher dword of rdreg and lower dword of t0reg
|
|
||||||
PUNPCKHDQRtoR(rdreg, t0reg);
|
|
||||||
_freeMMXreg(t0reg);
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
// better timing
|
|
||||||
PSRADItoR(rdreg, 31);
|
|
||||||
|
|
||||||
// take higher dword of rdreg and lower dword of t0reg
|
|
||||||
PUNPCKHDQRtoR(t0reg, rdreg);
|
|
||||||
|
|
||||||
// swap
|
|
||||||
mmxregs[t0reg] = mmxregs[rdreg];
|
|
||||||
mmxregs[rdreg].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
void recDSRA32_(int info)
|
void recDSRA32_(int info)
|
||||||
|
@ -545,35 +351,7 @@ int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int
|
||||||
{
|
{
|
||||||
pxAssert( !(info & PROCESS_EE_XMM) );
|
pxAssert( !(info & PROCESS_EE_XMM) );
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
if( forcemmx ) {
|
||||||
*rtreg = EEREC_T;
|
|
||||||
*rdreg = EEREC_D;
|
|
||||||
*rsreg = EEREC_S;
|
|
||||||
|
|
||||||
// make sure to take only low 5 bits of *rsreg
|
|
||||||
if( !(g_pCurInstInfo->regs[_Rs_]&EEINST_LASTUSE) && EEINST_ISLIVE64(_Rs_)) {
|
|
||||||
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
MOVQRtoR(*rstemp, *rsreg);
|
|
||||||
*rsreg = *rstemp;
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( *rsreg != *rdreg ) {
|
|
||||||
_freeMMXreg(*rsreg);
|
|
||||||
mmxregs[*rsreg].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
PANDMtoR(*rsreg, (u32)&s_sa[shift64?2:0]);
|
|
||||||
|
|
||||||
if( EEREC_D == EEREC_S ) {
|
|
||||||
// need to be separate
|
|
||||||
int mmreg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
*rdreg = mmreg;
|
|
||||||
mmxregs[mmreg] = mmxregs[EEREC_S];
|
|
||||||
mmxregs[EEREC_S].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else if( forcemmx ) {
|
|
||||||
_addNeededMMXreg(MMX_GPR+_Rt_);
|
_addNeededMMXreg(MMX_GPR+_Rt_);
|
||||||
_addNeededMMXreg(MMX_GPR+_Rd_);
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
||||||
*rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
*rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
|
||||||
|
@ -596,45 +374,15 @@ int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int
|
||||||
|
|
||||||
void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp, int shift64)
|
void recSetConstShiftV(int info, int* rsreg, int* rdreg, int* rstemp, int shift64)
|
||||||
{
|
{
|
||||||
if( info & PROCESS_EE_MMX ) {
|
_addNeededMMXreg(MMX_GPR+_Rd_);
|
||||||
*rdreg = EEREC_D;
|
*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
||||||
*rsreg = EEREC_S;
|
SetMMXstate();
|
||||||
|
|
||||||
// make sure to take only low 5 bits of *rsreg
|
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
||||||
if( !(g_pCurInstInfo->regs[_Rs_]&EEINST_LASTUSE) && EEINST_ISLIVE64(_Rs_) ) {
|
MOV32MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
||||||
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
AND32ItoR(EAX, shift64?0x3f:0x1f);
|
||||||
MOVQRtoR(*rstemp, *rsreg);
|
MOVD32RtoMMX(*rstemp, EAX);
|
||||||
*rsreg = *rstemp;
|
*rsreg = *rstemp;
|
||||||
}
|
|
||||||
else {
|
|
||||||
if( *rsreg != *rdreg ) {
|
|
||||||
_freeMMXreg(*rsreg);
|
|
||||||
mmxregs[*rsreg].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
PANDMtoR(*rsreg, (u32)&s_sa[shift64?2:0]);
|
|
||||||
|
|
||||||
|
|
||||||
if( EEREC_D == EEREC_S ) {
|
|
||||||
// need to be separate
|
|
||||||
int mmreg = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
*rdreg = mmreg;
|
|
||||||
mmxregs[mmreg] = mmxregs[EEREC_S];
|
|
||||||
mmxregs[EEREC_S].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
else {
|
|
||||||
_addNeededMMXreg(MMX_GPR+_Rd_);
|
|
||||||
*rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
|
|
||||||
SetMMXstate();
|
|
||||||
|
|
||||||
*rstemp = _allocMMXreg(-1, MMX_TEMP, 0);
|
|
||||||
MOV32MtoR(EAX, (u32)&cpuRegs.GPR.r[_Rs_].UL[0]);
|
|
||||||
AND32ItoR(EAX, shift64?0x3f:0x1f);
|
|
||||||
MOVD32RtoMMX(*rstemp, EAX);
|
|
||||||
*rsreg = *rstemp;
|
|
||||||
}
|
|
||||||
|
|
||||||
_flushConstReg(_Rt_);
|
_flushConstReg(_Rt_);
|
||||||
}
|
}
|
||||||
|
@ -650,10 +398,6 @@ void recMoveSignToRd(int info)
|
||||||
EEINST_RESETHASLIVE1(_Rd_);
|
EEINST_RESETHASLIVE1(_Rd_);
|
||||||
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
|
||||||
}
|
}
|
||||||
|
|
||||||
if( info & PROCESS_EE_MMX ) {
|
|
||||||
mmxregs[EEREC_D].inuse = 0;
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|
||||||
//// SLLV
|
//// SLLV
|
||||||
|
@ -670,8 +414,7 @@ void recSLLV_consts(int info)
|
||||||
|
|
||||||
void recSLLV_constt(int info)
|
void recSLLV_constt(int info)
|
||||||
{
|
{
|
||||||
if( (info & PROCESS_EE_MMX) && (info & PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||||||
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
||||||
|
|
||||||
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
||||||
AND32ItoR( ECX, 0x1f );
|
AND32ItoR( ECX, 0x1f );
|
||||||
|
@ -736,8 +479,7 @@ void recSRLV_consts(int info)
|
||||||
|
|
||||||
void recSRLV_constt(int info)
|
void recSRLV_constt(int info)
|
||||||
{
|
{
|
||||||
if( (info & PROCESS_EE_MMX) && (info&PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||||||
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
||||||
|
|
||||||
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
||||||
AND32ItoR( ECX, 0x1f );
|
AND32ItoR( ECX, 0x1f );
|
||||||
|
@ -802,8 +544,7 @@ void recSRAV_consts(int info)
|
||||||
|
|
||||||
void recSRAV_constt(int info)
|
void recSRAV_constt(int info)
|
||||||
{
|
{
|
||||||
if( (info & PROCESS_EE_MMX) && (info&PROCESS_EE_MODEWRITES) ) MOVD32MMXtoR(ECX, EEREC_S);
|
MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
||||||
else MOV32MtoR( ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
|
|
||||||
|
|
||||||
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
MOV32ItoR( EAX, g_cpuConstRegs[_Rt_].UL[0] );
|
||||||
AND32ItoR( ECX, 0x1f );
|
AND32ItoR( ECX, 0x1f );
|
||||||
|
|
Loading…
Reference in New Issue