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Cleanup commit: 

- Remove code dealing with "EEINST_MMX"

git-svn-id: http://pcsx2.googlecode.com/svn/trunk@2453 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
ramapcsx2 2010-01-18 13:36:23 +00:00
parent 9e7d4dc49a
commit c91b68c6a0
10 changed files with 325 additions and 811 deletions
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4
pcsx2/Dump.cpp
View File

@ -227,8 +227,8 @@ void iDumpBlock( int startpc, u8 * ptr )
// write the instruction info
eff.Printf( "\n\nlive0 - %x, live1 - %x, live2 - %x, lastuse - %x\nmmx - %x, xmm - %x, used - %x\n",
EEINST_LIVE0, EEINST_LIVE1, EEINST_LIVE2, EEINST_LASTUSE, EEINST_MMX, EEINST_XMM, EEINST_USED
eff.Printf( "\n\nlive0 - %x, live1 - %x, live2 - %x, lastuse - %x\nxmm - %x, used - %x\n",
EEINST_LIVE0, EEINST_LIVE1, EEINST_LIVE2, EEINST_LASTUSE, EEINST_XMM, EEINST_USED
);
memzero(used);

5
pcsx2/x86/iCore.h
View File

@ -201,8 +201,7 @@ static const int MEM_XMMTAG = 0x8000; // mmreg is xmmreg
#define EEINST_LIVE1 2 // if cur var's next 32 bits are needed
#define EEINST_LIVE2 4 // if cur var's next 64 bits are needed
#define EEINST_LASTUSE 8 // if var isn't written/read anymore
//#define EEINST_MMX 0x10 // var will be used in mmx ops (disabled, see below)
#define EEINST_XMM 0x20 // var will be used in xmm ops (takes precedence
#define EEINST_XMM 0x20 // var will be used in xmm ops
#define EEINST_USED 0x40
// MMX is disabled by setting this to 0, which seems a general speedup and fixes several
@ -219,7 +218,7 @@ struct EEINST
{
u8 regs[34]; // includes HI/LO (HI=32, LO=33)
u8 fpuregs[33]; // ACC=32
u8 info; // extra info, if 1 inst is COP1, 2 inst is COP2. Also uses EEINST_MMX|EEINST_XMM
u8 info; // extra info, if 1 inst is COP1, 2 inst is COP2. Also uses EEINST_XMM
// uses XMMTYPE_ flags; if type == XMMTYPE_TEMP, not used
u8 writeType[3], writeReg[3]; // reg written in this inst, 0 if no reg

99
pcsx2/x86/ir5900tables.cpp
View File

@ -81,14 +81,14 @@ void BSCPropagate::rpropSetRead( int reg, int mask )
pinst.regs[reg] |= EEINST_LASTUSE;
prev.regs[reg] |= EEINST_LIVE0|(mask)|EEINST_USED;
pinst.regs[reg] |= EEINST_USED;
if( reg ) pinst.info = ((mask)&(EEINST_MMX|EEINST_XMM));
if( reg ) pinst.info = ((mask)&EEINST_XMM);
_recFillRegister(pinst, XMMTYPE_GPRREG, reg, 0);
}
template< int live >
void BSCPropagate::rpropSetWrite0( int reg, int mask )
{
prev.regs[reg] &= ~((mask)|live|EEINST_XMM|EEINST_MMX);
prev.regs[reg] &= ~((mask)|live|EEINST_XMM);
if( !(pinst.regs[reg] & EEINST_USED) )
pinst.regs[reg] |= EEINST_LASTUSE;
pinst.regs[reg] |= EEINST_USED;
@ -127,7 +127,7 @@ void BSCPropagate::rpropSetFPURead( int reg, int mask )
pinst.fpuregs[reg] |= EEINST_LASTUSE;
prev.fpuregs[reg] |= EEINST_LIVE0|(mask)|EEINST_USED;
pinst.fpuregs[reg] |= EEINST_USED;
if( reg ) pinst.info = ((mask)&(EEINST_MMX|EEINST_XMM));
if( reg ) pinst.info = ((mask)&EEINST_XMM);
if( reg == XMMFPU_ACC ) _recFillRegister(pinst, XMMTYPE_FPACC, 0, 0);
else _recFillRegister(pinst, XMMTYPE_FPREG, reg, 0);
}
@ -135,7 +135,7 @@ void BSCPropagate::rpropSetFPURead( int reg, int mask )
template< int live >
void BSCPropagate::rpropSetFPUWrite0( int reg, int mask )
{
prev.fpuregs[reg] &= ~((mask)|live|EEINST_XMM|EEINST_MMX);
prev.fpuregs[reg] &= ~((mask)|live|EEINST_XMM);
if( !(pinst.fpuregs[reg] & EEINST_USED) )
pinst.fpuregs[reg] |= EEINST_LASTUSE;
pinst.fpuregs[reg] |= EEINST_USED;
@ -168,15 +168,12 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 2: // SRL
case 3: // SRA
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_MMX);
break;
case 4: // sllv
case 6: // srlv
case 7: // srav
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_MMX);
rpropSetRead(_Rt_, EEINST_MMX);
break;
case 8: // JR
@ -193,7 +190,6 @@ __forceinline void BSCPropagate::rpropSPECIAL()
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rd_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
_recFillRegister(pinst, XMMTYPE_GPRREG, _Rd_, 1);
break;
@ -207,7 +203,7 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 16: // mfhi
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(XMMGPR_HI, (pinst.regs[_Rd_]&(EEINST_MMX|EEINST_REALXMM))|EEINST_LIVE1);
rpropSetRead(XMMGPR_HI, (pinst.regs[_Rd_]&EEINST_REALXMM)|EEINST_LIVE1);
break;
case 17: // mthi
rpropSetWrite(XMMGPR_HI, EEINST_LIVE1);
@ -215,7 +211,7 @@ __forceinline void BSCPropagate::rpropSPECIAL()
break;
case 18: // mflo
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(XMMGPR_LO, (pinst.regs[_Rd_]&(EEINST_MMX|EEINST_REALXMM))|EEINST_LIVE1);
rpropSetRead(XMMGPR_LO, (pinst.regs[_Rd_]&EEINST_REALXMM)|EEINST_LIVE1);
break;
case 19: // mtlo
rpropSetWrite(XMMGPR_LO, EEINST_LIVE1);
@ -226,15 +222,14 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 22: // dsrlv
case 23: // dsrav
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_MMX);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_MMX);
rpropSetRead(_Rt_, EEINST_LIVE1);
break;
//case 24: // mult
// // can do unsigned mult only if HI isn't used
// //using this allocation for temp causes the emu to crash
// //temp = (pinst.regs[XMMGPR_HI]&(EEINST_LIVE0|EEINST_LIVE1))?0:EEINST_MMX;
// //temp = 0;
// temp = 0;
// rpropSetWrite(XMMGPR_LO, EEINST_LIVE1);
// rpropSetWrite(XMMGPR_HI, EEINST_LIVE1);
@ -252,9 +247,6 @@ __forceinline void BSCPropagate::rpropSPECIAL()
// rpropSetWrite(XMMGPR_LO, EEINST_LIVE1);
// rpropSetWrite(XMMGPR_HI, EEINST_LIVE1);
// rpropSetWrite(_Rd_, EEINST_LIVE1);
// rpropSetRead(_Rs_, EEINST_MMX);
// rpropSetRead(_Rt_, EEINST_MMX);
// pinst.info |= EEINST_MMX;
// break;
@ -276,7 +268,7 @@ __forceinline void BSCPropagate::rpropSPECIAL()
rpropSetWrite(XMMGPR_HI, EEINST_LIVE1);
rpropSetRead(_Rs_, 0);
rpropSetRead(_Rt_, 0);
//pinst.info |= EEINST_REALXMM|EEINST_MMX;
//pinst.info |= EEINST_REALXMM;
break;
case 32: // add
@ -286,7 +278,6 @@ __forceinline void BSCPropagate::rpropSPECIAL()
rpropSetWrite(_Rd_, EEINST_LIVE1);
if( _Rs_ ) rpropSetRead(_Rs_, EEINST_LIVE1);
if( _Rt_ ) rpropSetRead(_Rt_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 36: // and
@ -295,29 +286,27 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 39: // nor
// if rd == rs or rt, keep live1
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, (pinst.regs[_Rd_]&EEINST_LIVE1)|EEINST_MMX);
rpropSetRead(_Rt_, (pinst.regs[_Rd_]&EEINST_LIVE1)|EEINST_MMX);
rpropSetRead(_Rs_, (pinst.regs[_Rd_]&EEINST_LIVE1));
rpropSetRead(_Rt_, (pinst.regs[_Rd_]&EEINST_LIVE1));
break;
case 40: // mfsa
rpropSetWrite(_Rd_, EEINST_LIVE1);
break;
case 41: // mtsa
rpropSetRead(_Rs_, EEINST_LIVE1|EEINST_MMX);
rpropSetRead(_Rs_, EEINST_LIVE1);
break;
case 42: // slt
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 43: // sltu
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 44: // dadd
@ -325,16 +314,8 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 46: // dsub
case 47: // dsubu
rpropSetWrite(_Rd_, EEINST_LIVE1);
if( _Rs_ == 0 || _Rt_ == 0 ) {
// just a copy, so don't force mmx
rpropSetRead(_Rs_, (pinst.regs[_Rd_]&EEINST_LIVE1));
rpropSetRead(_Rt_, (pinst.regs[_Rd_]&EEINST_LIVE1));
}
else {
rpropSetRead(_Rs_, (pinst.regs[_Rd_]&EEINST_LIVE1)|EEINST_MMX);
rpropSetRead(_Rt_, (pinst.regs[_Rd_]&EEINST_LIVE1)|EEINST_MMX);
}
pinst.info |= EEINST_MMX;
rpropSetRead(_Rs_, (pinst.regs[_Rd_]&EEINST_LIVE1));
rpropSetRead(_Rt_, (pinst.regs[_Rd_]&EEINST_LIVE1));
break;
// traps
@ -349,20 +330,17 @@ __forceinline void BSCPropagate::rpropSPECIAL()
case 62: // dsrl32
case 63: // dsra32
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_MMX);
pinst.info |= EEINST_MMX;
rpropSetRead(_Rt_, EEINST_LIVE1);
break;
case 60: // dsll32
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_MMX);
pinst.info |= EEINST_MMX;
break;
default:
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1|EEINST_MMX);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_MMX);
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
break;
}
}
@ -377,7 +355,6 @@ __forceinline void BSCPropagate::rpropREGIMM()
case 0: // bltz
case 1: // bgez
rpropSetRead(_Rs_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
@ -387,7 +364,6 @@ __forceinline void BSCPropagate::rpropREGIMM()
_recClearInst(&prev);
prev.info = 0;
rpropSetRead(_Rs_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
@ -469,14 +445,14 @@ __forceinline void BSCPropagate::rpropCP1()
rpropSetFPURead(_Fs_, EEINST_REALXMM);
break;
case 2: // cfc1
rpropSetWrite(_Rt_, EEINST_LIVE1|EEINST_REALXMM|EEINST_MMX);
rpropSetWrite(_Rt_, EEINST_LIVE1|EEINST_REALXMM);
break;
case 4: // mtc1
rpropSetFPUWrite(_Fs_, EEINST_REALXMM);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_REALXMM);
break;
case 6: // ctc1
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_REALXMM|EEINST_MMX);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_REALXMM);
break;
case 8: // bc1
// reset since don't know which path to go
@ -609,7 +585,7 @@ __forceinline void BSCPropagate::rpropMMI()
case 16: // mfhi1
{
rpropSetWrite(_Rd_, EEINST_LIVE1);
int temp = ((pinst.regs[_Rd_]&(EEINST_MMX|EEINST_REALXMM))?EEINST_MMX:EEINST_REALXMM);
int temp = ((pinst.regs[_Rd_]&(EEINST_REALXMM))?0:EEINST_REALXMM);
rpropSetRead(XMMGPR_HI, temp|EEINST_LIVE2);
break;
}
@ -620,7 +596,7 @@ __forceinline void BSCPropagate::rpropMMI()
case 18: // mflo1
{
rpropSetWrite(_Rd_, EEINST_LIVE1);
int temp = ((pinst.regs[_Rd_]&(EEINST_MMX|EEINST_REALXMM))?EEINST_MMX:EEINST_REALXMM);
int temp = ((pinst.regs[_Rd_]&(EEINST_REALXMM))?0:EEINST_REALXMM);
rpropSetRead(XMMGPR_LO, temp|EEINST_LIVE2);
break;
}
@ -631,22 +607,15 @@ __forceinline void BSCPropagate::rpropMMI()
case 24: // mult1
{
int temp = (pinst.regs[XMMGPR_HI]&(EEINST_LIVE2))?0:EEINST_MMX;
rpropSetWrite0<0>(XMMGPR_LO, EEINST_LIVE2);
rpropSetWrite0<0>(XMMGPR_HI, EEINST_LIVE2);
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, temp);
rpropSetRead(_Rt_, temp);
pinst.info |= temp;
break;
}
case 25: // multu1
rpropSetWrite0<0>(XMMGPR_LO, EEINST_LIVE2);
rpropSetWrite0<0>(XMMGPR_HI, EEINST_LIVE2);
rpropSetWrite(_Rd_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_MMX);
rpropSetRead(_Rt_, EEINST_MMX);
pinst.info |= EEINST_MMX;
break;
case 26: // div1
@ -655,7 +624,7 @@ __forceinline void BSCPropagate::rpropMMI()
rpropSetWrite0<0>(XMMGPR_HI, EEINST_LIVE2);
rpropSetRead(_Rs_, 0);
rpropSetRead(_Rt_, 0);
//pinst.info |= EEINST_REALXMM|EEINST_MMX;
//pinst.info |= EEINST_REALXMM;
break;
case 32: // madd1
@ -887,7 +856,7 @@ void BSCPropagate::rprop()
case 5: // bne
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
pinst.info |= EEINST_REALXMM|EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
case 20: // beql
@ -897,7 +866,7 @@ void BSCPropagate::rprop()
prev.info = 0;
rpropSetRead(_Rs_, EEINST_LIVE1);
rpropSetRead(_Rt_, EEINST_LIVE1);
pinst.info |= EEINST_REALXMM|EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
case 6: // blez
@ -916,41 +885,34 @@ void BSCPropagate::rprop()
case 24: // daddi
case 25: // daddiu
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1 | (_Rs_!=0?EEINST_MMX:0)); // This looks like what ZeroFrog wanted; ToDo: Needs checking! (cottonvibes)
rpropSetRead(_Rs_, EEINST_LIVE1);
break;
case 8: // addi
case 9: // addiu
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 10: // slti
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 11: // sltiu
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1);
pinst.info |= EEINST_MMX;
break;
case 12: // andi
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, (_Rs_!=_Rt_?EEINST_MMX:0));
pinst.info |= EEINST_MMX;
break;
case 13: // ori
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1|(_Rs_!=_Rt_?EEINST_MMX:0));
pinst.info |= EEINST_MMX;
rpropSetRead(_Rs_, EEINST_LIVE1);
break;
case 14: // xori
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1|(_Rs_!=_Rt_?EEINST_MMX:0));
pinst.info |= EEINST_MMX;
rpropSetRead(_Rs_, EEINST_LIVE1);
break;
case 15: // lui
@ -982,14 +944,12 @@ void BSCPropagate::rprop()
case 30: // lq
rpropSetWrite(_Rt_, EEINST_LIVE1|EEINST_LIVE2);
rpropSetRead(_Rs_, 0);
pinst.info |= EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
case 31: // sq
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_LIVE2|EEINST_REALXMM);
rpropSetRead(_Rs_, 0);
pinst.info |= EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
@ -997,14 +957,13 @@ void BSCPropagate::rprop()
case 40: case 41: case 42: case 43: case 46:
rpropSetRead(_Rt_, 0);
rpropSetRead(_Rs_, 0);
pinst.info |= EEINST_MMX;
pinst.info |= EEINST_REALXMM;
break;
case 44: // sdl
case 45: // sdr
case 63: // sd
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_MMX|EEINST_REALXMM);
rpropSetRead(_Rt_, EEINST_LIVE1|EEINST_REALXMM);
rpropSetRead(_Rs_, 0);
break;
@ -1025,7 +984,7 @@ void BSCPropagate::rprop()
default:
rpropSetWrite(_Rt_, EEINST_LIVE1);
rpropSetRead(_Rs_, EEINST_LIVE1|(_Rs_!=0?EEINST_MMX:0));
rpropSetRead(_Rs_, EEINST_LIVE1);
break;
}
} // End namespace OpcodeImpl

79
pcsx2/x86/ix86-32/iCore-32.cpp
View File

@ -515,10 +515,8 @@ int _getFreeMMXreg()
for (i=0; i<iREGCNT_MMX; i++) {
if (mmxregs[i].needed) continue;
if (MMX_ISGPR(mmxregs[i].reg)) {
if( !(g_pCurInstInfo->regs[mmxregs[i].reg] & EEINST_MMX) ) {
_freeMMXreg(i);
return i;
}
_freeMMXreg(i);
return i;
}
}
@ -900,27 +898,13 @@ int _signExtendGPRMMXtoMMX(x86MMXRegType to, u32 gprreg, x86MMXRegType from, u32
// from is free for use
SetMMXstate();
if( g_pCurInstInfo->regs[gprreg] & EEINST_MMX ) {
if( EEINST_ISLIVE64(gprfromreg) ) {
_freeMMXreg(from);
}
MOVQRtoR(to, from);
PSRADItoR(from, 31);
PUNPCKLDQRtoR(to, from);
return to;
}
else {
MOVQRtoR(to, from);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], from);
PSRADItoR(from, 31);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], from);
mmxregs[to].inuse = 0;
return -1;
}
pxAssert( false );
MOVQRtoR(to, from);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], from);
PSRADItoR(from, 31);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], from);
mmxregs[to].inuse = 0;
return -1;
}
int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
@ -934,48 +918,17 @@ int _signExtendGPRtoMMX(x86MMXRegType to, u32 gprreg, int shift)
SetMMXstate();
if( g_pCurInstInfo->regs[gprreg] & EEINST_MMX ) {
if( _hasFreeMMXreg() ) {
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);
MOVQRtoR(t0reg, to);
PSRADItoR(to, 31);
if( shift > 0 ) PSRADItoR(t0reg, shift);
PUNPCKLDQRtoR(t0reg, to);
// swap mmx regs.. don't ask
mmxregs[t0reg] = mmxregs[to];
mmxregs[to].inuse = 0;
return t0reg;
}
else {
// will be used in the future as mmx
if( shift > 0 ) PSRADItoR(to, shift);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to);
PSRADItoR(to, 31);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to);
// read again
MOVQMtoR(to, (u32)&cpuRegs.GPR.r[gprreg].UL[0]);
mmxregs[to].mode &= ~MODE_WRITE;
return to;
}
}
else {
if( shift > 0 ) PSRADItoR(to, shift);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to);
PSRADItoR(to, 31);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to);
mmxregs[to].inuse = 0;
return -1;
}
pxAssert( false );
if( shift > 0 ) PSRADItoR(to, shift);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[0], to);
PSRADItoR(to, 31);
MOVDMMXtoM((u32)&cpuRegs.GPR.r[gprreg].UL[1], to);
mmxregs[to].inuse = 0;
return -1;
}
int _allocCheckGPRtoMMX(EEINST* pinst, int reg, int mode)
{
if( pinst->regs[reg] & EEINST_MMX ) return _allocMMXreg(-1, MMX_GPR+reg, mode);
return _checkMMXreg(MMX_GPR+reg, mode);
}

496
pcsx2/x86/ix86-32/iR5900Arit.cpp
View File

@ -89,7 +89,7 @@ void recADD_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) && (!EEINST_ISLIVE1(_Rd_) || !g_cpuConstRegs[ creg ].UL[0]) ) {
if(!g_cpuConstRegs[ creg ].UL[0]) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
@ -189,51 +189,42 @@ void recADD_(int info)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) && !EEINST_ISLIVE1(_Rd_) ) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( _Rd_ == _Rs_ ) {
if( _Rd_ == _Rt_ ) SHL32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 1); // mult by 2
else {
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
}
if( EEINST_ISLIVE1(_Rd_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rd_);
return;
}
else if( _Rd_ == _Rt_ ) {
EEINST_RESETHASLIVE1(_Rd_);
MOVDMtoMMX(mmreg, (int)&cpuRegs.GPR.r[_Rs_].UL[0] );
PADDDMtoR(mmreg, (int)&cpuRegs.GPR.r[_Rt_].UL[0] );
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
if( EEINST_ISLIVE1(_Rd_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rd_);
}
else {
if( _Rd_ == _Rs_ ) {
if( _Rd_ == _Rt_ ) SHL32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], 1); // mult by 2
else {
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( _Rs_ != _Rt_ ) ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
else SHL32ItoR(EAX, 1); // mult by 2
if( EEINST_ISLIVE1(_Rd_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rd_);
return;
}
else if( _Rd_ == _Rt_ ) {
EEINST_RESETHASLIVE1(_Rd_);
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], ECX);
if( EEINST_ISLIVE1(_Rd_) ) _signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ]);
else EEINST_RESETHASLIVE1(_Rd_);
if( EEINST_ISLIVE1(_Rd_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( _Rs_ != _Rt_ ) ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
else SHL32ItoR(EAX, 1); // mult by 2
if( EEINST_ISLIVE1(_Rd_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
else {
EEINST_RESETHASLIVE1(_Rd_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
}
EEINST_RESETHASLIVE1(_Rd_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
}
}
}
}
@ -269,57 +260,48 @@ void recDADD_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
if( g_cpuConstRegs[ creg ].UL[0] == 0 && g_cpuConstRegs[ creg ].UL[1] == 0 && _hasFreeMMXreg() ) {
// copy
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ]);
if( g_cpuConstRegs[ creg ].UD[0] ) PADDQMtoR(mmreg, (u32)_eeGetConstReg(creg));
if( EEINST_ISLIVE1(_Rd_) ) MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ]);
else {
MOVDMtoMMX(mmreg, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ]);
EEINST_RESETHASLIVE1(_Rd_);
}
}
else {
if( g_cpuConstRegs[ creg ].UL[0] == 0 && g_cpuConstRegs[ creg ].UL[1] == 0 && _hasFreeMMXreg() ) {
// copy
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
if( EEINST_ISLIVE1(_Rd_) ) MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ]);
else {
MOVDMtoMMX(mmreg, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ]);
if( _Rd_ == vreg ) {
if( EEINST_ISLIVE1(_Rd_) && (g_cpuConstRegs[ creg ].UL[ 0 ] || g_cpuConstRegs[ creg ].UL[ 1 ]) ) {
ADD32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ creg ].UL[ 0 ] );
ADC32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[ creg ].UL[ 1 ] );
}
else if( g_cpuConstRegs[ creg ].UL[ 0 ] ) {
EEINST_RESETHASLIVE1(_Rd_);
ADD32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ creg ].UL[ 0 ] );
}
return;
}
else {
if( _Rd_ == vreg ) {
if( EEINST_ISLIVE1(_Rd_) && (g_cpuConstRegs[ creg ].UL[ 0 ] || g_cpuConstRegs[ creg ].UL[ 1 ]) ) {
ADD32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ creg ].UL[ 0 ] );
ADC32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[ creg ].UL[ 1 ] );
}
else if( g_cpuConstRegs[ creg ].UL[ 0 ] ) {
EEINST_RESETHASLIVE1(_Rd_);
ADD32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ creg ].UL[ 0 ] );
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ] );
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 1 ] );
if( g_cpuConstRegs[ creg ].UL[0] || g_cpuConstRegs[ creg ].UL[1] ) {
ADD32ItoR( EAX, g_cpuConstRegs[ creg ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 1 ] );
if( g_cpuConstRegs[ creg ].UL[0] || g_cpuConstRegs[ creg ].UL[1] ) {
ADD32ItoR( EAX, g_cpuConstRegs[ creg ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
ADC32ItoR( EDX, g_cpuConstRegs[ creg ].UL[ 1 ] );
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
ADC32ItoR( EDX, g_cpuConstRegs[ creg ].UL[ 1 ] );
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -348,39 +330,31 @@ void recDADD_(int info)
}
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
if( _Rs_ != _Rt_ ) PADDQMtoR(mmreg, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
else PSLLQItoR(mmreg, 1); // mult by 2
if( _Rd_ == _Rs_ || _Rd_ == _Rt_ ) {
int vreg = _Rd_ == _Rs_ ? _Rt_ : _Rs_;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 1 ] );
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
if( EEINST_ISLIVE1(_Rd_) )
ADC32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
else
EEINST_RESETHASLIVE1(_Rd_);
}
else {
if( _Rd_ == _Rs_ || _Rd_ == _Rt_ ) {
int vreg = _Rd_ == _Rs_ ? _Rt_ : _Rs_;
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ vreg ].UL[ 1 ] );
ADD32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX);
if( EEINST_ISLIVE1(_Rd_) )
ADC32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX);
else
EEINST_RESETHASLIVE1(_Rd_);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
ADC32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
ADD32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
ADC32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
}
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -510,7 +484,7 @@ void recSUB_constt(int info)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) && (!EEINST_ISLIVE1(_Rd_) || !g_cpuConstRegs[_Rt_].UL[0]) ) {
if(!g_cpuConstRegs[_Rt_].UL[0]) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
@ -596,36 +570,26 @@ void recSUB_(int info)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) && !EEINST_ISLIVE1(_Rd_)) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( !EEINST_ISLIVE1(_Rd_) ) {
if( _Rd_ == _Rs_) {
EEINST_RESETHASLIVE1(_Rd_);
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
SUB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
return;
}
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
EEINST_RESETHASLIVE1(_Rd_);
MOVDMtoMMX(mmreg, (int)&cpuRegs.GPR.r[_Rs_].UL[0] );
PSUBDMtoR(mmreg, (int)&cpuRegs.GPR.r[_Rt_].UL[0] );
if( EEINST_ISLIVE1(_Rd_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
else {
if( !EEINST_ISLIVE1(_Rd_) ) {
if( _Rd_ == _Rs_) {
EEINST_RESETHASLIVE1(_Rd_);
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
SUB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
return;
}
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
}
else {
EEINST_RESETHASLIVE1(_Rd_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
}
EEINST_RESETHASLIVE1(_Rd_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
}
}
}
@ -685,64 +649,57 @@ void recDSUB_consts(int info)
}
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(mmreg, (u32)_eeGetConstReg(_Rs_));
PSUBQMtoR(mmreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[ 0 ]);
if( g_cpuConstRegs[ _Rs_ ].UL[ 0 ] || g_cpuConstRegs[ _Rs_ ].UL[ 1 ] ) {
MOV32ItoR( EAX, g_cpuConstRegs[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32ItoR( EDX, g_cpuConstRegs[ _Rs_ ].UL[ 1 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
SBB32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
}
else {
if( g_cpuConstRegs[ _Rs_ ].UL[ 0 ] || g_cpuConstRegs[ _Rs_ ].UL[ 1 ] ) {
MOV32ItoR( EAX, g_cpuConstRegs[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32ItoR( EDX, g_cpuConstRegs[ _Rs_ ].UL[ 1 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
SBB32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
if( !EEINST_ISLIVE1(_Rd_) )
EEINST_RESETHASLIVE1(_Rd_);
}
else {
if( _Rd_ == _Rt_ ) {
if( _Rd_ == _Rt_ ) {
// negate _Rt_ all in memory
if( EEINST_ISLIVE1(_Rd_) ) {
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
NEG32M((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
ADC32ItoR(EDX, 0);
NEG32R(EDX);
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX);
}
else {
EEINST_RESETHASLIVE1(_Rd_);
NEG32M((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]);
}
return;
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
// take negative of 64bit number
NEG32R(EAX);
if( EEINST_ISLIVE1(_Rd_) ) {
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
NEG32M((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ]);
ADC32ItoR(EDX, 0);
NEG32R(EDX);
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX);
}
else {
EEINST_RESETHASLIVE1(_Rd_);
NEG32M((int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ]);
}
return;
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
// take negative of 64bit number
NEG32R(EAX);
if( EEINST_ISLIVE1(_Rd_) ) {
ADC32ItoR(EDX, 0);
NEG32R(EDX);
}
else {
EEINST_RESETHASLIVE1(_Rd_);
}
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else {
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -762,41 +719,33 @@ void recDSUB_constt(int info)
}
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
if( g_cpuConstRegs[_Rt_].UD[0] ) PSUBQMtoR(mmreg, (u32)_eeGetConstReg(_Rt_));
if( _Rd_ == _Rs_ ) {
if( EEINST_ISLIVE1(_Rd_) && (g_cpuConstRegs[ _Rt_ ].UL[ 0 ] || g_cpuConstRegs[ _Rt_ ].UL[ 1 ]) ) {
SUB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
SBB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[ _Rt_ ].UL[ 1 ] );
}
else if( g_cpuConstRegs[ _Rt_ ].UL[ 0 ] ) {
EEINST_RESETHASLIVE1(_Rd_);
SUB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
}
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
if( _Rd_ == _Rs_ ) {
if( EEINST_ISLIVE1(_Rd_) && (g_cpuConstRegs[ _Rt_ ].UL[ 0 ] || g_cpuConstRegs[ _Rt_ ].UL[ 1 ]) ) {
SUB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
SBB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[1], g_cpuConstRegs[ _Rt_ ].UL[ 1 ] );
}
else if( g_cpuConstRegs[ _Rt_ ].UL[ 0 ] ) {
EEINST_RESETHASLIVE1(_Rd_);
SUB32ItoM( (u32)&cpuRegs.GPR.r[_Rd_].UL[0], g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
}
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( g_cpuConstRegs[ _Rt_ ].UL[ 0 ] || g_cpuConstRegs[ _Rt_ ].UL[ 1 ] ) {
SUB32ItoR( EAX, g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
if( g_cpuConstRegs[ _Rt_ ].UL[ 0 ] || g_cpuConstRegs[ _Rt_ ].UL[ 1 ] ) {
SUB32ItoR( EAX, g_cpuConstRegs[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
SBB32ItoR( EDX, g_cpuConstRegs[ _Rt_ ].UL[ 1 ] );
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
SBB32ItoR( EDX, g_cpuConstRegs[ _Rt_ ].UL[ 1 ] );
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -823,36 +772,29 @@ void recDSUB_(int info)
}
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
int mmreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(mmreg, (int)&cpuRegs.GPR.r[_Rs_].UL[ 0 ]);
PSUBQMtoR(mmreg, (int)&cpuRegs.GPR.r[_Rt_].UL[ 0 ]);
if( _Rd_ == _Rs_ ) {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
SUB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
SBB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
}
else {
if( _Rd_ == _Rs_ ) {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
SUB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
SBB32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
SBB32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
SUB32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rd_) )
SBB32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rd_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -889,45 +831,36 @@ void recAND_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) || (_Rd_ != vreg && _hasFreeMMXreg()) ) {
int rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
if( g_cpuConstRegs[ creg ].UL[0] || g_cpuConstRegs[ creg ].UL[1] ) {
MOVQMtoR(rdreg, (u32)&cpuRegs.GPR.r[vreg].UL[0] );
PANDMtoR(rdreg, (u32)_eeGetConstReg(creg) );
}
else {
if( g_cpuConstRegs[ creg ].UL[0] || g_cpuConstRegs[ creg ].UL[1] ) {
if( _Rd_ == vreg ) {
AND32ItoM((int)&cpuRegs.GPR.r[ vreg ].UL[0], g_cpuConstRegs[creg].UL[0]);
if( EEINST_ISLIVE1(_Rd_) ) {
if( g_cpuConstRegs[creg].UL[1] != 0xffffffff ) AND32ItoM((int)&cpuRegs.GPR.r[ vreg ].UL[1], g_cpuConstRegs[creg].UL[1]);
}
else
EEINST_RESETHASLIVE1(_Rd_);
if( _Rd_ == vreg ) {
AND32ItoM((int)&cpuRegs.GPR.r[ vreg ].UL[0], g_cpuConstRegs[creg].UL[0]);
if( EEINST_ISLIVE1(_Rd_) ) {
if( g_cpuConstRegs[creg].UL[1] != 0xffffffff ) AND32ItoM((int)&cpuRegs.GPR.r[ vreg ].UL[1], g_cpuConstRegs[creg].UL[1]);
}
else {
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ vreg ]);
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ vreg ] + 4 );
AND32ItoR(EAX, g_cpuConstRegs[ creg ].UL[0]);
if( EEINST_ISLIVE1(_Rd_) )
AND32ItoR(ECX, g_cpuConstRegs[ creg ].UL[1]);
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ], EAX);
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ]+4, ECX);
else
EEINST_RESETHASLIVE1(_Rd_);
}
}
else {
MOV32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ], 0);
if( EEINST_ISLIVE1(_Rd_) )
MOV32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ]+4, 0);
else
EEINST_RESETHASLIVE1(_Rd_);
}
else {
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ vreg ]);
if( EEINST_ISLIVE1(_Rd_) )
MOV32MtoR(ECX, (int)&cpuRegs.GPR.r[ vreg ] + 4 );
AND32ItoR(EAX, g_cpuConstRegs[ creg ].UL[0]);
if( EEINST_ISLIVE1(_Rd_) )
AND32ItoR(ECX, g_cpuConstRegs[ creg ].UL[1]);
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ], EAX);
if( EEINST_ISLIVE1(_Rd_) )
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rd_ ]+4, ECX);
else
EEINST_RESETHASLIVE1(_Rd_);
}
}
else {
MOV32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ], 0);
if( EEINST_ISLIVE1(_Rd_) )
MOV32ItoM((int)&cpuRegs.GPR.r[ _Rd_ ]+4, 0);
else
EEINST_RESETHASLIVE1(_Rd_);
}
}
}
@ -954,31 +887,6 @@ void recLogicalOp(int info, int op)
LogicalOpRtoR(EEREC_D, EEREC_T, op);
}
}
else if( (g_pCurInstInfo->regs[_Rs_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
int rsreg, rtreg, rdreg;
_addNeededMMXreg(MMX_GPR+_Rs_);
_addNeededMMXreg(MMX_GPR+_Rt_);
_addNeededMMXreg(MMX_GPR+_Rd_);
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
rsreg = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ);
rtreg = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ);
SetMMXstate();
if( rdreg == rsreg ) {
if( rtreg >= 0 ) LogicalOpRtoR(rdreg, rtreg, op);
else LogicalOpMtoR(rdreg, (int)&cpuRegs.GPR.r[ _Rt_ ], op);
}
else {
if( rdreg != rtreg ) {
if( rtreg >= 0 ) MOVQRtoR(rdreg, rtreg);
else MOVQMtoR(rdreg, (int)&cpuRegs.GPR.r[ _Rt_ ]);
}
if( rsreg >= 0 ) LogicalOpRtoR(rdreg, rsreg, op);
else LogicalOpMtoR(rdreg, (int)&cpuRegs.GPR.r[ _Rs_ ], op);
}
}
else {
if( _Rd_ == _Rs_ || _Rd_ == _Rt_ ) {
int vreg = _Rd_ == _Rs_ ? _Rt_ : _Rs_;
@ -1050,7 +958,7 @@ void recOR_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) || (_Rd_ != vreg && _hasFreeMMXreg()) ) {
if(_Rd_ != vreg && _hasFreeMMXreg()) {
int rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
@ -1128,7 +1036,7 @@ void recXOR_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) || (_Rd_ != vreg && _hasFreeMMXreg()) ) {
if(_Rd_ != vreg && _hasFreeMMXreg()) {
int rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(rdreg, (u32)&cpuRegs.GPR.r[vreg].UL[0] );
@ -1210,7 +1118,7 @@ void recNOR_constv(int info, int creg, int vreg)
}
else {
if( (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) || (_Rd_ != vreg && _hasFreeMMXreg()) ) {
if(_Rd_ != vreg && _hasFreeMMXreg()) {
int rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
int t0reg = _allocMMXreg(-1, MMX_TEMP, 0);

195
pcsx2/x86/ix86-32/iR5900AritImm.cpp
View File

@ -77,55 +77,32 @@ void recADDI_(int info)
return;
}
if ( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && (_Rt_ != _Rs_) ) {
int rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
SetMMXstate();
if ( _Imm_ != 0 ) {
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
PADDDMtoR(rtreg, (uptr)recGetImm64(0, _Imm_));
if ( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(rtreg, _Rt_, 0);
else EEINST_RESETHASLIVE1(_Rt_);
if ( _Rt_ == _Rs_ ) {
if ( EEINST_ISLIVE1(_Rt_) )
{
// must perform the ADD unconditionally, to maintain flags status:
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
_signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
}
else {
// just move and sign extend
if ( !EEINST_HASLIVE1(_Rs_) ) {
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
if ( EEINST_ISLIVE1(_Rt_) ) _signExtendGPRtoMMX(rtreg, _Rt_, 0);
else EEINST_RESETHASLIVE1(_Rt_);
}
else MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
else
{
if( _Imm_ ) ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
EEINST_RESETHASLIVE1(_Rt_);
}
}
else {
if ( _Rt_ == _Rs_ ) {
if ( EEINST_ISLIVE1(_Rt_) )
{
// must perform the ADD unconditionally, to maintain flags status:
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
_signExtendSFtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ]);
}
else
{
if( _Imm_ ) ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
EEINST_RESETHASLIVE1(_Rt_);
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if ( _Imm_ != 0 ) ADD32ItoR( EAX, _Imm_ );
if ( EEINST_ISLIVE1(_Rt_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if ( _Imm_ != 0 ) ADD32ItoR( EAX, _Imm_ );
if ( EEINST_ISLIVE1(_Rt_) ) {
CDQ( );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
else {
EEINST_RESETHASLIVE1(_Rt_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
EEINST_RESETHASLIVE1(_Rt_);
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
}
}
@ -160,42 +137,31 @@ void recDADDI_(int info)
return;
}
if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) ) {
int rtreg;
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
SetMMXstate();
MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
PADDQMtoR(rtreg, (uptr)recGetImm64(-(_Imm_ < 0), _Imm_));
if( _Rt_ == _Rs_ ) {
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
ADC32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
}
else {
if( _Rt_ == _Rs_ ) {
ADD32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _Imm_);
ADC32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], _Imm_<0?0xffffffff:0);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rt_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
if( EEINST_ISLIVE1(_Rt_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
if ( _Imm_ != 0 )
{
ADD32ItoR( EAX, _Imm_ );
if ( _Imm_ != 0 )
{
ADD32ItoR( EAX, _Imm_ );
if( EEINST_ISLIVE1(_Rt_) ) {
ADC32ItoR( EDX, _Imm_ < 0?0xffffffff:0);
}
if( EEINST_ISLIVE1(_Rt_) ) {
ADC32ItoR( EDX, _Imm_ < 0?0xffffffff:0);
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rt_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rt_);
}
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rt_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
else
EEINST_RESETHASLIVE1(_Rt_);
}
}
@ -332,65 +298,46 @@ void recLogicalOpI(int info, int op)
return;
}
if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) && ((_Rt_ != _Rs_) || (_ImmU_==0)) ) {
int rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
SetMMXstate();
if( op == 0 ) {
if ( _ImmU_ != 0 ) {
MOVDMtoMMX(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
PANDMtoR(rtreg, (uptr)recGetImm64(0, _ImmU_));
}
else PXORRtoR(rtreg, rtreg);
if ( _ImmU_ != 0 )
{
if( _Rt_ == _Rs_ ) {
LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
}
else {
MOVQMtoR(rtreg, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ]);
if ( _ImmU_ != 0 ) {
LogicalOpMtoR(rtreg, (uptr)recGetImm64(0, _ImmU_), op);
}
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
LogicalOp32ItoR( EAX, _ImmU_, op);
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
if( op == 0 ) {
if( EEINST_ISLIVE1(_Rt_ ) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
else EEINST_RESETHASLIVE1(_Rt_);
}
}
else {
if ( _ImmU_ != 0 )
{
if( _Rt_ == _Rs_ ) {
LogicalOp32ItoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], _ImmU_, op);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
MOV32MtoR( EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
LogicalOp32ItoR( EAX, _ImmU_, op);
if( op != 0 && EEINST_ISLIVE1(_Rt_) )
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
MOV32RtoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
}
if( op == 0 ) {
if( EEINST_ISLIVE1(_Rt_ ) ) MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
else EEINST_RESETHASLIVE1(_Rt_);
else
{
if( op == 0 ) {
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
}
else {
if( _Rt_ != _Rs_ ) {
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
}
else
{
if( op == 0 ) {
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], 0 );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32ItoM( (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], 0 );
}
else {
if( _Rt_ != _Rs_ ) {
MOV32MtoR(EAX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 0 ] );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32MtoR(EDX, (int)&cpuRegs.GPR.r[ _Rs_ ].UL[ 1 ] );
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ], EAX );
if( EEINST_ISLIVE1(_Rt_ ) )
MOV32RtoM((int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ], EDX );
}
}
if( !EEINST_ISLIVE1(_Rt_) ) EEINST_RESETHASLIVE1(_Rt_);
}
if( !EEINST_ISLIVE1(_Rt_) ) EEINST_RESETHASLIVE1(_Rt_);
}
}

2
pcsx2/x86/ix86-32/iR5900LoadStore.cpp
View File

@ -750,7 +750,7 @@ void recLQ( void )
assert( (g_cpuConstRegs[_Rs_].UL[0]+_Imm_) % 16 == 0 );
if( _Rt_ ) {
if( (g_pCurInstInfo->regs[_Rt_]&EEINST_XMM) || !(g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) ) {
if(g_pCurInstInfo->regs[_Rt_]&EEINST_XMM) {
_deleteMMXreg(MMX_GPR+_Rt_, 2);
_eeOnWriteReg(_Rt_, 0);
mmreg = _allocGPRtoXMMreg(-1, _Rt_, MODE_WRITE);

9
pcsx2/x86/ix86-32/iR5900MultDiv.cpp
View File

@ -86,14 +86,7 @@ void recWritebackHILO(int info, int writed, int upper)
_eeOnWriteReg(_Rd_, 1);
regd = -1;
if( g_pCurInstInfo->regs[_Rd_] & EEINST_MMX ) {
if( savedlo ) {
regd = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
MOVQMtoR(regd, loaddr);
}
}
else if( g_pCurInstInfo->regs[_Rd_] & EEINST_XMM ) {
if( g_pCurInstInfo->regs[_Rd_] & EEINST_XMM ) {
if( savedlo ) {
regd = _checkXMMreg(XMMTYPE_GPRREG, _Rd_, MODE_WRITE|MODE_READ);
if( regd >= 0 ) {

41
pcsx2/x86/ix86-32/iR5900Shift.cpp
View File

@ -68,12 +68,6 @@ void recSLLs_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( g_pCurInstInfo->regs[_Rd_]&EEINST_MMX ) {
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 )
@ -142,12 +136,6 @@ void recSRLs_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 ) SHR32ItoR( EAX, sa);
@ -216,12 +204,6 @@ void recSRAs_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
MOVDMtoMMX(rtreg, (u32)&cpuRegs.GPR.r[_Rt_].UL[0]);
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 ) SAR32ItoR( EAX, sa);
@ -422,13 +404,6 @@ void recDSLL32s_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
_addNeededMMXreg(MMX_GPR+_Rt_);
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 0 ] );
if ( sa != 0 )
@ -466,13 +441,6 @@ void recDSRL32s_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
_addNeededMMXreg(MMX_GPR+_Rt_);
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
if ( sa != 0 ) SHR32ItoR( EAX, sa );
@ -509,13 +477,6 @@ void recDSRA32s_(int info, int sa)
rtreg = EEREC_T;
rdreg = EEREC_D;
}
else if( (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
_addNeededMMXreg(MMX_GPR+_Rt_);
_addNeededMMXreg(MMX_GPR+_Rd_);
rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
rdreg = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
SetMMXstate();
}
else {
MOV32MtoR( EAX, (int)&cpuRegs.GPR.r[ _Rt_ ].UL[ 1 ] );
CDQ( );
@ -612,7 +573,7 @@ int recSetShiftV(int info, int* rsreg, int* rtreg, int* rdreg, int* rstemp, int
mmxregs[EEREC_S].inuse = 0;
}
}
else if( forcemmx || (g_pCurInstInfo->regs[_Rt_]&EEINST_MMX) || (g_pCurInstInfo->regs[_Rd_]&EEINST_MMX) ) {
else if( forcemmx ) {
_addNeededMMXreg(MMX_GPR+_Rt_);
_addNeededMMXreg(MMX_GPR+_Rd_);
*rtreg = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);

206
pcsx2/x86/ix86-32/iR5900Templates.cpp
View File

@ -107,136 +107,6 @@ void eeRecompileCode0(R5900FNPTR constcode, R5900FNPTR_INFO constscode, R5900FNP
moded = MODE_WRITE|((xmminfo&XMMINFO_READD)?MODE_READ:0);
// test if should write mmx
if( g_pCurInstInfo->info & EEINST_MMX ) {
if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) _addNeededMMXreg(MMX_GPR+MMX_LO);
if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) _addNeededMMXreg(MMX_GPR+MMX_HI);
_addNeededMMXreg(MMX_GPR+_Rs_);
_addNeededMMXreg(MMX_GPR+_Rt_);
if( GPR_IS_CONST1(_Rs_) || GPR_IS_CONST1(_Rt_) ) {
int creg = GPR_IS_CONST1(_Rs_) ? _Rs_ : _Rt_;
int vreg = creg == _Rs_ ? _Rt_ : _Rs_;
// if(g_pCurInstInfo->regs[vreg]&EEINST_MMX) {
// mmreg1 = _allocMMXreg(-1, MMX_GPR+vreg, MODE_READ);
// _addNeededMMXreg(MMX_GPR+vreg);
// }
mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, vreg, MODE_READ);
if( mmreg1 >= 0 ) {
int info = PROCESS_EE_MMX;
if( GPR_IS_CONST1(_Rs_) ) info |= PROCESS_EE_SETMODET(mmreg1);
else info |= PROCESS_EE_SETMODES(mmreg1);
if( xmminfo & XMMINFO_WRITED ) {
_addNeededMMXreg(MMX_GPR+_Rd_);
mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded);
if( !(xmminfo&XMMINFO_READD) && mmreg3 < 0 && ((g_pCurInstInfo->regs[vreg] & EEINST_LASTUSE) || !EEINST_ISLIVE64(vreg)) ) {
if( EEINST_ISLIVE64(vreg) ) {
_freeMMXreg(mmreg1);
if( GPR_IS_CONST1(_Rs_) ) info &= ~PROCESS_EE_MODEWRITET;
else info &= ~PROCESS_EE_MODEWRITES;
}
_deleteGPRtoXMMreg(_Rd_, 2);
mmxregs[mmreg1].inuse = 1;
mmxregs[mmreg1].reg = _Rd_;
mmxregs[mmreg1].mode = moded;
mmreg3 = mmreg1;
}
else if( mmreg3 < 0 ) mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded);
info |= PROCESS_EE_SET_D(mmreg3);
}
if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) {
mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1);
if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp);
}
if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) {
mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1);
if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp);
}
SetMMXstate();
if( creg == _Rs_ ) constscode(info|PROCESS_EE_SET_T(mmreg1));
else consttcode(info|PROCESS_EE_SET_S(mmreg1));
_clearNeededMMXregs();
if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_);
return;
}
}
else {
// no const regs
mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ);
mmreg2 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ);
if( mmreg1 >= 0 || mmreg2 >= 0 ) {
int info = PROCESS_EE_MMX;
// do it all in mmx
if( mmreg1 < 0 ) mmreg1 = _allocMMXreg(-1, MMX_GPR+_Rs_, MODE_READ);
if( mmreg2 < 0 ) mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_READ);
info |= PROCESS_EE_SETMODES(mmreg1)|PROCESS_EE_SETMODET(mmreg2);
// check for last used, if so don't alloc a new MMX reg
if( xmminfo & XMMINFO_WRITED ) {
_addNeededMMXreg(MMX_GPR+_Rd_);
mmreg3 = _checkMMXreg(MMX_GPR+_Rd_, moded);
if( mmreg3 < 0 ) {
if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_)) ) {
if( EEINST_ISLIVE64(_Rt_) ) {
_freeMMXreg(mmreg2);
info &= ~PROCESS_EE_MODEWRITET;
}
_deleteGPRtoXMMreg(_Rd_, 2);
mmxregs[mmreg2].inuse = 1;
mmxregs[mmreg2].reg = _Rd_;
mmxregs[mmreg2].mode = moded;
mmreg3 = mmreg2;
}
else if( !(xmminfo&XMMINFO_READD) && ((g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_)) ) {
if( EEINST_ISLIVE64(_Rs_) ) {
_freeMMXreg(mmreg1);
info &= ~PROCESS_EE_MODEWRITES;
}
_deleteGPRtoXMMreg(_Rd_, 2);
mmxregs[mmreg1].inuse = 1;
mmxregs[mmreg1].reg = _Rd_;
mmxregs[mmreg1].mode = moded;
mmreg3 = mmreg1;
}
else mmreg3 = _allocMMXreg(-1, MMX_GPR+_Rd_, moded);
}
info |= PROCESS_EE_SET_D(mmreg3);
}
if( xmminfo & (XMMINFO_READLO|XMMINFO_WRITELO) ) {
mmtemp = eeProcessHILO(MMX_LO, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1);
if( mmtemp >= 0 ) info |= PROCESS_EE_SET_LO(mmtemp);
}
if( xmminfo & (XMMINFO_READHI|XMMINFO_WRITEHI) ) {
mmtemp = eeProcessHILO(MMX_HI, ((xmminfo&XMMINFO_READLO)?MODE_READ:0)|((xmminfo&XMMINFO_WRITELO)?MODE_WRITE:0), 1);
if( mmtemp >= 0 ) info |= PROCESS_EE_SET_HI(mmtemp);
}
SetMMXstate();
noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2));
_clearNeededMMXregs();
if( xmminfo & XMMINFO_WRITED ) GPR_DEL_CONST(_Rd_);
return;
}
}
_clearNeededMMXregs();
}
// test if should write xmm, mirror to mmx code
if( g_pCurInstInfo->info & EEINST_XMM ) {
@ -413,44 +283,6 @@ void eeRecompileCode1(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode)
return;
}
// test if should write mmx
if( g_pCurInstInfo->info & EEINST_MMX ) {
// no const regs
mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rs_, MODE_READ);
if( mmreg1 >= 0 ) {
int info = PROCESS_EE_MMX|PROCESS_EE_SETMODES(mmreg1);
// check for last used, if so don't alloc a new MMX reg
_addNeededMMXreg(MMX_GPR+_Rt_);
mmreg2 = _checkMMXreg(MMX_GPR+_Rt_, MODE_WRITE);
if( mmreg2 < 0 ) {
if( (g_pCurInstInfo->regs[_Rs_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rs_) ) {
if( EEINST_ISLIVE64(_Rs_) ) {
_freeMMXreg(mmreg1);
info &= ~PROCESS_EE_MODEWRITES;
}
_deleteGPRtoXMMreg(_Rt_, 2);
mmxregs[mmreg1].inuse = 1;
mmxregs[mmreg1].reg = _Rt_;
mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ;
mmreg2 = mmreg1;
}
else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rt_, MODE_WRITE);
}
SetMMXstate();
noconstcode(info|PROCESS_EE_SET_S(mmreg1)|PROCESS_EE_SET_T(mmreg2));
_clearNeededMMXregs();
GPR_DEL_CONST(_Rt_);
return;
}
_clearNeededMMXregs();
}
// test if should write xmm, mirror to mmx code
if( g_pCurInstInfo->info & EEINST_XMM ) {
@ -513,44 +345,6 @@ void eeRecompileCode2(R5900FNPTR constcode, R5900FNPTR_INFO noconstcode)
return;
}
// test if should write mmx
if( g_pCurInstInfo->info & EEINST_MMX ) {
// no const regs
mmreg1 = _allocCheckGPRtoMMX(g_pCurInstInfo, _Rt_, MODE_READ);
if( mmreg1 >= 0 ) {
int info = PROCESS_EE_MMX|PROCESS_EE_SETMODET(mmreg1);
// check for last used, if so don't alloc a new MMX reg
_addNeededMMXreg(MMX_GPR+_Rd_);
mmreg2 = _checkMMXreg(MMX_GPR+_Rd_, MODE_WRITE);
if( mmreg2 < 0 ) {
if( (g_pCurInstInfo->regs[_Rt_] & EEINST_LASTUSE) || !EEINST_ISLIVE64(_Rt_) ) {
if( EEINST_ISLIVE64(_Rt_) ) {
_freeMMXreg(mmreg1);
info &= ~PROCESS_EE_MODEWRITET;
}
_deleteGPRtoXMMreg(_Rd_, 2);
mmxregs[mmreg1].inuse = 1;
mmxregs[mmreg1].reg = _Rd_;
mmxregs[mmreg1].mode = MODE_WRITE|MODE_READ;
mmreg2 = mmreg1;
}
else mmreg2 = _allocMMXreg(-1, MMX_GPR+_Rd_, MODE_WRITE);
}
SetMMXstate();
noconstcode(info|PROCESS_EE_SET_T(mmreg1)|PROCESS_EE_SET_D(mmreg2));
_clearNeededMMXregs();
GPR_DEL_CONST(_Rd_);
return;
}
_clearNeededMMXregs();
}
// test if should write xmm, mirror to mmx code
if( g_pCurInstInfo->info & EEINST_XMM ) {