mirror of https://github.com/PCSX2/pcsx2.git
microVU: moved stuff around, and implemented some other stuff... also added the file microVU_Analyze.inl to project.
git-svn-id: http://pcsx2.googlecode.com/svn/trunk@831 96395faa-99c1-11dd-bbfe-3dabce05a288
This commit is contained in:
cottonvibes
parent
df95ec6b87
commit
3e3ffef417
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@ -2502,6 +2502,10 @@
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RelativePath="..\..\x86\microVU_Alloc.inl"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_Analyze.inl"
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>
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</File>
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<File
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RelativePath="..\..\x86\microVU_Compile.inl"
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>
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@ -24,6 +24,7 @@
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#include "GS.h"
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#include "ix86/ix86.h"
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#include "microVU_Alloc.h"
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#include "microVU_Misc.h"
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struct microBlock {
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microRegInfo pState; // Detailed State of Pipeline
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@ -155,7 +156,9 @@ microVUt(void) mVUreset();
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microVUt(void) mVUclose();
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#endif
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#include "microVU_Misc.h"
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// Include all the *.inl files (Needed because C++ sucks with templates and *.cpp files)
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#include "microVU_Misc.inl"
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#include "microVU_Analyze.inl"
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#include "microVU_Alloc.inl"
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#include "microVU_Tables.inl"
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#include "microVU_Compile.inl"
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@ -30,20 +30,26 @@ union regInfo {
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struct microRegInfo {
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regInfo VF[32];
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regInfo Acc;
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u8 VI[32];
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u8 i;
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u8 q;
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u8 p;
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u8 r;
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};
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struct microTempRegInfo {
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regInfo VF[2]; // Holds cycle info for Fd, VF[0] = Upper Instruction, VF[1] = Lower Instruction
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u8 VFreg[2]; // Index of the VF reg
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u8 VI; // Holds cycle info for Id
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u8 VIreg; // Index of the VI reg
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};
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template<u32 pSize>
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struct microAllocInfo {
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microRegInfo regs;
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u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR)
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u32 curPC; // Current PC
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u32 cycles; // Cycles for current block
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microRegInfo regs; // Pipeline info
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microTempRegInfo regsTemp; // Temp Pipeline info (used so that new pipeline info isn't conflicting between upper and lower instructions in the same cycle)
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u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR)
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u32 curPC; // Current PC
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u32 cycles; // Cycles for current block
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u32 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes)
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u32 info[pSize];// bit 00 = Lower Instruction is NOP
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// bit 01
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// bit 02
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@ -19,96 +19,6 @@
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#pragma once
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#ifdef PCSX2_MICROVU
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//------------------------------------------------------------------
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// Micro VU - recPass 0 Functions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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#define aReg(x) mVUallocInfo.regs.VF[x]
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#define aMax(x, y) ((x > y) ? x : y)
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#define analyzeReg1(reg) { \
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if (reg) { \
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if (_X) { mVal = aMax(mVal, aReg(reg).x); } \
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if (_Y) { mVal = aMax(mVal, aReg(reg).y); } \
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if (_Z) { mVal = aMax(mVal, aReg(reg).z); } \
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if (_W) { mVal = aMax(mVal, aReg(reg).w); } \
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} \
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}
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#define analyzeReg2(reg) { \
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if (reg) { \
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if (_X) { aReg(reg).x = 4; } \
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if (_Y) { aReg(reg).y = 4; } \
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if (_Z) { aReg(reg).z = 4; } \
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if (_W) { aReg(reg).w = 4; } \
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} \
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}
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microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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int mVal = 0;
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg1(Ft);
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incCycles(mVal);
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analyzeReg2(Fd);
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}
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//------------------------------------------------------------------
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// FMAC2 - ABS/FTOI/ITOF Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
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microVU* mVU = mVUx;
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int mVal = 0;
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analyzeReg1(Fs);
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incCycles(mVal);
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analyzeReg2(Ft);
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}
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//------------------------------------------------------------------
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// FMAC3 - BC(xyzw) FMAC Opcodes
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//------------------------------------------------------------------
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#define analyzeReg3(reg) { \
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if (reg) { \
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if (_bc_x) { mVal = aMax(mVal, aReg(reg).x); } \
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else if (_bc_y) { mVal = aMax(mVal, aReg(reg).y); } \
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else if (_bc_z) { mVal = aMax(mVal, aReg(reg).z); } \
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else { mVal = aMax(mVal, aReg(reg).w); } \
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} \
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}
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microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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int mVal = 0;
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg3(Ft);
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incCycles(mVal);
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analyzeReg2(Fd);
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}
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//------------------------------------------------------------------
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// FMAC4 - Clip FMAC Opcode
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//------------------------------------------------------------------
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#define analyzeReg4(reg) { \
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if (reg) { mVal = aMax(mVal, aReg(reg).w); } \
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}
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microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
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microVU* mVU = mVUx;
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int mVal = 0;
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analyzeReg1(Fs);
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analyzeReg4(Ft);
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incCycles(mVal);
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}
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//------------------------------------------------------------------
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// Micro VU - recPass 1 Functions
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//------------------------------------------------------------------
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@ -855,4 +765,5 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) {
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if (!_reg_ && (_fxf_ < 3)) { XOR32RtoR(GPRreg, GPRreg); } \
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else { MOV32MtoR(GPRreg, (uptr)&mVU->regs->VF[_reg_].UL[0]); } \
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}
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#endif //PCSX2_MICROVU
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@ -0,0 +1,126 @@
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/* Pcsx2 - Pc Ps2 Emulator
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* Copyright (C) 2009 Pcsx2-Playground Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#pragma once
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#ifdef PCSX2_MICROVU
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//------------------------------------------------------------------
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// Micro VU - recPass 0 Functions
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// FMAC1 - Normal FMAC Opcodes
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//------------------------------------------------------------------
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#define aReg(x) mVUallocInfo.regs.VF[x]
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#define bReg(x) mVUallocInfo.regsTemp.VFreg[0] = x; mVUallocInfo.regsTemp.VF[0]
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#define aMax(x, y) ((x > y) ? x : y)
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#define analyzeReg1(reg) { \
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if (reg) { \
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if (_X) { mVUstall = aMax(mVUstall, aReg(reg).x); } \
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if (_Y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \
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if (_Z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \
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if (_W) { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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} \
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}
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#define analyzeReg2(reg) { \
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if (reg) { \
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if (_X) { bReg(reg).x = 4; } \
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if (_Y) { bReg(reg).y = 4; } \
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if (_Z) { bReg(reg).z = 4; } \
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if (_W) { bReg(reg).w = 4; } \
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} \
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}
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microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg1(Ft);
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analyzeReg2(Fd);
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}
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//------------------------------------------------------------------
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// FMAC2 - ABS/FTOI/ITOF Opcodes
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//------------------------------------------------------------------
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microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) {
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microVU* mVU = mVUx;
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analyzeReg1(Fs);
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analyzeReg2(Ft);
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}
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//------------------------------------------------------------------
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// FMAC3 - BC(xyzw) FMAC Opcodes
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//------------------------------------------------------------------
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#define analyzeReg3(reg) { \
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if (reg) { \
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if (_bc_x) { mVUstall = aMax(mVUstall, aReg(reg).x); } \
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else if (_bc_y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \
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else if (_bc_z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \
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else { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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} \
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}
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microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) {
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microVU* mVU = mVUx;
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mVUinfo |= _doStatus;
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analyzeReg1(Fs);
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analyzeReg3(Ft);
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analyzeReg2(Fd);
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}
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//------------------------------------------------------------------
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// FMAC4 - Clip FMAC Opcode
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//------------------------------------------------------------------
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#define analyzeReg4(reg) { \
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if (reg) { mVUstall = aMax(mVUstall, aReg(reg).w); } \
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}
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microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) {
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microVU* mVU = mVUx;
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analyzeReg1(Fs);
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analyzeReg4(Ft);
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}
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//------------------------------------------------------------------
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// FDIV - DIV/SQRT/RSQRT Opcodes
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//------------------------------------------------------------------
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#define analyzeReg5(reg, fxf) { \
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if (reg) { \
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switch (fxf) { \
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case 0: mVUstall = aMax(mVUstall, aReg(reg).x); break; \
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case 1: mVUstall = aMax(mVUstall, aReg(reg).y); break; \
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case 2: mVUstall = aMax(mVUstall, aReg(reg).z); break; \
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case 3: mVUstall = aMax(mVUstall, aReg(reg).w); break; \
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} \
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} \
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}
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microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf) {
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microVU* mVU = mVUx;
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analyzeReg5(Fs, Fsf);
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analyzeReg5(Ft, Ftf);
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}
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#endif //PCSX2_MICROVU
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@ -31,10 +31,6 @@
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#define mVUdebugStuff1() {}
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#endif
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#define curI mVUcurProg.data[iPC]
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#define setCode() { mVU->code = curI; }
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#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); }
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#define createBlock(blockEndPtr) { \
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block.pipelineState = pipelineState; \
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block.x86ptrStart = x86ptrStart; \
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@ -45,6 +41,19 @@
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} \
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}
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#define curI mVUcurProg.data[iPC]
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#define setCode() { mVU->code = curI; }
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#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); }
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#define startLoop() { mVUdebugStuff1(); mVUstall = 0; memset(&mVUregsTemp, 0, sizeof(mVUregsTemp)); }
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microVUt(void) mVUsetCycles() {
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microVU* mVU = mVUx;
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incCycles(mVUstall);
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mVUregs.VF[mVUregsTemp.VFreg[0]].reg = mVUregsTemp.VF[0].reg;
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mVUregs.VF[mVUregsTemp.VFreg[1]].reg = mVUregsTemp.VF[1].reg;
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mVUregs.VI[mVUregsTemp.VIreg] = mVUregsTemp.VI;
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}
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microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState, u8* x86ptrStart) {
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microVU* mVU = mVUx;
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microBlock block;
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@ -57,12 +66,13 @@ microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState,
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// First Pass
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setCode();
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for (;;) {
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mVUdebugStuff1();
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startLoop();
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mVUopU<vuIndex, 0>();
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if (curI & _Ebit_) { mVUbranch = 5; }
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if (curI & _MDTbit_) { mVUbranch = 4; }
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if (curI & _Ibit_) { incPC(1); mVUinfo |= _isNOP; }
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else { incPC(1); mVUopL<vuIndex, 0>(); }
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mVUsetCycles<vuIndex>();
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if (mVUbranch == 4) { mVUbranch = 0; mVUinfo |= _isEOB; break; }
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else if (mVUbranch == 5) { mVUbranch = 4; }
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else if (mVUbranch) { mVUbranch = 4; mVUinfo |= _isBranch; }
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@ -25,7 +25,7 @@
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microVUf(void) mVU_DIV() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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//u8 *pjmp;, *pjmp1;
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u32 *ajmp32, *bjmp32;
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@ -72,7 +72,7 @@ microVUf(void) mVU_DIV() {
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}
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microVUf(void) mVU_SQRT() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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//u8* pjmp;
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getReg5(xmmFt, _Ft_, _Ftf_);
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@ -94,7 +94,7 @@ microVUf(void) mVU_SQRT() {
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}
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microVUf(void) mVU_RSQRT() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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u8 *ajmp8, *bjmp8;
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@ -162,7 +162,7 @@ microVUt(void) mVU_EATAN_() {
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}
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microVUf(void) mVU_EATAN() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -177,7 +177,7 @@ microVUf(void) mVU_EATAN() {
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}
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microVUf(void) mVU_EATANxy() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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getReg6(xmmFt, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x01);
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@ -193,7 +193,7 @@ microVUf(void) mVU_EATANxy() {
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}
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microVUf(void) mVU_EATANxz() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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getReg6(xmmFt, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x02);
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@ -215,7 +215,7 @@ microVUf(void) mVU_EATANxz() {
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}
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microVUf(void) mVU_EEXP() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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getReg5(xmmFs, _Fs_, _Fsf_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -261,7 +261,7 @@ microVUt(void) mVU_sumXYZ() {
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}
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microVUf(void) mVU_ELENG() {
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microVU* mVU = mVUx;
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if (recPass == 0) {}
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if (!recPass) {}
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else {
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getReg6(xmmFs, _Fs_);
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SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
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@ -272,7 +272,7 @@ microVUf(void) mVU_ELENG() {
|
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}
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microVUf(void) mVU_ERCPR() {
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microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -285,7 +285,7 @@ microVUf(void) mVU_ERCPR() {
|
|||
}
|
||||
microVUf(void) mVU_ERLENG() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -299,7 +299,7 @@ microVUf(void) mVU_ERLENG() {
|
|||
}
|
||||
microVUf(void) mVU_ERSADD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -313,7 +313,7 @@ microVUf(void) mVU_ERSADD() {
|
|||
}
|
||||
microVUf(void) mVU_ERSQRT() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -326,7 +326,7 @@ microVUf(void) mVU_ERSQRT() {
|
|||
}
|
||||
microVUf(void) mVU_ESADD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -342,7 +342,7 @@ microVUf(void) mVU_ESADD() {
|
|||
}
|
||||
microVUf(void) mVU_ESIN() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -367,7 +367,7 @@ microVUf(void) mVU_ESIN() {
|
|||
}
|
||||
microVUf(void) mVU_ESQRT() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg5(xmmFs, _Fs_, _Fsf_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -377,7 +377,7 @@ microVUf(void) mVU_ESQRT() {
|
|||
}
|
||||
microVUf(void) mVU_ESUM() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
getReg6(xmmFs, _Fs_);
|
||||
SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance
|
||||
|
|
@ -392,7 +392,7 @@ microVUf(void) mVU_ESUM() {
|
|||
|
||||
microVUf(void) mVU_FCAND() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
|
||||
AND32ItoR(gprT1, _Imm24_);
|
||||
|
|
@ -403,7 +403,7 @@ microVUf(void) mVU_FCAND() {
|
|||
}
|
||||
microVUf(void) mVU_FCEQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
|
||||
XOR32ItoR(gprT1, _Imm24_);
|
||||
|
|
@ -414,7 +414,7 @@ microVUf(void) mVU_FCEQ() {
|
|||
}
|
||||
microVUf(void) mVU_FCGET() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
|
||||
AND32ItoR(gprT1, 0xfff);
|
||||
|
|
@ -423,7 +423,7 @@ microVUf(void) mVU_FCGET() {
|
|||
}
|
||||
microVUf(void) mVU_FCOR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocCFLAGa<vuIndex>(gprT1, fvcInstance);
|
||||
OR32ItoR(gprT1, _Imm24_);
|
||||
|
|
@ -434,7 +434,7 @@ microVUf(void) mVU_FCOR() {
|
|||
}
|
||||
microVUf(void) mVU_FCSET() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
MOV32ItoR(gprT1, _Imm24_);
|
||||
mVUallocCFLAGb<vuIndex>(gprT1, fcInstance);
|
||||
|
|
@ -443,7 +443,7 @@ microVUf(void) mVU_FCSET() {
|
|||
|
||||
microVUf(void) mVU_FMAND() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
|
||||
mVUallocVIa<vuIndex>(gprT2, _Fs_);
|
||||
|
|
@ -453,7 +453,7 @@ microVUf(void) mVU_FMAND() {
|
|||
}
|
||||
microVUf(void) mVU_FMEQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
|
||||
mVUallocVIa<vuIndex>(gprT2, _Fs_);
|
||||
|
|
@ -465,7 +465,7 @@ microVUf(void) mVU_FMEQ() {
|
|||
}
|
||||
microVUf(void) mVU_FMOR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocMFLAGa<vuIndex>(gprT1, fvmInstance);
|
||||
mVUallocVIa<vuIndex>(gprT2, _Fs_);
|
||||
|
|
@ -476,7 +476,7 @@ microVUf(void) mVU_FMOR() {
|
|||
|
||||
microVUf(void) mVU_FSAND() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
|
||||
AND16ItoR(gprT1, _Imm12_);
|
||||
|
|
@ -485,7 +485,7 @@ microVUf(void) mVU_FSAND() {
|
|||
}
|
||||
microVUf(void) mVU_FSEQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
|
||||
XOR16ItoR(gprT1, _Imm12_);
|
||||
|
|
@ -496,7 +496,7 @@ microVUf(void) mVU_FSEQ() {
|
|||
}
|
||||
microVUf(void) mVU_FSOR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocSFLAGa<vuIndex>(gprT1, fvsInstance);
|
||||
OR16ItoR(gprT1, _Imm12_);
|
||||
|
|
@ -505,7 +505,7 @@ microVUf(void) mVU_FSOR() {
|
|||
}
|
||||
microVUf(void) mVU_FSSET() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
int flagReg;
|
||||
getFlagReg(flagReg, fsInstance);
|
||||
|
|
@ -515,7 +515,7 @@ microVUf(void) mVU_FSSET() {
|
|||
|
||||
microVUf(void) mVU_IADD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
if (_Ft_ != _Fs_) {
|
||||
|
|
@ -528,7 +528,7 @@ microVUf(void) mVU_IADD() {
|
|||
}
|
||||
microVUf(void) mVU_IADDI() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
ADD16ItoR(gprT1, _Imm5_);
|
||||
|
|
@ -537,7 +537,7 @@ microVUf(void) mVU_IADDI() {
|
|||
}
|
||||
microVUf(void) mVU_IADDIU() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
ADD16ItoR(gprT1, _Imm12_);
|
||||
|
|
@ -546,7 +546,7 @@ microVUf(void) mVU_IADDIU() {
|
|||
}
|
||||
microVUf(void) mVU_IAND() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
if (_Ft_ != _Fs_) {
|
||||
|
|
@ -558,7 +558,7 @@ microVUf(void) mVU_IAND() {
|
|||
}
|
||||
microVUf(void) mVU_IOR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
if (_Ft_ != _Fs_) {
|
||||
|
|
@ -570,7 +570,7 @@ microVUf(void) mVU_IOR() {
|
|||
}
|
||||
microVUf(void) mVU_ISUB() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (_Ft_ != _Fs_) {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
|
|
@ -586,7 +586,7 @@ microVUf(void) mVU_ISUB() {
|
|||
}
|
||||
microVUf(void) mVU_ISUBIU() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
SUB16ItoR(gprT1, _Imm12_);
|
||||
|
|
@ -596,7 +596,7 @@ microVUf(void) mVU_ISUBIU() {
|
|||
|
||||
microVUf(void) mVU_MOVE() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ }
|
||||
else {
|
||||
mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W);
|
||||
mVUsaveReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
|
||||
|
|
@ -604,7 +604,7 @@ microVUf(void) mVU_MOVE() {
|
|||
}
|
||||
microVUf(void) mVU_MFIR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Fs_);
|
||||
MOVSX32R16toR(gprT1, gprT1);
|
||||
|
|
@ -615,7 +615,7 @@ microVUf(void) mVU_MFIR() {
|
|||
}
|
||||
microVUf(void) mVU_MFP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
getPreg(xmmFt);
|
||||
mVUsaveReg<vuIndex>(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W);
|
||||
|
|
@ -623,7 +623,7 @@ microVUf(void) mVU_MFP() {
|
|||
}
|
||||
microVUf(void) mVU_MTIR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
|
|
@ -631,7 +631,7 @@ microVUf(void) mVU_MTIR() {
|
|||
}
|
||||
microVUf(void) mVU_MR32() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
mVUloadReg<vuIndex>(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15);
|
||||
if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); }
|
||||
|
|
@ -641,7 +641,7 @@ microVUf(void) mVU_MR32() {
|
|||
|
||||
microVUf(void) mVU_ILW() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
if (!_Fs_) {
|
||||
MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS );
|
||||
|
|
@ -659,7 +659,7 @@ microVUf(void) mVU_ILW() {
|
|||
}
|
||||
microVUf(void) mVU_ILWR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
if (!_Fs_) {
|
||||
MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + offsetSS );
|
||||
|
|
@ -676,7 +676,7 @@ microVUf(void) mVU_ILWR() {
|
|||
}
|
||||
microVUf(void) mVU_ISW() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Fs_) {
|
||||
int imm = getVUmem(_Imm11_);
|
||||
|
|
@ -700,7 +700,7 @@ microVUf(void) mVU_ISW() {
|
|||
}
|
||||
microVUf(void) mVU_ISWR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Fs_) {
|
||||
mVUallocVIa<vuIndex>(gprT1, _Ft_);
|
||||
|
|
@ -723,7 +723,7 @@ microVUf(void) mVU_ISWR() {
|
|||
|
||||
microVUf(void) mVU_LQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*If (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*If (!_Ft_) nop();*/ }
|
||||
else {
|
||||
if (!_Fs_) {
|
||||
mVUloadReg<vuIndex>(xmmFt, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W);
|
||||
|
|
@ -740,7 +740,7 @@ microVUf(void) mVU_LQ() {
|
|||
}
|
||||
microVUf(void) mVU_LQD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Fs_ && _Ft_) {
|
||||
mVUloadReg<vuIndex>(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W);
|
||||
|
|
@ -760,7 +760,7 @@ microVUf(void) mVU_LQD() {
|
|||
}
|
||||
microVUf(void) mVU_LQI() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Fs_ && _Ft_) {
|
||||
mVUloadReg<vuIndex>(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W);
|
||||
|
|
@ -781,7 +781,7 @@ microVUf(void) mVU_LQI() {
|
|||
}
|
||||
microVUf(void) mVU_SQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Ft_) {
|
||||
getReg7(xmmFs, _Fs_);
|
||||
|
|
@ -798,7 +798,7 @@ microVUf(void) mVU_SQ() {
|
|||
}
|
||||
microVUf(void) mVU_SQD() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Ft_) {
|
||||
getReg7(xmmFs, _Fs_);
|
||||
|
|
@ -816,7 +816,7 @@ microVUf(void) mVU_SQD() {
|
|||
}
|
||||
microVUf(void) mVU_SQI() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (!_Ft_) {
|
||||
getReg7(xmmFs, _Fs_);
|
||||
|
|
@ -836,7 +836,7 @@ microVUf(void) mVU_SQI() {
|
|||
|
||||
microVUf(void) mVU_RINIT() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (_Fs_ || (_Fsf_ == 3)) {
|
||||
getReg8(gprR, _Fs_, _Fsf_);
|
||||
|
|
@ -857,12 +857,12 @@ microVUt(void) mVU_RGET_() {
|
|||
}
|
||||
microVUf(void) mVU_RGET() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*if (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*if (!_Ft_) nop();*/ }
|
||||
else { mVU_RGET_<vuIndex>(); }
|
||||
}
|
||||
microVUf(void) mVU_RNEXT() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) { /*if (!_Ft_) nop();*/ }
|
||||
if (!recPass) { /*if (!_Ft_) nop();*/ }
|
||||
else {
|
||||
// algorithm from www.project-fao.org
|
||||
MOV32RtoR(gprT1, gprR);
|
||||
|
|
@ -883,7 +883,7 @@ microVUf(void) mVU_RNEXT() {
|
|||
}
|
||||
microVUf(void) mVU_RXOR() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
if (_Fs_ || (_Fsf_ == 3)) {
|
||||
getReg8(gprT1, _Fs_, _Fsf_);
|
||||
|
|
@ -895,18 +895,18 @@ microVUf(void) mVU_RXOR() {
|
|||
|
||||
microVUf(void) mVU_WAITP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {}
|
||||
}
|
||||
microVUf(void) mVU_WAITQ() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {}
|
||||
}
|
||||
|
||||
microVUf(void) mVU_XTOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->top);
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
|
|
@ -914,7 +914,7 @@ microVUf(void) mVU_XTOP() {
|
|||
}
|
||||
microVUf(void) mVU_XITOP() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->itop );
|
||||
mVUallocVIb<vuIndex>(gprT1, _Ft_);
|
||||
|
|
@ -934,7 +934,7 @@ void __fastcall mVU_XGKICK1(u32 addr) { mVU_XGKICK_<1>(addr); }
|
|||
|
||||
microVUf(void) mVU_XGKICK() {
|
||||
microVU* mVU = mVUx;
|
||||
if (recPass == 0) {}
|
||||
if (!recPass) {}
|
||||
else {
|
||||
mVUallocVIa<vuIndex>(gprT2, _Fs_); // gprT2 = ECX for __fastcall
|
||||
if (!vuIndex) CALLFunc((uptr)mVU_XGKICK0);
|
||||
|
|
|
|||
|
|
@ -143,6 +143,9 @@ declareAllVariables
|
|||
#define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo
|
||||
#define mVUbranch mVUallocInfo.branch
|
||||
#define mVUcycles mVUallocInfo.cycles
|
||||
#define mVUstall mVUallocInfo.maxStall
|
||||
#define mVUregs mVUallocInfo.regs
|
||||
#define mVUregsTemp mVUallocInfo.regsTemp
|
||||
#define mVUinfo mVUallocInfo.info[mVUallocInfo.curPC / 2]
|
||||
#define iPC mVUallocInfo.curPC
|
||||
#define xPC ((iPC / 2) * 8)
|
||||
|
|
@ -195,4 +198,3 @@ declareAllVariables
|
|||
#define isMMX(_VIreg_) (_VIreg_ >= 1 && _VIreg_ <=9)
|
||||
#define mmVI(_VIreg_) (_VIreg_ - 1)
|
||||
|
||||
#include "microVU_Misc.inl"
|
||||
|
|
|
|||
Loading…
Reference in New Issue