From 3e3ffef41778c034e4c4a066bf164760a6e072a1 Mon Sep 17 00:00:00 2001 From: cottonvibes Date: Sun, 22 Mar 2009 07:36:02 +0000 Subject: [PATCH] microVU: moved stuff around, and implemented some other stuff... also added the file microVU_Analyze.inl to project. git-svn-id: http://pcsx2.googlecode.com/svn/trunk@831 96395faa-99c1-11dd-bbfe-3dabce05a288 --- pcsx2/windows/VCprojects/pcsx2_2008.vcproj | 4 + pcsx2/x86/microVU.h | 5 +- pcsx2/x86/microVU_Alloc.h | 20 ++-- pcsx2/x86/microVU_Alloc.inl | 91 +-------------- pcsx2/x86/microVU_Analyze.inl | 126 +++++++++++++++++++++ pcsx2/x86/microVU_Compile.inl | 20 +++- pcsx2/x86/microVU_Lower.inl | 118 +++++++++---------- pcsx2/x86/microVU_Misc.h | 4 +- 8 files changed, 225 insertions(+), 163 deletions(-) create mode 100644 pcsx2/x86/microVU_Analyze.inl diff --git a/pcsx2/windows/VCprojects/pcsx2_2008.vcproj b/pcsx2/windows/VCprojects/pcsx2_2008.vcproj index 7d5ea1a0b1..5a10f67c6c 100644 --- a/pcsx2/windows/VCprojects/pcsx2_2008.vcproj +++ b/pcsx2/windows/VCprojects/pcsx2_2008.vcproj @@ -2502,6 +2502,10 @@ RelativePath="..\..\x86\microVU_Alloc.inl" > + + diff --git a/pcsx2/x86/microVU.h b/pcsx2/x86/microVU.h index d755d28b61..609c97b4dd 100644 --- a/pcsx2/x86/microVU.h +++ b/pcsx2/x86/microVU.h @@ -24,6 +24,7 @@ #include "GS.h" #include "ix86/ix86.h" #include "microVU_Alloc.h" +#include "microVU_Misc.h" struct microBlock { microRegInfo pState; // Detailed State of Pipeline @@ -155,7 +156,9 @@ microVUt(void) mVUreset(); microVUt(void) mVUclose(); #endif -#include "microVU_Misc.h" +// Include all the *.inl files (Needed because C++ sucks with templates and *.cpp files) +#include "microVU_Misc.inl" +#include "microVU_Analyze.inl" #include "microVU_Alloc.inl" #include "microVU_Tables.inl" #include "microVU_Compile.inl" diff --git a/pcsx2/x86/microVU_Alloc.h b/pcsx2/x86/microVU_Alloc.h index a6eda6b6d6..8f29b71fae 100644 --- a/pcsx2/x86/microVU_Alloc.h +++ b/pcsx2/x86/microVU_Alloc.h @@ -30,20 +30,26 @@ union regInfo { struct microRegInfo { regInfo VF[32]; - regInfo Acc; u8 VI[32]; - u8 i; u8 q; u8 p; - u8 r; +}; + +struct microTempRegInfo { + regInfo VF[2]; // Holds cycle info for Fd, VF[0] = Upper Instruction, VF[1] = Lower Instruction + u8 VFreg[2]; // Index of the VF reg + u8 VI; // Holds cycle info for Id + u8 VIreg; // Index of the VI reg }; template struct microAllocInfo { - microRegInfo regs; - u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR) - u32 curPC; // Current PC - u32 cycles; // Cycles for current block + microRegInfo regs; // Pipeline info + microTempRegInfo regsTemp; // Temp Pipeline info (used so that new pipeline info isn't conflicting between upper and lower instructions in the same cycle) + u8 branch; // 0 = No Branch, 1 = Branch, 2 = Conditional Branch, 3 = Jump (JALR/JR) + u32 curPC; // Current PC + u32 cycles; // Cycles for current block + u32 maxStall; // Helps in computing stalls (stores the max amount of cycles to stall for the current opcodes) u32 info[pSize];// bit 00 = Lower Instruction is NOP // bit 01 // bit 02 diff --git a/pcsx2/x86/microVU_Alloc.inl b/pcsx2/x86/microVU_Alloc.inl index 7b165725c6..06e21c4456 100644 --- a/pcsx2/x86/microVU_Alloc.inl +++ b/pcsx2/x86/microVU_Alloc.inl @@ -19,96 +19,6 @@ #pragma once #ifdef PCSX2_MICROVU -//------------------------------------------------------------------ -// Micro VU - recPass 0 Functions -//------------------------------------------------------------------ - -//------------------------------------------------------------------ -// FMAC1 - Normal FMAC Opcodes -//------------------------------------------------------------------ - -#define aReg(x) mVUallocInfo.regs.VF[x] -#define aMax(x, y) ((x > y) ? x : y) - -#define analyzeReg1(reg) { \ - if (reg) { \ - if (_X) { mVal = aMax(mVal, aReg(reg).x); } \ - if (_Y) { mVal = aMax(mVal, aReg(reg).y); } \ - if (_Z) { mVal = aMax(mVal, aReg(reg).z); } \ - if (_W) { mVal = aMax(mVal, aReg(reg).w); } \ - } \ -} - -#define analyzeReg2(reg) { \ - if (reg) { \ - if (_X) { aReg(reg).x = 4; } \ - if (_Y) { aReg(reg).y = 4; } \ - if (_Z) { aReg(reg).z = 4; } \ - if (_W) { aReg(reg).w = 4; } \ - } \ -} - -microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { - microVU* mVU = mVUx; - int mVal = 0; - mVUinfo |= _doStatus; - analyzeReg1(Fs); - analyzeReg1(Ft); - incCycles(mVal); - analyzeReg2(Fd); -} - -//------------------------------------------------------------------ -// FMAC2 - ABS/FTOI/ITOF Opcodes -//------------------------------------------------------------------ - -microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { - microVU* mVU = mVUx; - int mVal = 0; - analyzeReg1(Fs); - incCycles(mVal); - analyzeReg2(Ft); -} - -//------------------------------------------------------------------ -// FMAC3 - BC(xyzw) FMAC Opcodes -//------------------------------------------------------------------ - -#define analyzeReg3(reg) { \ - if (reg) { \ - if (_bc_x) { mVal = aMax(mVal, aReg(reg).x); } \ - else if (_bc_y) { mVal = aMax(mVal, aReg(reg).y); } \ - else if (_bc_z) { mVal = aMax(mVal, aReg(reg).z); } \ - else { mVal = aMax(mVal, aReg(reg).w); } \ - } \ -} - -microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { - microVU* mVU = mVUx; - int mVal = 0; - mVUinfo |= _doStatus; - analyzeReg1(Fs); - analyzeReg3(Ft); - incCycles(mVal); - analyzeReg2(Fd); -} - -//------------------------------------------------------------------ -// FMAC4 - Clip FMAC Opcode -//------------------------------------------------------------------ - -#define analyzeReg4(reg) { \ - if (reg) { mVal = aMax(mVal, aReg(reg).w); } \ -} - -microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { - microVU* mVU = mVUx; - int mVal = 0; - analyzeReg1(Fs); - analyzeReg4(Ft); - incCycles(mVal); -} - //------------------------------------------------------------------ // Micro VU - recPass 1 Functions //------------------------------------------------------------------ @@ -855,4 +765,5 @@ microVUt(void) mVUallocVIb(int GPRreg, int _reg_) { if (!_reg_ && (_fxf_ < 3)) { XOR32RtoR(GPRreg, GPRreg); } \ else { MOV32MtoR(GPRreg, (uptr)&mVU->regs->VF[_reg_].UL[0]); } \ } + #endif //PCSX2_MICROVU diff --git a/pcsx2/x86/microVU_Analyze.inl b/pcsx2/x86/microVU_Analyze.inl new file mode 100644 index 0000000000..23050cd585 --- /dev/null +++ b/pcsx2/x86/microVU_Analyze.inl @@ -0,0 +1,126 @@ +/* Pcsx2 - Pc Ps2 Emulator +* Copyright (C) 2009 Pcsx2-Playground Team +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA +*/ + +#pragma once +#ifdef PCSX2_MICROVU + +//------------------------------------------------------------------ +// Micro VU - recPass 0 Functions +//------------------------------------------------------------------ + +//------------------------------------------------------------------ +// FMAC1 - Normal FMAC Opcodes +//------------------------------------------------------------------ + +#define aReg(x) mVUallocInfo.regs.VF[x] +#define bReg(x) mVUallocInfo.regsTemp.VFreg[0] = x; mVUallocInfo.regsTemp.VF[0] +#define aMax(x, y) ((x > y) ? x : y) + +#define analyzeReg1(reg) { \ + if (reg) { \ + if (_X) { mVUstall = aMax(mVUstall, aReg(reg).x); } \ + if (_Y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \ + if (_Z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \ + if (_W) { mVUstall = aMax(mVUstall, aReg(reg).w); } \ + } \ +} + +#define analyzeReg2(reg) { \ + if (reg) { \ + if (_X) { bReg(reg).x = 4; } \ + if (_Y) { bReg(reg).y = 4; } \ + if (_Z) { bReg(reg).z = 4; } \ + if (_W) { bReg(reg).w = 4; } \ + } \ +} + +microVUt(void) mVUanalyzeFMAC1(int Fd, int Fs, int Ft) { + microVU* mVU = mVUx; + mVUinfo |= _doStatus; + analyzeReg1(Fs); + analyzeReg1(Ft); + analyzeReg2(Fd); +} + +//------------------------------------------------------------------ +// FMAC2 - ABS/FTOI/ITOF Opcodes +//------------------------------------------------------------------ + +microVUt(void) mVUanalyzeFMAC2(int Fs, int Ft) { + microVU* mVU = mVUx; + analyzeReg1(Fs); + analyzeReg2(Ft); +} + +//------------------------------------------------------------------ +// FMAC3 - BC(xyzw) FMAC Opcodes +//------------------------------------------------------------------ + +#define analyzeReg3(reg) { \ + if (reg) { \ + if (_bc_x) { mVUstall = aMax(mVUstall, aReg(reg).x); } \ + else if (_bc_y) { mVUstall = aMax(mVUstall, aReg(reg).y); } \ + else if (_bc_z) { mVUstall = aMax(mVUstall, aReg(reg).z); } \ + else { mVUstall = aMax(mVUstall, aReg(reg).w); } \ + } \ +} + +microVUt(void) mVUanalyzeFMAC3(int Fd, int Fs, int Ft) { + microVU* mVU = mVUx; + mVUinfo |= _doStatus; + analyzeReg1(Fs); + analyzeReg3(Ft); + analyzeReg2(Fd); +} + +//------------------------------------------------------------------ +// FMAC4 - Clip FMAC Opcode +//------------------------------------------------------------------ + +#define analyzeReg4(reg) { \ + if (reg) { mVUstall = aMax(mVUstall, aReg(reg).w); } \ +} + +microVUt(void) mVUanalyzeFMAC4(int Fs, int Ft) { + microVU* mVU = mVUx; + analyzeReg1(Fs); + analyzeReg4(Ft); +} + +//------------------------------------------------------------------ +// FDIV - DIV/SQRT/RSQRT Opcodes +//------------------------------------------------------------------ + +#define analyzeReg5(reg, fxf) { \ + if (reg) { \ + switch (fxf) { \ + case 0: mVUstall = aMax(mVUstall, aReg(reg).x); break; \ + case 1: mVUstall = aMax(mVUstall, aReg(reg).y); break; \ + case 2: mVUstall = aMax(mVUstall, aReg(reg).z); break; \ + case 3: mVUstall = aMax(mVUstall, aReg(reg).w); break; \ + } \ + } \ +} + +microVUt(void) mVUanalyzeFDIV(int Fs, int Fsf, int Ft, int Ftf) { + microVU* mVU = mVUx; + analyzeReg5(Fs, Fsf); + analyzeReg5(Ft, Ftf); +} + +#endif //PCSX2_MICROVU diff --git a/pcsx2/x86/microVU_Compile.inl b/pcsx2/x86/microVU_Compile.inl index 0574d9faa3..7614bb9224 100644 --- a/pcsx2/x86/microVU_Compile.inl +++ b/pcsx2/x86/microVU_Compile.inl @@ -31,10 +31,6 @@ #define mVUdebugStuff1() {} #endif -#define curI mVUcurProg.data[iPC] -#define setCode() { mVU->code = curI; } -#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); } - #define createBlock(blockEndPtr) { \ block.pipelineState = pipelineState; \ block.x86ptrStart = x86ptrStart; \ @@ -45,6 +41,19 @@ } \ } +#define curI mVUcurProg.data[iPC] +#define setCode() { mVU->code = curI; } +#define incPC(x) { iPC = ((iPC + x) & (mVU->progSize-1)); setCode(); } +#define startLoop() { mVUdebugStuff1(); mVUstall = 0; memset(&mVUregsTemp, 0, sizeof(mVUregsTemp)); } + +microVUt(void) mVUsetCycles() { + microVU* mVU = mVUx; + incCycles(mVUstall); + mVUregs.VF[mVUregsTemp.VFreg[0]].reg = mVUregsTemp.VF[0].reg; + mVUregs.VF[mVUregsTemp.VFreg[1]].reg = mVUregsTemp.VF[1].reg; + mVUregs.VI[mVUregsTemp.VIreg] = mVUregsTemp.VI; +} + microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState, u8* x86ptrStart) { microVU* mVU = mVUx; microBlock block; @@ -57,12 +66,13 @@ microVUx(void) mVUcompile(u32 startPC, u32 pipelineState, microRegInfo* pState, // First Pass setCode(); for (;;) { - mVUdebugStuff1(); + startLoop(); mVUopU(); if (curI & _Ebit_) { mVUbranch = 5; } if (curI & _MDTbit_) { mVUbranch = 4; } if (curI & _Ibit_) { incPC(1); mVUinfo |= _isNOP; } else { incPC(1); mVUopL(); } + mVUsetCycles(); if (mVUbranch == 4) { mVUbranch = 0; mVUinfo |= _isEOB; break; } else if (mVUbranch == 5) { mVUbranch = 4; } else if (mVUbranch) { mVUbranch = 4; mVUinfo |= _isBranch; } diff --git a/pcsx2/x86/microVU_Lower.inl b/pcsx2/x86/microVU_Lower.inl index 817cc46b1d..2001be8a37 100644 --- a/pcsx2/x86/microVU_Lower.inl +++ b/pcsx2/x86/microVU_Lower.inl @@ -25,7 +25,7 @@ microVUf(void) mVU_DIV() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { //u8 *pjmp;, *pjmp1; u32 *ajmp32, *bjmp32; @@ -72,7 +72,7 @@ microVUf(void) mVU_DIV() { } microVUf(void) mVU_SQRT() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { //u8* pjmp; getReg5(xmmFt, _Ft_, _Ftf_); @@ -94,7 +94,7 @@ microVUf(void) mVU_SQRT() { } microVUf(void) mVU_RSQRT() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { u8 *ajmp8, *bjmp8; @@ -162,7 +162,7 @@ microVUt(void) mVU_EATAN_() { } microVUf(void) mVU_EATAN() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -177,7 +177,7 @@ microVUf(void) mVU_EATAN() { } microVUf(void) mVU_EATANxy() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFt, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x01); @@ -193,7 +193,7 @@ microVUf(void) mVU_EATANxy() { } microVUf(void) mVU_EATANxz() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFt, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmFs, xmmFt, 0x02); @@ -215,7 +215,7 @@ microVUf(void) mVU_EATANxz() { } microVUf(void) mVU_EEXP() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -261,7 +261,7 @@ microVUt(void) mVU_sumXYZ() { } microVUf(void) mVU_ELENG() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -272,7 +272,7 @@ microVUf(void) mVU_ELENG() { } microVUf(void) mVU_ERCPR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -285,7 +285,7 @@ microVUf(void) mVU_ERCPR() { } microVUf(void) mVU_ERLENG() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -299,7 +299,7 @@ microVUf(void) mVU_ERLENG() { } microVUf(void) mVU_ERSADD() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -313,7 +313,7 @@ microVUf(void) mVU_ERSADD() { } microVUf(void) mVU_ERSQRT() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -326,7 +326,7 @@ microVUf(void) mVU_ERSQRT() { } microVUf(void) mVU_ESADD() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -342,7 +342,7 @@ microVUf(void) mVU_ESADD() { } microVUf(void) mVU_ESIN() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -367,7 +367,7 @@ microVUf(void) mVU_ESIN() { } microVUf(void) mVU_ESQRT() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg5(xmmFs, _Fs_, _Fsf_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -377,7 +377,7 @@ microVUf(void) mVU_ESQRT() { } microVUf(void) mVU_ESUM() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { getReg6(xmmFs, _Fs_); SSE2_PSHUFD_XMM_to_XMM(xmmPQ, xmmPQ, writeP ? 0x27 : 0xC6); // Flip xmmPQ to get Valid P instance @@ -392,7 +392,7 @@ microVUf(void) mVU_ESUM() { microVUf(void) mVU_FCAND() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocCFLAGa(gprT1, fvcInstance); AND32ItoR(gprT1, _Imm24_); @@ -403,7 +403,7 @@ microVUf(void) mVU_FCAND() { } microVUf(void) mVU_FCEQ() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocCFLAGa(gprT1, fvcInstance); XOR32ItoR(gprT1, _Imm24_); @@ -414,7 +414,7 @@ microVUf(void) mVU_FCEQ() { } microVUf(void) mVU_FCGET() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocCFLAGa(gprT1, fvcInstance); AND32ItoR(gprT1, 0xfff); @@ -423,7 +423,7 @@ microVUf(void) mVU_FCGET() { } microVUf(void) mVU_FCOR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocCFLAGa(gprT1, fvcInstance); OR32ItoR(gprT1, _Imm24_); @@ -434,7 +434,7 @@ microVUf(void) mVU_FCOR() { } microVUf(void) mVU_FCSET() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { MOV32ItoR(gprT1, _Imm24_); mVUallocCFLAGb(gprT1, fcInstance); @@ -443,7 +443,7 @@ microVUf(void) mVU_FCSET() { microVUf(void) mVU_FMAND() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocMFLAGa(gprT1, fvmInstance); mVUallocVIa(gprT2, _Fs_); @@ -453,7 +453,7 @@ microVUf(void) mVU_FMAND() { } microVUf(void) mVU_FMEQ() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocMFLAGa(gprT1, fvmInstance); mVUallocVIa(gprT2, _Fs_); @@ -465,7 +465,7 @@ microVUf(void) mVU_FMEQ() { } microVUf(void) mVU_FMOR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocMFLAGa(gprT1, fvmInstance); mVUallocVIa(gprT2, _Fs_); @@ -476,7 +476,7 @@ microVUf(void) mVU_FMOR() { microVUf(void) mVU_FSAND() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocSFLAGa(gprT1, fvsInstance); AND16ItoR(gprT1, _Imm12_); @@ -485,7 +485,7 @@ microVUf(void) mVU_FSAND() { } microVUf(void) mVU_FSEQ() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocSFLAGa(gprT1, fvsInstance); XOR16ItoR(gprT1, _Imm12_); @@ -496,7 +496,7 @@ microVUf(void) mVU_FSEQ() { } microVUf(void) mVU_FSOR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocSFLAGa(gprT1, fvsInstance); OR16ItoR(gprT1, _Imm12_); @@ -505,7 +505,7 @@ microVUf(void) mVU_FSOR() { } microVUf(void) mVU_FSSET() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { int flagReg; getFlagReg(flagReg, fsInstance); @@ -515,7 +515,7 @@ microVUf(void) mVU_FSSET() { microVUf(void) mVU_IADD() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { @@ -528,7 +528,7 @@ microVUf(void) mVU_IADD() { } microVUf(void) mVU_IADDI() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); ADD16ItoR(gprT1, _Imm5_); @@ -537,7 +537,7 @@ microVUf(void) mVU_IADDI() { } microVUf(void) mVU_IADDIU() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); ADD16ItoR(gprT1, _Imm12_); @@ -546,7 +546,7 @@ microVUf(void) mVU_IADDIU() { } microVUf(void) mVU_IAND() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { @@ -558,7 +558,7 @@ microVUf(void) mVU_IAND() { } microVUf(void) mVU_IOR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); if (_Ft_ != _Fs_) { @@ -570,7 +570,7 @@ microVUf(void) mVU_IOR() { } microVUf(void) mVU_ISUB() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (_Ft_ != _Fs_) { mVUallocVIa(gprT1, _Fs_); @@ -586,7 +586,7 @@ microVUf(void) mVU_ISUB() { } microVUf(void) mVU_ISUBIU() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT1, _Fs_); SUB16ItoR(gprT1, _Imm12_); @@ -596,7 +596,7 @@ microVUf(void) mVU_ISUBIU() { microVUf(void) mVU_MOVE() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ } + if (!recPass) { /*If (!_Ft_ || (_Ft_ == _Fs_)) nop();*/ } else { mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], _X_Y_Z_W); mVUsaveReg(xmmT1, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); @@ -604,7 +604,7 @@ microVUf(void) mVU_MOVE() { } microVUf(void) mVU_MFIR() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { mVUallocVIa(gprT1, _Fs_); MOVSX32R16toR(gprT1, gprT1); @@ -615,7 +615,7 @@ microVUf(void) mVU_MFIR() { } microVUf(void) mVU_MFP() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { getPreg(xmmFt); mVUsaveReg(xmmFt, (uptr)&mVU->regs->VF[_Ft_].UL[0], _X_Y_Z_W); @@ -623,7 +623,7 @@ microVUf(void) mVU_MFP() { } microVUf(void) mVU_MTIR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { MOVZX32M16toR(gprT1, (uptr)&mVU->regs->VF[_Fs_].UL[_Fsf_]); mVUallocVIb(gprT1, _Ft_); @@ -631,7 +631,7 @@ microVUf(void) mVU_MTIR() { } microVUf(void) mVU_MR32() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { mVUloadReg(xmmT1, (uptr)&mVU->regs->VF[_Fs_].UL[0], (_X_Y_Z_W == 8) ? 4 : 15); if (_X_Y_Z_W != 8) { SSE2_PSHUFD_XMM_to_XMM(xmmT1, xmmT1, 0x39); } @@ -641,7 +641,7 @@ microVUf(void) mVU_MR32() { microVUf(void) mVU_ILW() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { if (!_Fs_) { MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + getVUmem(_Imm11_) + offsetSS ); @@ -659,7 +659,7 @@ microVUf(void) mVU_ILW() { } microVUf(void) mVU_ILWR() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { if (!_Fs_) { MOVZX32M16toR( gprT1, (uptr)mVU->regs->Mem + offsetSS ); @@ -676,7 +676,7 @@ microVUf(void) mVU_ILWR() { } microVUf(void) mVU_ISW() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Fs_) { int imm = getVUmem(_Imm11_); @@ -700,7 +700,7 @@ microVUf(void) mVU_ISW() { } microVUf(void) mVU_ISWR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Fs_) { mVUallocVIa(gprT1, _Ft_); @@ -723,7 +723,7 @@ microVUf(void) mVU_ISWR() { microVUf(void) mVU_LQ() { microVU* mVU = mVUx; - if (recPass == 0) { /*If (!_Ft_) nop();*/ } + if (!recPass) { /*If (!_Ft_) nop();*/ } else { if (!_Fs_) { mVUloadReg(xmmFt, (uptr)mVU->regs->Mem + getVUmem(_Imm11_), _X_Y_Z_W); @@ -740,7 +740,7 @@ microVUf(void) mVU_LQ() { } microVUf(void) mVU_LQD() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Fs_ && _Ft_) { mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); @@ -760,7 +760,7 @@ microVUf(void) mVU_LQD() { } microVUf(void) mVU_LQI() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Fs_ && _Ft_) { mVUloadReg(xmmFt, (uptr)mVU->regs->Mem, _X_Y_Z_W); @@ -781,7 +781,7 @@ microVUf(void) mVU_LQI() { } microVUf(void) mVU_SQ() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Ft_) { getReg7(xmmFs, _Fs_); @@ -798,7 +798,7 @@ microVUf(void) mVU_SQ() { } microVUf(void) mVU_SQD() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Ft_) { getReg7(xmmFs, _Fs_); @@ -816,7 +816,7 @@ microVUf(void) mVU_SQD() { } microVUf(void) mVU_SQI() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (!_Ft_) { getReg7(xmmFs, _Fs_); @@ -836,7 +836,7 @@ microVUf(void) mVU_SQI() { microVUf(void) mVU_RINIT() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprR, _Fs_, _Fsf_); @@ -857,12 +857,12 @@ microVUt(void) mVU_RGET_() { } microVUf(void) mVU_RGET() { microVU* mVU = mVUx; - if (recPass == 0) { /*if (!_Ft_) nop();*/ } + if (!recPass) { /*if (!_Ft_) nop();*/ } else { mVU_RGET_(); } } microVUf(void) mVU_RNEXT() { microVU* mVU = mVUx; - if (recPass == 0) { /*if (!_Ft_) nop();*/ } + if (!recPass) { /*if (!_Ft_) nop();*/ } else { // algorithm from www.project-fao.org MOV32RtoR(gprT1, gprR); @@ -883,7 +883,7 @@ microVUf(void) mVU_RNEXT() { } microVUf(void) mVU_RXOR() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { if (_Fs_ || (_Fsf_ == 3)) { getReg8(gprT1, _Fs_, _Fsf_); @@ -895,18 +895,18 @@ microVUf(void) mVU_RXOR() { microVUf(void) mVU_WAITP() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else {} } microVUf(void) mVU_WAITQ() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else {} } microVUf(void) mVU_XTOP() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->top); mVUallocVIb(gprT1, _Ft_); @@ -914,7 +914,7 @@ microVUf(void) mVU_XTOP() { } microVUf(void) mVU_XITOP() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { MOVZX32M16toR( gprT1, (uptr)&mVU->regs->vifRegs->itop ); mVUallocVIb(gprT1, _Ft_); @@ -934,7 +934,7 @@ void __fastcall mVU_XGKICK1(u32 addr) { mVU_XGKICK_<1>(addr); } microVUf(void) mVU_XGKICK() { microVU* mVU = mVUx; - if (recPass == 0) {} + if (!recPass) {} else { mVUallocVIa(gprT2, _Fs_); // gprT2 = ECX for __fastcall if (!vuIndex) CALLFunc((uptr)mVU_XGKICK0); diff --git a/pcsx2/x86/microVU_Misc.h b/pcsx2/x86/microVU_Misc.h index 956b1b1378..cecee4105e 100644 --- a/pcsx2/x86/microVU_Misc.h +++ b/pcsx2/x86/microVU_Misc.h @@ -143,6 +143,9 @@ declareAllVariables #define mVUallocInfo mVU->prog.prog[mVU->prog.cur].allocInfo #define mVUbranch mVUallocInfo.branch #define mVUcycles mVUallocInfo.cycles +#define mVUstall mVUallocInfo.maxStall +#define mVUregs mVUallocInfo.regs +#define mVUregsTemp mVUallocInfo.regsTemp #define mVUinfo mVUallocInfo.info[mVUallocInfo.curPC / 2] #define iPC mVUallocInfo.curPC #define xPC ((iPC / 2) * 8) @@ -195,4 +198,3 @@ declareAllVariables #define isMMX(_VIreg_) (_VIreg_ >= 1 && _VIreg_ <=9) #define mmVI(_VIreg_) (_VIreg_ - 1) -#include "microVU_Misc.inl"