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feature/cached-interp
feature/dynarec
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medusa
optimization/arm-inline
optimization/arm-noinline
optimization/cpu-alu
optimization/dma-caching
optimization/invert-window
optimization/ls-reduce
optimization/negative-clock2
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optimization/staging
optimization/thumb-notrunc
optimization/unify-barrel
optimization/video
optimization/video-tests/affine1
optimization/video-tests/affine2
optimization/video-tests/affine3
optimization/video-tests/localy
optimization/video-tests/obj-postprocess
port/crucible
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0.1.0
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0.10.3
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0.2.0
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0.4.0
0.4.1
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0.5.2
0.6-b1
0.6.0
0.6.1
0.6.2
0.6.3
0.7-b1
0.7.0
0.7.1
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0.7.3
0.8-b1
0.8.0
0.8.1
0.8.2
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0.8.4
0.9.0
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medusa-a1
medusa-a2
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0.1
0.10
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appveyor
feature/cached-interp
feature/dynarec
feature/sio-dolphin
master
medusa
optimization/arm-inline
optimization/arm-noinline
optimization/cpu-alu
optimization/dma-caching
optimization/invert-window
optimization/ls-reduce
optimization/negative-clock2
optimization/page-align
optimization/staging
optimization/thumb-notrunc
optimization/unify-barrel
optimization/video
optimization/video-tests/affine1
optimization/video-tests/affine2
optimization/video-tests/affine3
optimization/video-tests/localy
optimization/video-tests/obj-postprocess
port/crucible
translations
travis
#1
#100
#100
#1014
#1015
#1017
#1019
#1021
#1024
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0.1.0
0.1.1
0.10.0
0.10.1
0.10.2
0.10.3
0.10.4
0.2.0
0.2.1
0.3.0
0.3.1
0.3.2
0.4.0
0.4.1
0.5.0
0.5.1
0.5.2
0.6-b1
0.6.0
0.6.1
0.6.2
0.6.3
0.7-b1
0.7.0
0.7.1
0.7.2
0.7.3
0.8-b1
0.8.0
0.8.1
0.8.2
0.8.3
0.8.4
0.9.0
0.9.1
0.9.2
0.9.3
medusa-a1
medusa-a2
-
7b82cc0040
Fill in LDR/STR block
Jeffrey Pfau
2013-04-06 13:05:53 -0700 -
befba57fe6
Simple error checking
Jeffrey Pfau
2013-04-06 04:34:19 -0700 -
9efc945f1b
Add store callbacks
Jeffrey Pfau
2013-04-06 04:20:44 -0700 -
96da9c7ef1
Partially implement LDR/STR and friends
Jeffrey Pfau
2013-04-06 04:16:27 -0700 -
92e74a78e1
Apparently I can't count to 8
Jeffrey Pfau
2013-04-06 02:49:54 -0700 -
cb2469c4f4
Filler for more instructions
Jeffrey Pfau
2013-04-06 00:32:01 -0700 -
a01fc986a3
Begin GBA structure
Jeffrey Pfau
2013-04-05 02:17:22 -0700 -
cd07dee7b1
Implement immediate shifter
Jeffrey Pfau
2013-04-05 00:43:47 -0700 -
c07df4a337
Fill in immediates
Jeffrey Pfau
2013-04-04 03:12:22 -0700 -
63f6f53a80
Implement BIC, MOV, MVN, ORR
Jeffrey Pfau
2013-04-04 02:42:17 -0700 -
dbee1e871e
Add stubs, including for illegal instructions
Jeffrey Pfau
2013-04-04 02:36:53 -0700 -
e093960316
Fill in more opcodes, implement CMN, CMP, TEQ, TST
Jeffrey Pfau
2013-04-04 02:31:32 -0700 -
fd4ee12eb5
Implement ADD, ADC, RSB, RSC, SUB
Jeffrey Pfau
2013-04-04 02:04:51 -0700 -
c1a8042db4
Fill in more opcodes, implement EOR
Jeffrey Pfau
2013-04-04 01:27:51 -0700 -
4025bf89f2
Add boilerplate for instructions
Jeffrey Pfau
2013-04-04 00:46:50 -0700 -
bf72532715
Add more framework for loading instructions
Jeffrey Pfau
2013-04-03 22:34:49 -0700 -
009bef870c
Initial commit
Jeffrey Pfau
2013-04-03 22:12:15 -0700