2017-08-13 01:10:05 +00:00
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; this file was created with wlalink by ville helin <vhelin@iki.fi>.
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2019-07-06 22:21:04 +00:00
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; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing2-GS.gb".
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2017-08-13 01:10:05 +00:00
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[labels]
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2019-07-06 22:21:04 +00:00
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01:47f0 check_asserts_cb
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01:4842 check_asserts_cb@check_asserts
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01:4864 check_asserts_cb@fail0
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01:4870 check_asserts_cb@ok0
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01:487a check_asserts_cb@skip0
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01:4885 check_asserts_cb@out0
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01:489c check_asserts_cb@fail1
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01:48a8 check_asserts_cb@ok1
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01:48b2 check_asserts_cb@skip1
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01:48bd check_asserts_cb@out1
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01:48dd check_asserts_cb@fail2
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01:48e9 check_asserts_cb@ok2
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01:48f3 check_asserts_cb@skip2
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01:48fe check_asserts_cb@out2
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01:4915 check_asserts_cb@fail3
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01:4921 check_asserts_cb@ok3
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01:492b check_asserts_cb@skip3
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01:4936 check_asserts_cb@out3
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01:4956 check_asserts_cb@fail4
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01:4962 check_asserts_cb@ok4
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01:496c check_asserts_cb@skip4
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01:4977 check_asserts_cb@out4
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01:498e check_asserts_cb@fail5
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01:499a check_asserts_cb@ok5
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01:49a4 check_asserts_cb@skip5
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01:49af check_asserts_cb@out5
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01:49cf check_asserts_cb@fail6
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01:49db check_asserts_cb@ok6
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01:49e5 check_asserts_cb@skip6
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01:49f0 check_asserts_cb@out6
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01:4a07 check_asserts_cb@fail7
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01:4a13 check_asserts_cb@ok7
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01:4a1d check_asserts_cb@skip7
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01:4a28 check_asserts_cb@out7
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01:4b7b clear_vram
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01:4b3a disable_lcd_safe
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01:4b40 disable_lcd_safe@wait_ly_0
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01:4b8f memcpy
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01:4b98 memset
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01:4b58 print_hex4
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01:4b85 print_hex8
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01:4ba8 print_inline_string
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01:4b64 print_load_font
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01:4b70 print_newline
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01:4a2b print_reg_dump
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01:4ba1 print_string
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01:4ab0 quit
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01:4ac5 quit@cb_return
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01:4aca quit@wait_ly_1
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01:4ad0 quit@wait_ly_2
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01:4ad6 quit@wait_ly_3
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01:4adc quit@wait_ly_4
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01:4ae6 quit@success
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01:4b0d quit@failure
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01:4b22 quit@halt
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01:4b23 quit@halt_execution_0
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01:4b26 reset_screen
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01:4b49 serial_send_byte
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2017-08-13 01:10:05 +00:00
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01:4000 font
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2019-07-06 22:21:04 +00:00
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00:ff80 v_regs_save
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00:ff80 v_regs_save.reg_f
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00:ff81 v_regs_save.reg_a
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00:ff82 v_regs_save.reg_c
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00:ff83 v_regs_save.reg_b
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00:ff84 v_regs_save.reg_e
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00:ff85 v_regs_save.reg_d
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00:ff86 v_regs_save.reg_l
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00:ff87 v_regs_save.reg_h
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00:ff88 v_regs_flags
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00:ff89 v_regs_assert
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00:ff89 v_regs_assert.reg_f
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00:ff8a v_regs_assert.reg_a
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00:ff8b v_regs_assert.reg_c
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00:ff8c v_regs_assert.reg_b
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00:ff8d v_regs_assert.reg_e
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00:ff8e v_regs_assert.reg_d
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00:ff8f v_regs_assert.reg_l
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00:ff90 v_regs_assert.reg_h
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00:0150 main
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00:0151 main@wait_ly_5
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2017-08-13 01:10:05 +00:00
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00:0167 test_round1
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00:0183 _delay_long_time_0
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00:0193 finish_round1
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00:01a2 test_round2
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00:01bd _delay_long_time_1
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00:01ce finish_round2
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00:01dd test_round3
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00:01f8 finish_round3
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00:0207 test_round4
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00:0221 finish_round4
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2019-07-06 22:21:04 +00:00
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00:026d fail_halt
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00:0274 fail_halt@quit_inline_1
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00:0288 fail_round1
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00:028f fail_round1@quit_inline_2
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00:02a6 fail_round2
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00:02ad fail_round2@quit_inline_3
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00:02c4 fail_round3
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00:02cb fail_round3@quit_inline_4
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00:02e2 fail_round4
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00:02e9 fail_round4@quit_inline_5
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[definitions]
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0000023b _sizeof_check_asserts_cb
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0000000a _sizeof_clear_vram
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0000000f _sizeof_disable_lcd_safe
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00000009 _sizeof_memcpy
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00000009 _sizeof_memset
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0000000c _sizeof_print_hex4
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0000000a _sizeof_print_hex8
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00000006 _sizeof_print_inline_string
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0000000c _sizeof_print_load_font
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0000000b _sizeof_print_newline
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00000085 _sizeof_print_reg_dump
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00000007 _sizeof_print_string
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00000076 _sizeof_quit
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00000014 _sizeof_reset_screen
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0000000f _sizeof_serial_send_byte
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000007f0 _sizeof_font
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00000008 _sizeof_v_regs_save
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00000001 _sizeof_v_regs_save.reg_f
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00000001 _sizeof_v_regs_save.reg_a
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00000001 _sizeof_v_regs_save.reg_c
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00000001 _sizeof_v_regs_save.reg_b
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00000001 _sizeof_v_regs_save.reg_e
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00000001 _sizeof_v_regs_save.reg_d
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00000001 _sizeof_v_regs_save.reg_l
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00000001 _sizeof_v_regs_save.reg_h
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00000001 _sizeof_v_regs_flags
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00000008 _sizeof_v_regs_assert
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00000001 _sizeof_v_regs_assert.reg_f
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00000001 _sizeof_v_regs_assert.reg_a
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00000001 _sizeof_v_regs_assert.reg_c
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00000001 _sizeof_v_regs_assert.reg_b
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00000001 _sizeof_v_regs_assert.reg_e
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00000001 _sizeof_v_regs_assert.reg_d
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00000001 _sizeof_v_regs_assert.reg_l
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00000001 _sizeof_v_regs_assert.reg_h
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00000017 _sizeof_main
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0000001c _sizeof_test_round1
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00000010 _sizeof__delay_long_time_0
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0000000f _sizeof_finish_round1
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0000001b _sizeof_test_round2
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00000011 _sizeof__delay_long_time_1
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0000000f _sizeof_finish_round2
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0000001b _sizeof_test_round3
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0000000f _sizeof_finish_round3
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0000001a _sizeof_test_round4
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0000004c _sizeof_finish_round4
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0000001b _sizeof_fail_halt
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0000001e _sizeof_fail_round1
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0000001e _sizeof_fail_round2
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0000001e _sizeof_fail_round3
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