cinema: Update mooneye-gb tests

cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/test.sym

@@ -1,206 +1,144 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0150 _wait_ly_4
-00:0156 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0150 main@wait_ly_5
+00:0156 main@wait_ly_6
 00:0180 test_finish
-00:01c4 wram_test
-00:01d3 hiram_test
-00:01d3 test_round1
-00:01d5 _wait_ly_6
-00:01db _wait_ly_7
-00:01f0 finish_round1
-00:01ff test_round2
-00:0201 _wait_ly_8
-00:0207 _wait_ly_9
-00:021d finish_round2
-00:c014 result_tmp
-00:c016 result_round1
+00:01c9 wram_test
+00:01d8 hiram_test
+00:01d8 test_round1
+00:01da test_round1@wait_ly_7
+00:01e0 test_round1@wait_ly_8
+00:01f5 finish_round1
+00:0204 test_round2
+00:0206 test_round2@wait_ly_9
+00:020c test_round2@wait_ly_10
+00:0222 finish_round2
+00:ff91 result_tmp
+00:ff93 result_round1
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_result_tmp
+00000002 _sizeof_result_round1
+00000030 _sizeof_main
+00000049 _sizeof_test_finish
+0000000f _sizeof_wram_test
+00000000 _sizeof_hiram_test
+0000001d _sizeof_test_round1
+0000000f _sizeof_finish_round1
+0000001e _sizeof_test_round2

cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym

@@ -1,212 +1,50 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:016f test_finish
-00:0183 _wait_ly_4
-00:0189 _wait_ly_5
-00:019f _print_results_halt_1
-00:01a2 _test_ok_cb_0
-00:01aa _print_sl_data55
-00:01b2 _print_sl_out55
-00:01b5 fail_1
-00:01c9 _wait_ly_6
-00:01cf _wait_ly_7
-00:01e5 _print_results_halt_2
-00:01e8 _test_failure_cb_0
-00:01f0 _print_sl_data56
-00:01fd _print_sl_out56
-00:0200 fail_0
-00:0214 _wait_ly_8
-00:021a _wait_ly_9
-00:0230 _print_results_halt_3
-00:0233 _test_failure_cb_1
-00:023b _print_sl_data57
-00:0248 _print_sl_out57
+00:0176 test_finish@quit_inline_1
+00:0187 fail_1
+00:018e fail_1@quit_inline_2
+00:01a4 fail_0
+00:01ab fail_0@quit_inline_3
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000001f _sizeof_main
+00000018 _sizeof_test_finish
+0000001d _sizeof_fail_1

cinema/gb/mooneye-gb/acceptance/bits/reg_f/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/reg_f.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/reg_f.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0160 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000010 _sizeof_main

cinema/gb/mooneye-gb/acceptance/bits/unused_hwio-GS/test.sym

@@ -1,194 +1,32 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/unused_hwio-GS.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/unused_hwio-GS.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c017 regs_save
-00:c017 regs_save.f
-00:c018 regs_save.a
-00:c019 regs_save.c
-00:c01a regs_save.b
-00:c01b regs_save.e
-00:c01c regs_save.d
-00:c01d regs_save.l
-00:c01e regs_save.h
-00:c01f regs_flags
-00:c020 regs_assert
-00:c020 regs_assert.f
-00:c021 regs_assert.a
-00:c022 regs_assert.c
-00:c023 regs_assert.b
-00:c024 regs_assert.e
-00:c025 regs_assert.d
-00:c026 regs_assert.l
-00:c027 regs_assert.h
-00:c028 memdump_len
-00:c029 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:0150 main
 00:0161 _test_data_0
 00:0177 _finish_0
 00:0187 _test_data_1
@@ -497,39 +335,357 @@
 00:1807 _finish_152
 00:1817 _test_data_153
 00:182d _finish_153
-00:1841 _wait_ly_4
-00:1847 _wait_ly_5
-00:185d _print_results_halt_1
-00:1860 _test_ok_cb_0
-00:1868 _print_sl_data55
-00:1870 _print_sl_out55
-00:1873 run_testcase
-00:189e _wait_ly_6
-00:18a4 _wait_ly_7
-00:18ba _print_results_halt_2
-00:18bd test_failure_cb
-00:18c5 _print_sl_data56
-00:18d1 _print_sl_out56
-00:18df _print_sl_data57
-00:18e3 _print_sl_out57
-00:18f1 _print_sl_data58
-00:1901 _print_sl_out58
-00:190f _print_sl_data59
-00:191c _print_sl_out59
-00:192d _print_sl_data60
-00:193a _print_sl_out60
-00:194b _print_sl_data61
-00:1958 _print_sl_out61
-00:195e fetch_test_data
-00:1978 print_got
-00:198a _print_zero
-00:198e _print_one
-00:1990 _print_bit
-00:1999 _skip
-00:199a _next
-00:c000 test_addr
-00:c002 test_got
-00:c003 test_reg
-00:c004 test_mask
-00:c005 test_str_write
-00:c00e test_str_expect
+00:1834 _finish_153@quit_inline_1
+00:1845 run_testcase
+00:1863 run_testcase@quit_inline_2
+00:18e6 fetch_test_data
+00:1900 print_got
+00:1912 _print_zero
+00:1916 _print_one
+00:1918 _print_bit
+00:1921 _skip
+00:1922 _next
+00:ff80 test_addr
+00:ff82 test_got
+00:ff83 test_reg
+00:ff84 test_mask
+00:ff85 test_str_write
+00:ff8e test_str_expect
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_test_addr
+00000001 _sizeof_test_got
+00000001 _sizeof_test_reg
+00000001 _sizeof_test_mask
+00000009 _sizeof_test_str_write
+00000009 _sizeof_test_str_expect
+00000011 _sizeof_main
+00000016 _sizeof__test_data_0
+00000010 _sizeof__finish_0
+00000016 _sizeof__test_data_1
+00000010 _sizeof__finish_1
+00000016 _sizeof__test_data_2
+00000010 _sizeof__finish_2
+00000016 _sizeof__test_data_3
+00000010 _sizeof__finish_3
+00000016 _sizeof__test_data_4
+00000010 _sizeof__finish_4
+00000016 _sizeof__test_data_5
+00000010 _sizeof__finish_5
+00000016 _sizeof__test_data_6
+00000010 _sizeof__finish_6
+00000016 _sizeof__test_data_7
+00000010 _sizeof__finish_7
+00000016 _sizeof__test_data_8
+00000010 _sizeof__finish_8
+00000016 _sizeof__test_data_9
+00000010 _sizeof__finish_9
+00000016 _sizeof__test_data_10
+00000010 _sizeof__finish_10
+00000016 _sizeof__test_data_11
+00000010 _sizeof__finish_11
+00000016 _sizeof__test_data_12
+00000010 _sizeof__finish_12
+00000016 _sizeof__test_data_13
+00000010 _sizeof__finish_13
+00000016 _sizeof__test_data_14
+00000010 _sizeof__finish_14
+00000016 _sizeof__test_data_15
+00000010 _sizeof__finish_15
+00000016 _sizeof__test_data_16
+00000010 _sizeof__finish_16
+00000016 _sizeof__test_data_17
+00000010 _sizeof__finish_17
+00000016 _sizeof__test_data_18
+00000010 _sizeof__finish_18
+00000016 _sizeof__test_data_19
+00000010 _sizeof__finish_19
+00000016 _sizeof__test_data_20
+00000010 _sizeof__finish_20
+00000016 _sizeof__test_data_21
+00000010 _sizeof__finish_21
+00000016 _sizeof__test_data_22
+00000010 _sizeof__finish_22
+00000016 _sizeof__test_data_23
+00000010 _sizeof__finish_23
+00000016 _sizeof__test_data_24
+00000010 _sizeof__finish_24
+00000016 _sizeof__test_data_25
+00000010 _sizeof__finish_25
+00000016 _sizeof__test_data_26
+00000010 _sizeof__finish_26
+00000016 _sizeof__test_data_27
+00000010 _sizeof__finish_27
+00000016 _sizeof__test_data_28
+00000010 _sizeof__finish_28
+00000016 _sizeof__test_data_29
+00000010 _sizeof__finish_29
+00000016 _sizeof__test_data_30
+00000010 _sizeof__finish_30
+00000016 _sizeof__test_data_31
+00000010 _sizeof__finish_31
+00000016 _sizeof__test_data_32
+00000010 _sizeof__finish_32
+00000016 _sizeof__test_data_33
+00000010 _sizeof__finish_33
+00000016 _sizeof__test_data_34
+00000010 _sizeof__finish_34
+00000016 _sizeof__test_data_35
+00000010 _sizeof__finish_35
+00000016 _sizeof__test_data_36
+00000010 _sizeof__finish_36
+00000016 _sizeof__test_data_37
+00000010 _sizeof__finish_37
+00000016 _sizeof__test_data_38
+00000010 _sizeof__finish_38
+00000016 _sizeof__test_data_39
+00000010 _sizeof__finish_39
+00000016 _sizeof__test_data_40
+00000010 _sizeof__finish_40
+00000016 _sizeof__test_data_41
+00000010 _sizeof__finish_41
+00000016 _sizeof__test_data_42
+00000010 _sizeof__finish_42
+00000016 _sizeof__test_data_43
+00000010 _sizeof__finish_43
+00000016 _sizeof__test_data_44
+00000010 _sizeof__finish_44
+00000016 _sizeof__test_data_45
+00000010 _sizeof__finish_45
+00000016 _sizeof__test_data_46
+00000010 _sizeof__finish_46
+00000016 _sizeof__test_data_47
+00000010 _sizeof__finish_47
+00000016 _sizeof__test_data_48
+00000010 _sizeof__finish_48
+00000016 _sizeof__test_data_49
+00000010 _sizeof__finish_49
+00000016 _sizeof__test_data_50
+00000010 _sizeof__finish_50
+00000016 _sizeof__test_data_51
+00000010 _sizeof__finish_51
+00000016 _sizeof__test_data_52
+00000010 _sizeof__finish_52
+00000016 _sizeof__test_data_53
+00000010 _sizeof__finish_53
+00000016 _sizeof__test_data_54
+00000010 _sizeof__finish_54
+00000016 _sizeof__test_data_55
+00000010 _sizeof__finish_55
+00000016 _sizeof__test_data_56
+00000010 _sizeof__finish_56
+00000016 _sizeof__test_data_57
+00000010 _sizeof__finish_57
+00000016 _sizeof__test_data_58
+00000010 _sizeof__finish_58
+00000016 _sizeof__test_data_59
+00000010 _sizeof__finish_59
+00000016 _sizeof__test_data_60
+00000010 _sizeof__finish_60
+00000016 _sizeof__test_data_61
+00000010 _sizeof__finish_61
+00000016 _sizeof__test_data_62
+00000010 _sizeof__finish_62
+00000016 _sizeof__test_data_63
+00000010 _sizeof__finish_63
+00000016 _sizeof__test_data_64
+00000010 _sizeof__finish_64
+00000016 _sizeof__test_data_65
+00000010 _sizeof__finish_65
+00000016 _sizeof__test_data_66
+00000010 _sizeof__finish_66
+00000016 _sizeof__test_data_67
+00000010 _sizeof__finish_67
+00000016 _sizeof__test_data_68
+00000010 _sizeof__finish_68
+00000016 _sizeof__test_data_69
+00000010 _sizeof__finish_69
+00000016 _sizeof__test_data_70
+00000010 _sizeof__finish_70
+00000016 _sizeof__test_data_71
+00000010 _sizeof__finish_71
+00000016 _sizeof__test_data_72
+00000010 _sizeof__finish_72
+00000016 _sizeof__test_data_73
+00000010 _sizeof__finish_73
+00000016 _sizeof__test_data_74
+00000010 _sizeof__finish_74
+00000016 _sizeof__test_data_75
+00000010 _sizeof__finish_75
+00000016 _sizeof__test_data_76
+00000010 _sizeof__finish_76
+00000016 _sizeof__test_data_77
+00000010 _sizeof__finish_77
+00000016 _sizeof__test_data_78
+00000010 _sizeof__finish_78
+00000016 _sizeof__test_data_79
+00000010 _sizeof__finish_79
+00000016 _sizeof__test_data_80
+00000010 _sizeof__finish_80
+00000016 _sizeof__test_data_81
+00000010 _sizeof__finish_81
+00000016 _sizeof__test_data_82
+00000010 _sizeof__finish_82
+00000016 _sizeof__test_data_83
+00000010 _sizeof__finish_83
+00000016 _sizeof__test_data_84
+00000010 _sizeof__finish_84
+00000016 _sizeof__test_data_85
+00000010 _sizeof__finish_85
+00000016 _sizeof__test_data_86
+00000010 _sizeof__finish_86
+00000016 _sizeof__test_data_87
+00000010 _sizeof__finish_87
+00000016 _sizeof__test_data_88
+00000010 _sizeof__finish_88
+00000016 _sizeof__test_data_89
+00000010 _sizeof__finish_89
+00000016 _sizeof__test_data_90
+00000010 _sizeof__finish_90
+00000016 _sizeof__test_data_91
+00000010 _sizeof__finish_91
+00000016 _sizeof__test_data_92
+00000010 _sizeof__finish_92
+00000016 _sizeof__test_data_93
+00000010 _sizeof__finish_93
+00000016 _sizeof__test_data_94
+00000010 _sizeof__finish_94
+00000016 _sizeof__test_data_95
+00000010 _sizeof__finish_95
+00000016 _sizeof__test_data_96
+00000010 _sizeof__finish_96
+00000016 _sizeof__test_data_97
+00000010 _sizeof__finish_97
+00000016 _sizeof__test_data_98
+00000010 _sizeof__finish_98
+00000016 _sizeof__test_data_99
+00000010 _sizeof__finish_99
+00000016 _sizeof__test_data_100
+00000010 _sizeof__finish_100
+00000016 _sizeof__test_data_101
+00000010 _sizeof__finish_101
+00000016 _sizeof__test_data_102
+00000010 _sizeof__finish_102
+00000016 _sizeof__test_data_103
+00000010 _sizeof__finish_103
+00000016 _sizeof__test_data_104
+00000010 _sizeof__finish_104
+00000016 _sizeof__test_data_105
+00000010 _sizeof__finish_105
+00000016 _sizeof__test_data_106
+00000010 _sizeof__finish_106
+00000016 _sizeof__test_data_107
+00000010 _sizeof__finish_107
+00000016 _sizeof__test_data_108
+00000010 _sizeof__finish_108
+00000016 _sizeof__test_data_109
+00000010 _sizeof__finish_109
+00000016 _sizeof__test_data_110
+00000010 _sizeof__finish_110
+00000016 _sizeof__test_data_111
+00000010 _sizeof__finish_111
+00000016 _sizeof__test_data_112
+00000010 _sizeof__finish_112
+00000016 _sizeof__test_data_113
+00000010 _sizeof__finish_113
+00000016 _sizeof__test_data_114
+00000010 _sizeof__finish_114
+00000016 _sizeof__test_data_115
+00000010 _sizeof__finish_115
+00000016 _sizeof__test_data_116
+00000010 _sizeof__finish_116
+00000016 _sizeof__test_data_117
+00000010 _sizeof__finish_117
+00000016 _sizeof__test_data_118
+00000010 _sizeof__finish_118
+00000016 _sizeof__test_data_119
+00000010 _sizeof__finish_119
+00000016 _sizeof__test_data_120
+00000010 _sizeof__finish_120
+00000016 _sizeof__test_data_121
+00000010 _sizeof__finish_121
+00000016 _sizeof__test_data_122
+00000010 _sizeof__finish_122
+00000016 _sizeof__test_data_123
+00000010 _sizeof__finish_123
+00000016 _sizeof__test_data_124
+00000010 _sizeof__finish_124
+00000016 _sizeof__test_data_125
+00000010 _sizeof__finish_125
+00000016 _sizeof__test_data_126
+00000010 _sizeof__finish_126
+00000016 _sizeof__test_data_127
+00000010 _sizeof__finish_127
+00000016 _sizeof__test_data_128
+00000010 _sizeof__finish_128
+00000016 _sizeof__test_data_129
+00000010 _sizeof__finish_129
+00000016 _sizeof__test_data_130
+00000010 _sizeof__finish_130
+00000016 _sizeof__test_data_131
+00000010 _sizeof__finish_131
+00000016 _sizeof__test_data_132
+00000010 _sizeof__finish_132
+00000016 _sizeof__test_data_133
+00000010 _sizeof__finish_133
+00000016 _sizeof__test_data_134
+00000010 _sizeof__finish_134
+00000016 _sizeof__test_data_135
+00000010 _sizeof__finish_135
+00000016 _sizeof__test_data_136
+00000010 _sizeof__finish_136
+00000016 _sizeof__test_data_137
+00000010 _sizeof__finish_137
+00000016 _sizeof__test_data_138
+00000010 _sizeof__finish_138
+00000016 _sizeof__test_data_139
+00000010 _sizeof__finish_139
+00000016 _sizeof__test_data_140
+00000010 _sizeof__finish_140
+00000016 _sizeof__test_data_141
+00000010 _sizeof__finish_141
+00000016 _sizeof__test_data_142
+00000010 _sizeof__finish_142
+00000016 _sizeof__test_data_143
+00000010 _sizeof__finish_143
+00000016 _sizeof__test_data_144
+00000010 _sizeof__finish_144
+00000016 _sizeof__test_data_145
+00000010 _sizeof__finish_145
+00000016 _sizeof__test_data_146
+00000010 _sizeof__finish_146
+00000016 _sizeof__test_data_147
+00000010 _sizeof__finish_147
+00000016 _sizeof__test_data_148
+00000010 _sizeof__finish_148
+00000016 _sizeof__test_data_149
+00000010 _sizeof__finish_149
+00000016 _sizeof__test_data_150
+00000010 _sizeof__finish_150
+00000016 _sizeof__test_data_151
+00000010 _sizeof__finish_151
+00000016 _sizeof__test_data_152
+00000010 _sizeof__finish_152
+00000016 _sizeof__test_data_153
+00000018 _sizeof__finish_153
+000000a1 _sizeof_run_testcase
+0000001a _sizeof_fetch_test_data
+00000012 _sizeof_print_got
+00000004 _sizeof__print_zero
+00000002 _sizeof__print_one
+00000009 _sizeof__print_bit
+00000001 _sizeof__skip

cinema/gb/mooneye-gb/acceptance/boot_div-S/manifest.yml

@@ -0,0 +1,3 @@
+config:
+  gb.model: SGB
+fail: true

cinema/gb/mooneye-gb/acceptance/boot_div-S/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-S.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmg0.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmgABCmgb.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

cinema/gb/mooneye-gb/acceptance/boot_div2-S/manifest.yml

@@ -0,0 +1,3 @@
+config:
+  gb.model: SGB
+fail: true

cinema/gb/mooneye-gb/acceptance/boot_div2-S/test.sym

@@ -0,0 +1,120 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div2-S.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h

cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml

@@ -1 +1,2 @@
-config: {gb.model: SGB}
+config:
+  gb.model: SGB

cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.sym

@@ -1,212 +1,57 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/test.sym

@@ -1,212 +1,57 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmg0.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmg0.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.sym

@@ -1,212 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCXmgb.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_ok_cb_0
-00:020d _print_sl_data55
-00:0215 _print_sl_out55
-00:0218 mismatch
-00:023b _wait_ly_6
-00:0241 _wait_ly_7
-00:0257 _print_results_halt_2
-00:025a mismatch_cb
-00:0262 _print_sl_data56
-00:0270 _print_sl_out56
-00:028a _print_sl_data57
-00:0294 _print_sl_out57
-00:02a5 _print_sl_data58
-00:02af _print_sl_out58
-00:02b8 hwio_data
-00:c014 mismatch_addr
-00:c016 mismatch_data
-00:c017 mismatch_mem

cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym

@@ -0,0 +1,57 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCmgb.gb".
+
+[labels]
+01:48bb clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48cf memcpy
+01:48d8 memset
+01:4898 print_hex4
+01:48c5 print_hex8
+01:48e8 print_inline_string
+01:48a4 print_load_font
+01:48b0 print_newline
+01:48e1 print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
+01:4000 font
+00:0150 main
+00:01d9 main@quit_inline_1
+00:01ea mismatch
+00:0200 mismatch@quit_inline_2
+00:024f hwio_data
+00:ff80 mismatch_addr
+00:ff82 mismatch_data
+00:ff83 mismatch_mem
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000002 _sizeof_mismatch_addr
+00000001 _sizeof_mismatch_data
+00000001 _sizeof_mismatch_mem
+0000009a _sizeof_main
+00000065 _sizeof_mismatch

cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/test.sym

@@ -1,198 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg.gb".
-
-[labels]
-0001:4bf2 print_load_font
-0001:4bff print_string
-0001:4c09 print_a
-0001:4c13 print_newline
-0001:4c1e print_digit
-0001:4c2b print_regs
-0001:4c34 _print_sl_data0
-0001:4c3a _print_sl_out0
-0001:4c47 _print_sl_data1
-0001:4c4d _print_sl_out1
-0001:4c5f _print_sl_data2
-0001:4c65 _print_sl_out2
-0001:4c72 _print_sl_data3
-0001:4c78 _print_sl_out3
-0001:4c8a _print_sl_data4
-0001:4c90 _print_sl_out4
-0001:4c9d _print_sl_data5
-0001:4ca3 _print_sl_out5
-0001:4cb5 _print_sl_data6
-0001:4cbb _print_sl_out6
-0001:4cc8 _print_sl_data7
-0001:4cce _print_sl_out7
-0001:4000 font
-0000:c000 regs_save
-0000:c000 regs_save.f
-0000:c001 regs_save.a
-0000:c002 regs_save.c
-0000:c003 regs_save.b
-0000:c004 regs_save.e
-0000:c005 regs_save.d
-0000:c006 regs_save.l
-0000:c007 regs_save.h
-0000:c008 regs_flags
-0000:c009 regs_assert
-0000:c009 regs_assert.f
-0000:c00a regs_assert.a
-0000:c00b regs_assert.c
-0000:c00c regs_assert.b
-0000:c00d regs_assert.e
-0000:c00e regs_assert.d
-0000:c00f regs_assert.l
-0000:c010 regs_assert.h
-0000:c011 memdump_len
-0000:c012 memdump_addr
-0001:47f0 memcpy
-0001:47f9 memset
-0001:4802 clear_vram
-0001:480d reset_screen
-0001:481a process_results
-0001:481f _wait_ly_0
-0001:4825 _wait_ly_1
-0001:4841 _wait_ly_2
-0001:4847 _wait_ly_3
-0001:4860 _process_results_cb
-0001:486b _print_sl_data8
-0001:4875 _print_sl_out8
-0001:488f _print_sl_data9
-0001:489a _print_sl_out9
-0001:48b2 _print_sl_data10
-0001:48be _print_sl_out10
-0001:48bf dump_mem
-0001:48cf _wait_ly_4
-0001:48d5 _wait_ly_5
-0001:48f1 _dump_mem_line
-0001:491b _check_asserts
-0001:4929 _print_sl_data11
-0001:492c _print_sl_out11
-0001:4938 _print_sl_data12
-0001:493a _print_sl_out12
-0001:4942 _print_sl_data13
-0001:4945 _print_sl_out13
-0001:494f __check_assert_fail0
-0001:495a _print_sl_data14
-0001:495d _print_sl_out14
-0001:4960 __check_assert_ok0
-0001:4968 _print_sl_data15
-0001:496d _print_sl_out15
-0001:496f __check_assert_skip0
-0001:4977 _print_sl_data16
-0001:497f _print_sl_out16
-0001:497f __check_assert_out0
-0001:498b _print_sl_data17
-0001:498d _print_sl_out17
-0001:4995 _print_sl_data18
-0001:4998 _print_sl_out18
-0001:49a2 __check_assert_fail1
-0001:49ad _print_sl_data19
-0001:49b0 _print_sl_out19
-0001:49b3 __check_assert_ok1
-0001:49bb _print_sl_data20
-0001:49c0 _print_sl_out20
-0001:49c2 __check_assert_skip1
-0001:49ca _print_sl_data21
-0001:49d2 _print_sl_out21
-0001:49d2 __check_assert_out1
-0001:49dd _print_sl_data22
-0001:49e0 _print_sl_out22
-0001:49ec _print_sl_data23
-0001:49ee _print_sl_out23
-0001:49f6 _print_sl_data24
-0001:49f9 _print_sl_out24
-0001:4a03 __check_assert_fail2
-0001:4a0e _print_sl_data25
-0001:4a11 _print_sl_out25
-0001:4a14 __check_assert_ok2
-0001:4a1c _print_sl_data26
-0001:4a21 _print_sl_out26
-0001:4a23 __check_assert_skip2
-0001:4a2b _print_sl_data27
-0001:4a33 _print_sl_out27
-0001:4a33 __check_assert_out2
-0001:4a3f _print_sl_data28
-0001:4a41 _print_sl_out28
-0001:4a49 _print_sl_data29
-0001:4a4c _print_sl_out29
-0001:4a56 __check_assert_fail3
-0001:4a61 _print_sl_data30
-0001:4a64 _print_sl_out30
-0001:4a67 __check_assert_ok3
-0001:4a6f _print_sl_data31
-0001:4a74 _print_sl_out31
-0001:4a76 __check_assert_skip3
-0001:4a7e _print_sl_data32
-0001:4a86 _print_sl_out32
-0001:4a86 __check_assert_out3
-0001:4a91 _print_sl_data33
-0001:4a94 _print_sl_out33
-0001:4aa0 _print_sl_data34
-0001:4aa2 _print_sl_out34
-0001:4aaa _print_sl_data35
-0001:4aad _print_sl_out35
-0001:4ab7 __check_assert_fail4
-0001:4ac2 _print_sl_data36
-0001:4ac5 _print_sl_out36
-0001:4ac8 __check_assert_ok4
-0001:4ad0 _print_sl_data37
-0001:4ad5 _print_sl_out37
-0001:4ad7 __check_assert_skip4
-0001:4adf _print_sl_data38
-0001:4ae7 _print_sl_out38
-0001:4ae7 __check_assert_out4
-0001:4af3 _print_sl_data39
-0001:4af5 _print_sl_out39
-0001:4afd _print_sl_data40
-0001:4b00 _print_sl_out40
-0001:4b0a __check_assert_fail5
-0001:4b15 _print_sl_data41
-0001:4b18 _print_sl_out41
-0001:4b1b __check_assert_ok5
-0001:4b23 _print_sl_data42
-0001:4b28 _print_sl_out42
-0001:4b2a __check_assert_skip5
-0001:4b32 _print_sl_data43
-0001:4b3a _print_sl_out43
-0001:4b3a __check_assert_out5
-0001:4b45 _print_sl_data44
-0001:4b48 _print_sl_out44
-0001:4b54 _print_sl_data45
-0001:4b56 _print_sl_out45
-0001:4b5e _print_sl_data46
-0001:4b61 _print_sl_out46
-0001:4b6b __check_assert_fail6
-0001:4b76 _print_sl_data47
-0001:4b79 _print_sl_out47
-0001:4b7c __check_assert_ok6
-0001:4b84 _print_sl_data48
-0001:4b89 _print_sl_out48
-0001:4b8b __check_assert_skip6
-0001:4b93 _print_sl_data49
-0001:4b9b _print_sl_out49
-0001:4b9b __check_assert_out6
-0001:4ba7 _print_sl_data50
-0001:4ba9 _print_sl_out50
-0001:4bb1 _print_sl_data51
-0001:4bb4 _print_sl_out51
-0001:4bbe __check_assert_fail7
-0001:4bc9 _print_sl_data52
-0001:4bcc _print_sl_out52
-0001:4bcf __check_assert_ok7
-0001:4bd7 _print_sl_data53
-0001:4bdc _print_sl_out53
-0001:4bde __check_assert_skip7
-0001:4be6 _print_sl_data54
-0001:4bee _print_sl_out54
-0001:4bee __check_assert_out7
-0000:01d2 invalid_sp
-0000:01d7 _wait_ly_6
-0000:01dd _wait_ly_7
-0000:01f9 _wait_ly_8
-0000:01ff _wait_ly_9
-0000:0218 _test_failure_cb_0
-0000:0220 _print_sl_data55
-0000:0231 _print_sl_out55
-0000:c014 sp_save

cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym

@@ -0,0 +1,125 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABC.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/test.sym

@@ -1,199 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABCX.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save

cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/manifest.yml

@@ -1 +1,2 @@
-config: {gb.model: MGB}
+config:
+  gb.model: MGB

cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/manifest.yml

@@ -1 +1,2 @@
-config: {gb.model: SGB}
+config:
+  gb.model: SGB

cinema/gb/mooneye-gb/acceptance/boot_regs-sgb/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/manifest.yml

@@ -1 +1,2 @@
-config: {gb.model: SGB2}
+config:
+  gb.model: SGB2

cinema/gb/mooneye-gb/acceptance/boot_regs-sgb2/test.sym

@@ -1,199 +1,125 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-sgb2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:01d2 invalid_sp
-00:01e6 _wait_ly_4
-00:01ec _wait_ly_5
-00:0202 _print_results_halt_1
-00:0205 _test_failure_cb_0
-00:020d _print_sl_data55
-00:021e _print_sl_out55
-00:c014 sp_save
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01d3 invalid_sp
+00:01da invalid_sp@quit_inline_1
+00:ff91 sp_save
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000002 _sizeof_sp_save
+00000083 _sizeof_main

cinema/gb/mooneye-gb/acceptance/call_cc_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym

@@ -1,204 +1,138 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01cf hiram_test
-00:01d2 _wait_ly_6
-00:01d8 _wait_ly_7
-00:01ec finish_round1
-00:01ed _wait_ly_8
-00:01f3 _wait_ly_9
-00:0208 finish_round2
-00:0209 _wait_ly_10
-00:020f _wait_ly_11
-00:0225 finish_round3
+00:01d2 hiram_test
+00:01d5 hiram_test@wait_ly_7
+00:01db hiram_test@wait_ly_8
+00:01ef finish_round1
+00:01f0 finish_round1@wait_ly_9
+00:01f6 finish_round1@wait_ly_10
+00:020b finish_round2
+00:020c finish_round2@wait_ly_11
+00:0212 finish_round2@wait_ly_12
+00:0228 finish_round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+0000005b _sizeof_test_finish
+0000001d _sizeof_hiram_test
+0000001c _sizeof_finish_round1
+0000001d _sizeof_finish_round2

cinema/gb/mooneye-gb/acceptance/call_timing/test.sym

@@ -1,223 +1,66 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0184 test_finish
-00:0198 _wait_ly_6
-00:019e _wait_ly_7
-00:01b4 _print_results_halt_1
-00:01b7 _test_ok_cb_0
-00:01bf _print_sl_data55
-00:01c7 _print_sl_out55
-00:01ca wram_test
-00:01cd fail_round1
-00:01e1 _wait_ly_8
-00:01e7 _wait_ly_9
-00:01fd _print_results_halt_2
-00:0200 _test_failure_cb_0
-00:0208 _print_sl_data56
-00:0216 _print_sl_out56
-00:0219 fail_round2
-00:022d _wait_ly_10
-00:0233 _wait_ly_11
-00:0249 _print_results_halt_3
-00:024c _test_failure_cb_1
-00:0254 _print_sl_data57
-00:0262 _print_sl_out57
+00:018b test_finish@quit_inline_1
+00:019c wram_test
+00:019f fail_round1
+00:01a6 fail_round1@quit_inline_2
+00:01bd fail_round2
+00:01c4 fail_round2@quit_inline_3
 00:1f80 hiram_test
-00:1f87 _wait_ly_12
-00:1f8d _wait_ly_13
+00:1f87 hiram_test@wait_ly_7
+00:1f8d hiram_test@wait_ly_8
 00:1fa1 test_round2
-00:1fa8 _wait_ly_14
-00:1fae _wait_ly_15
+00:1fa8 test_round2@wait_ly_9
+00:1fae test_round2@wait_ly_10
 00:1fca finish_round1
 00:1ada finish_round2
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000034 _sizeof_main
+00000018 _sizeof_test_finish
+00000003 _sizeof_wram_test
+0000001e _sizeof_fail_round1
+0000191d _sizeof_fail_round2
+000004a6 _sizeof_finish_round2
+00000021 _sizeof_hiram_test
+00000029 _sizeof_test_round2

cinema/gb/mooneye-gb/acceptance/call_timing2/test.sym

@@ -1,204 +1,138 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing2.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing2.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:0151 main@wait_ly_5
+00:0157 main@wait_ly_6
 00:0177 test_finish
-00:01cf hiram_test
-00:01d2 _wait_ly_6
-00:01d8 _wait_ly_7
-00:01ec finish_round1
-00:01ed _wait_ly_8
-00:01f3 _wait_ly_9
-00:0208 finish_round2
-00:0209 _wait_ly_10
-00:020f _wait_ly_11
-00:0225 finish_round3
+00:01d2 hiram_test
+00:01d5 hiram_test@wait_ly_7
+00:01db hiram_test@wait_ly_8
+00:01ef finish_round1
+00:01f0 finish_round1@wait_ly_9
+00:01f6 finish_round1@wait_ly_10
+00:020b finish_round2
+00:020c finish_round2@wait_ly_11
+00:0212 finish_round2@wait_ly_12
+00:0228 finish_round3
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000027 _sizeof_main
+0000005b _sizeof_test_finish
+0000001d _sizeof_hiram_test
+0000001c _sizeof_finish_round1
+0000001d _sizeof_finish_round2

cinema/gb/mooneye-gb/acceptance/di_timing-GS/test.sym

@@ -1,228 +1,67 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/di_timing-GS.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/di_timing-GS.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:48af clear_vram
+01:487a disable_lcd_safe
+01:4880 disable_lcd_safe@wait_ly_0
+01:48b9 memcpy
+01:48c2 memset
+01:48d2 print_inline_string
+01:4898 print_load_font
+01:48a4 print_newline
+01:48cb print_string
+01:47f0 quit
+01:4805 quit@cb_return
+01:480a quit@wait_ly_1
+01:4810 quit@wait_ly_2
+01:4816 quit@wait_ly_3
+01:481c quit@wait_ly_4
+01:4826 quit@success
+01:484d quit@failure
+01:4862 quit@halt
+01:4863 quit@halt_execution_0
+01:4866 reset_screen
+01:4889 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0158 _wait_ly_4
-00:015e _wait_ly_5
+00:0150 main
+00:0158 main@wait_ly_5
+00:015e main@wait_ly_6
 00:016d test_round1
 00:0177 _delay_long_time_0
 00:0186 finish_round1
-00:0189 _wait_ly_6
-00:018f _wait_ly_7
+00:0189 finish_round1@wait_ly_7
+00:018f finish_round1@wait_ly_8
 00:019e test_round2
 00:01a8 _delay_long_time_1
 00:01b4 test_finish
-00:01c8 _wait_ly_8
-00:01ce _wait_ly_9
-00:01e4 _print_results_halt_1
-00:01e7 _test_ok_cb_0
-00:01ef _print_sl_data55
-00:01f7 _print_sl_out55
-00:01fa fail_halt
-00:020e _wait_ly_10
-00:0214 _wait_ly_11
-00:022a _print_results_halt_2
-00:022d _test_failure_cb_0
-00:0235 _print_sl_data56
-00:0240 _print_sl_out56
-00:0243 fail_round1
-00:0257 _wait_ly_12
-00:025d _wait_ly_13
-00:0273 _print_results_halt_3
-00:0276 _test_failure_cb_1
-00:027e _print_sl_data57
-00:028c _print_sl_out57
-00:028f fail_round2
-00:02a3 _wait_ly_14
-00:02a9 _wait_ly_15
-00:02bf _print_results_halt_4
-00:02c2 _test_failure_cb_2
-00:02ca _print_sl_data58
-00:02d8 _print_sl_out58
+00:01bb test_finish@quit_inline_1
+00:01cc fail_halt
+00:01d3 fail_halt@quit_inline_2
+00:01e7 fail_round1
+00:01ee fail_round1@quit_inline_3
+00:0205 fail_round2
+00:020c fail_round2@quit_inline_4
+
+[definitions]
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+0000001d _sizeof_main
+0000000a _sizeof_test_round1
+0000000f _sizeof__delay_long_time_0
+00000018 _sizeof_finish_round1
+0000000a _sizeof_test_round2
+0000000c _sizeof__delay_long_time_1
+00000018 _sizeof_test_finish
+0000001b _sizeof_fail_halt
+0000001e _sizeof_fail_round1

cinema/gb/mooneye-gb/acceptance/div_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/div_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/div_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0232 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+000000e2 _sizeof_main

cinema/gb/mooneye-gb/acceptance/ei_sequence/test.sym

@@ -0,0 +1,127 @@
+; this file was created with wlalink by ville helin <vhelin@iki.fi>.
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_sequence.gb".
+
+[labels]
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
+01:4000 font
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
+00:01a0 test
+00:01b2 fail
+00:01b9 fail@quit_inline_1
+00:01d0 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000050 _sizeof_main
+00000012 _sizeof_test
+0000001e _sizeof_fail

cinema/gb/mooneye-gb/acceptance/ei_timing/test.sym

@@ -1,192 +1,122 @@
 ; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb".
+; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb".
 
 [labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
+01:47f0 check_asserts_cb
+01:4842 check_asserts_cb@check_asserts
+01:4864 check_asserts_cb@fail0
+01:4870 check_asserts_cb@ok0
+01:487a check_asserts_cb@skip0
+01:4885 check_asserts_cb@out0
+01:489c check_asserts_cb@fail1
+01:48a8 check_asserts_cb@ok1
+01:48b2 check_asserts_cb@skip1
+01:48bd check_asserts_cb@out1
+01:48dd check_asserts_cb@fail2
+01:48e9 check_asserts_cb@ok2
+01:48f3 check_asserts_cb@skip2
+01:48fe check_asserts_cb@out2
+01:4915 check_asserts_cb@fail3
+01:4921 check_asserts_cb@ok3
+01:492b check_asserts_cb@skip3
+01:4936 check_asserts_cb@out3
+01:4956 check_asserts_cb@fail4
+01:4962 check_asserts_cb@ok4
+01:496c check_asserts_cb@skip4
+01:4977 check_asserts_cb@out4
+01:498e check_asserts_cb@fail5
+01:499a check_asserts_cb@ok5
+01:49a4 check_asserts_cb@skip5
+01:49af check_asserts_cb@out5
+01:49cf check_asserts_cb@fail6
+01:49db check_asserts_cb@ok6
+01:49e5 check_asserts_cb@skip6
+01:49f0 check_asserts_cb@out6
+01:4a07 check_asserts_cb@fail7
+01:4a13 check_asserts_cb@ok7
+01:4a1d check_asserts_cb@skip7
+01:4a28 check_asserts_cb@out7
+01:4b7b clear_vram
+01:4b3a disable_lcd_safe
+01:4b40 disable_lcd_safe@wait_ly_0
+01:4b8f memcpy
+01:4b98 memset
+01:4b58 print_hex4
+01:4b85 print_hex8
+01:4ba8 print_inline_string
+01:4b64 print_load_font
+01:4b70 print_newline
+01:4a2b print_reg_dump
+01:4ba1 print_string
+01:4ab0 quit
+01:4ac5 quit@cb_return
+01:4aca quit@wait_ly_1
+01:4ad0 quit@wait_ly_2
+01:4ad6 quit@wait_ly_3
+01:4adc quit@wait_ly_4
+01:4ae6 quit@success
+01:4b0d quit@failure
+01:4b22 quit@halt
+01:4b23 quit@halt_execution_0
+01:4b26 reset_screen
+01:4b49 serial_send_byte
 01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
+00:ff80 v_regs_save
+00:ff80 v_regs_save.reg_f
+00:ff81 v_regs_save.reg_a
+00:ff82 v_regs_save.reg_c
+00:ff83 v_regs_save.reg_b
+00:ff84 v_regs_save.reg_e
+00:ff85 v_regs_save.reg_d
+00:ff86 v_regs_save.reg_l
+00:ff87 v_regs_save.reg_h
+00:ff88 v_regs_flags
+00:ff89 v_regs_assert
+00:ff89 v_regs_assert.reg_f
+00:ff8a v_regs_assert.reg_a
+00:ff8b v_regs_assert.reg_c
+00:ff8c v_regs_assert.reg_b
+00:ff8d v_regs_assert.reg_e
+00:ff8e v_regs_assert.reg_d
+00:ff8f v_regs_assert.reg_l
+00:ff90 v_regs_assert.reg_h
+00:0150 main
 00:0160 test_finish
+
+[definitions]
+0000023b _sizeof_check_asserts_cb
+0000000a _sizeof_clear_vram
+0000000f _sizeof_disable_lcd_safe
+00000009 _sizeof_memcpy
+00000009 _sizeof_memset
+0000000c _sizeof_print_hex4
+0000000a _sizeof_print_hex8
+00000006 _sizeof_print_inline_string
+0000000c _sizeof_print_load_font
+0000000b _sizeof_print_newline
+00000085 _sizeof_print_reg_dump
+00000007 _sizeof_print_string
+00000076 _sizeof_quit
+00000014 _sizeof_reset_screen
+0000000f _sizeof_serial_send_byte
+000007f0 _sizeof_font
+00000008 _sizeof_v_regs_save
+00000001 _sizeof_v_regs_save.reg_f
+00000001 _sizeof_v_regs_save.reg_a
+00000001 _sizeof_v_regs_save.reg_c
+00000001 _sizeof_v_regs_save.reg_b
+00000001 _sizeof_v_regs_save.reg_e
+00000001 _sizeof_v_regs_save.reg_d
+00000001 _sizeof_v_regs_save.reg_l
+00000001 _sizeof_v_regs_save.reg_h
+00000001 _sizeof_v_regs_flags
+00000008 _sizeof_v_regs_assert
+00000001 _sizeof_v_regs_assert.reg_f
+00000001 _sizeof_v_regs_assert.reg_a
+00000001 _sizeof_v_regs_assert.reg_c
+00000001 _sizeof_v_regs_assert.reg_b
+00000001 _sizeof_v_regs_assert.reg_e
+00000001 _sizeof_v_regs_assert.reg_d
+00000001 _sizeof_v_regs_assert.reg_l
+00000001 _sizeof_v_regs_assert.reg_h
+00000010 _sizeof_main

cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/test.sym

@@ -1,219 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/hblank_ly_scx_timing-GS.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:03a2 _wait_ly_6
-00:03a8 _wait_ly_7
-00:03be _print_results_halt_1
-00:03c1 _test_ok_cb_0
-00:03c9 _print_sl_data55
-00:03d1 _print_sl_out55
-00:03d4 test_fail
-00:0404 _wait_ly_8
-00:040a _wait_ly_9
-00:0420 _print_results_halt_2
-00:0423 _test_failure_dump_cb_0
-00:042e _print_sl_data56
-00:0438 _print_sl_out56
-00:044c _print_sl_data57
-00:0458 _print_sl_out57
-00:045b standard_delay
-00:0473 setup_and_wait
-00:0473 _wait_ly_10
-00:0479 _wait_ly_11
-00:048d fail_halt
-00:04a1 _wait_ly_12
-00:04a7 _wait_ly_13
-00:04bd _print_results_halt_3
-00:04c0 _test_failure_cb_0
-00:04c8 _print_sl_data58
-00:04d3 _print_sl_out58

cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/test.sym

@@ -1,203 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_1_2_timing-GS.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:01ab setup_and_wait_mode1
-00:01ab _wait_ly_6
-00:01be setup_and_wait_mode2
-00:01cb fail_halt
-00:01df _wait_ly_7
-00:01e5 _wait_ly_8
-00:01fb _print_results_halt_1
-00:01fe _test_failure_cb_0
-00:0206 _print_sl_data55
-00:0211 _print_sl_out55

cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/test.sym

@@ -1,203 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_0_timing.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:01a9 setup_and_wait_mode2
-00:01a9 _wait_ly_6
-00:01cc setup_and_wait_mode0
-00:01d9 fail_halt
-00:01ed _wait_ly_7
-00:01f3 _wait_ly_8
-00:0209 _print_results_halt_1
-00:020c _test_failure_cb_0
-00:0214 _print_sl_data55
-00:021f _print_sl_out55

cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:0207 setup_and_wait_mode2
-00:0207 _wait_ly_6
-00:022a fail_halt
-00:023e _wait_ly_7
-00:0244 _wait_ly_8
-00:025a _print_results_halt_1
-00:025d _test_failure_cb_0
-00:0265 _print_sl_data55
-00:0270 _print_sl_out55

cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode0_timing_sprites/test.sym

@@ -1,437 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode0_timing_sprites.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c0c2 regs_save
-00:c0c2 regs_save.f
-00:c0c3 regs_save.a
-00:c0c4 regs_save.c
-00:c0c5 regs_save.b
-00:c0c6 regs_save.e
-00:c0c7 regs_save.d
-00:c0c8 regs_save.l
-00:c0c9 regs_save.h
-00:c0ca regs_flags
-00:c0cb regs_assert
-00:c0cb regs_assert.f
-00:c0cc regs_assert.a
-00:c0cd regs_assert.c
-00:c0ce regs_assert.b
-00:c0cf regs_assert.e
-00:c0d0 regs_assert.d
-00:c0d1 regs_assert.l
-00:c0d2 regs_assert.h
-00:c0d3 memdump_len
-00:c0d4 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0174 _testcase_data_0
-00:0176 _testcase_end_0
-00:0187 _testcase_data_1
-00:018a _testcase_end_1
-00:019b _testcase_data_2
-00:019f _testcase_end_2
-00:01b0 _testcase_data_3
-00:01b5 _testcase_end_3
-00:01c6 _testcase_data_4
-00:01cc _testcase_end_4
-00:01dd _testcase_data_5
-00:01e4 _testcase_end_5
-00:01f5 _testcase_data_6
-00:01fd _testcase_end_6
-00:020e _testcase_data_7
-00:0217 _testcase_end_7
-00:0228 _testcase_data_8
-00:0232 _testcase_end_8
-00:0243 _testcase_data_9
-00:024e _testcase_end_9
-00:025f _testcase_data_10
-00:026a _testcase_end_10
-00:027b _testcase_data_11
-00:0286 _testcase_end_11
-00:0297 _testcase_data_12
-00:02a2 _testcase_end_12
-00:02b3 _testcase_data_13
-00:02be _testcase_end_13
-00:02cf _testcase_data_14
-00:02da _testcase_end_14
-00:02eb _testcase_data_15
-00:02f6 _testcase_end_15
-00:0307 _testcase_data_16
-00:0312 _testcase_end_16
-00:0323 _testcase_data_17
-00:032e _testcase_end_17
-00:033f _testcase_data_18
-00:034a _testcase_end_18
-00:035b _testcase_data_19
-00:0366 _testcase_end_19
-00:0377 _testcase_data_20
-00:0382 _testcase_end_20
-00:0393 _testcase_data_21
-00:039e _testcase_end_21
-00:03af _testcase_data_22
-00:03ba _testcase_end_22
-00:03cb _testcase_data_23
-00:03d6 _testcase_end_23
-00:03e7 _testcase_data_24
-00:03f2 _testcase_end_24
-00:0403 _testcase_data_25
-00:040e _testcase_end_25
-00:041f _testcase_data_26
-00:042a _testcase_end_26
-00:043b _testcase_data_27
-00:0446 _testcase_end_27
-00:0457 _testcase_data_28
-00:0462 _testcase_end_28
-00:0473 _testcase_data_29
-00:047e _testcase_end_29
-00:048f _testcase_data_30
-00:049a _testcase_end_30
-00:04ab _testcase_data_31
-00:04b6 _testcase_end_31
-00:04c7 _testcase_data_32
-00:04d2 _testcase_end_32
-00:04e3 _testcase_data_33
-00:04ee _testcase_end_33
-00:04ff _testcase_data_34
-00:050a _testcase_end_34
-00:051b _testcase_data_35
-00:0526 _testcase_end_35
-00:0537 _testcase_data_36
-00:0542 _testcase_end_36
-00:0553 _testcase_data_37
-00:055e _testcase_end_37
-00:056f _testcase_data_38
-00:057a _testcase_end_38
-00:058b _testcase_data_39
-00:0596 _testcase_end_39
-00:05a7 _testcase_data_40
-00:05b2 _testcase_end_40
-00:05c3 _testcase_data_41
-00:05ce _testcase_end_41
-00:05df _testcase_data_42
-00:05ea _testcase_end_42
-00:05fb _testcase_data_43
-00:0606 _testcase_end_43
-00:0617 _testcase_data_44
-00:0622 _testcase_end_44
-00:0633 _testcase_data_45
-00:063e _testcase_end_45
-00:064f _testcase_data_46
-00:065a _testcase_end_46
-00:066b _testcase_data_47
-00:0676 _testcase_end_47
-00:0687 _testcase_data_48
-00:0692 _testcase_end_48
-00:06a3 _testcase_data_49
-00:06ae _testcase_end_49
-00:06bf _testcase_data_50
-00:06ca _testcase_end_50
-00:06db _testcase_data_51
-00:06e6 _testcase_end_51
-00:06f7 _testcase_data_52
-00:06f9 _testcase_end_52
-00:070a _testcase_data_53
-00:070c _testcase_end_53
-00:071d _testcase_data_54
-00:071f _testcase_end_54
-00:0730 _testcase_data_55
-00:0732 _testcase_end_55
-00:0743 _testcase_data_56
-00:0745 _testcase_end_56
-00:0756 _testcase_data_57
-00:0758 _testcase_end_57
-00:0769 _testcase_data_58
-00:076b _testcase_end_58
-00:077c _testcase_data_59
-00:077e _testcase_end_59
-00:078f _testcase_data_60
-00:0791 _testcase_end_60
-00:07a2 _testcase_data_61
-00:07a4 _testcase_end_61
-00:07b5 _testcase_data_62
-00:07b7 _testcase_end_62
-00:07c8 _testcase_data_63
-00:07ca _testcase_end_63
-00:07db _testcase_data_64
-00:07dd _testcase_end_64
-00:07ee _testcase_data_65
-00:07f0 _testcase_end_65
-00:0801 _testcase_data_66
-00:0803 _testcase_end_66
-00:0814 _testcase_data_67
-00:0816 _testcase_end_67
-00:0827 _testcase_data_68
-00:0829 _testcase_end_68
-00:083a _testcase_data_69
-00:083c _testcase_end_69
-00:084d _testcase_data_70
-00:084f _testcase_end_70
-00:0860 _testcase_data_71
-00:0862 _testcase_end_71
-00:0873 _testcase_data_72
-00:0875 _testcase_end_72
-00:0886 _testcase_data_73
-00:0888 _testcase_end_73
-00:0899 _testcase_data_74
-00:089b _testcase_end_74
-00:08ac _testcase_data_75
-00:08ae _testcase_end_75
-00:08bf _testcase_data_76
-00:08c1 _testcase_end_76
-00:08d2 _testcase_data_77
-00:08d4 _testcase_end_77
-00:08e5 _testcase_data_78
-00:08e8 _testcase_end_78
-00:08f9 _testcase_data_79
-00:08fc _testcase_end_79
-00:090d _testcase_data_80
-00:0910 _testcase_end_80
-00:0921 _testcase_data_81
-00:0924 _testcase_end_81
-00:0935 _testcase_data_82
-00:0938 _testcase_end_82
-00:0949 _testcase_data_83
-00:094c _testcase_end_83
-00:095d _testcase_data_84
-00:0960 _testcase_end_84
-00:0971 _testcase_data_85
-00:0974 _testcase_end_85
-00:0985 _testcase_data_86
-00:0988 _testcase_end_86
-00:0999 _testcase_data_87
-00:099c _testcase_end_87
-00:09ad _testcase_data_88
-00:09b0 _testcase_end_88
-00:09c1 _testcase_data_89
-00:09c4 _testcase_end_89
-00:09d5 _testcase_data_90
-00:09d8 _testcase_end_90
-00:09e9 _testcase_data_91
-00:09ec _testcase_end_91
-00:09fd _testcase_data_92
-00:0a00 _testcase_end_92
-00:0a11 _testcase_data_93
-00:0a14 _testcase_end_93
-00:0a25 _testcase_data_94
-00:0a28 _testcase_end_94
-00:0a39 _testcase_data_95
-00:0a44 _testcase_end_95
-00:0a55 _testcase_data_96
-00:0a60 _testcase_end_96
-00:0a71 _testcase_data_97
-00:0a7c _testcase_end_97
-00:0a8d _testcase_data_98
-00:0a98 _testcase_end_98
-00:0aa9 _testcase_data_99
-00:0ab4 _testcase_end_99
-00:0ac5 _testcase_data_100
-00:0ad0 _testcase_end_100
-00:0ae1 _testcase_data_101
-00:0aec _testcase_end_101
-00:0afd _testcase_data_102
-00:0b08 _testcase_end_102
-00:0b19 _testcase_data_103
-00:0b24 _testcase_end_103
-00:0b35 _testcase_data_104
-00:0b40 _testcase_end_104
-00:0b54 _wait_ly_4
-00:0b5a _wait_ly_5
-00:0b70 _print_results_halt_1
-00:0b73 _test_ok_cb_0
-00:0b7b _print_sl_data55
-00:0b83 _print_sl_out55
-00:0b86 run_testcase
-00:0b88 _wait_ly_6
-00:0b8e _wait_ly_7
-00:0bb9 testcase_round_a
-00:0bc4 testcase_round_a_ret
-00:0bd4 testcase_round_b
-00:0bdf testcase_round_b_ret
-00:0bf0 prepare_sprites
-00:0c06 prepare_nop_area
-00:0c0f setup_and_wait_mode2
-00:0c0f _wait_ly_8
-00:0c32 test_fail
-00:0c46 _wait_ly_9
-00:0c4c _wait_ly_10
-00:0c62 _print_results_halt_2
-00:0c65 _test_fail_cb
-00:0c6d _print_sl_data56
-00:0c74 _print_sl_out56
-00:0c82 _print_sl_data57
-00:0c8a _print_sl_out57
-00:0c8d fail_halt
-00:0ca1 _wait_ly_11
-00:0ca7 _wait_ly_12
-00:0cbd _print_results_halt_3
-00:0cc0 _test_failure_cb_0
-00:0cc8 _print_sl_data58
-00:0cd3 _print_sl_out58
-00:c000 testcase_id
-00:c002 nop_area_a
-00:c062 nop_area_b

cinema/gb/mooneye-gb/acceptance/gpu/intr_2_mode3_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_mode3_timing.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:01b5 setup_and_wait_mode2
-00:01b5 _wait_ly_6
-00:01d8 fail_halt
-00:01ec _wait_ly_7
-00:01f2 _wait_ly_8
-00:0208 _print_results_halt_1
-00:020b _test_failure_cb_0
-00:0213 _print_sl_data55
-00:021e _print_sl_out55

cinema/gb/mooneye-gb/acceptance/gpu/intr_2_oam_ok_timing/test.sym

@@ -1,202 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_2_oam_ok_timing.gb".
-
-[labels]
-01:4bff print_load_font
-01:4c0c print_string
-01:4c16 print_a
-01:4c20 print_newline
-01:4c2b print_digit
-01:4c38 print_regs
-01:4c41 _print_sl_data0
-01:4c47 _print_sl_out0
-01:4c54 _print_sl_data1
-01:4c5a _print_sl_out1
-01:4c6c _print_sl_data2
-01:4c72 _print_sl_out2
-01:4c7f _print_sl_data3
-01:4c85 _print_sl_out3
-01:4c97 _print_sl_data4
-01:4c9d _print_sl_out4
-01:4caa _print_sl_data5
-01:4cb0 _print_sl_out5
-01:4cc2 _print_sl_data6
-01:4cc8 _print_sl_out6
-01:4cd5 _print_sl_data7
-01:4cdb _print_sl_out7
-01:4000 font
-00:c000 regs_save
-00:c000 regs_save.f
-00:c001 regs_save.a
-00:c002 regs_save.c
-00:c003 regs_save.b
-00:c004 regs_save.e
-00:c005 regs_save.d
-00:c006 regs_save.l
-00:c007 regs_save.h
-00:c008 regs_flags
-00:c009 regs_assert
-00:c009 regs_assert.f
-00:c00a regs_assert.a
-00:c00b regs_assert.c
-00:c00c regs_assert.b
-00:c00d regs_assert.e
-00:c00e regs_assert.d
-00:c00f regs_assert.l
-00:c010 regs_assert.h
-00:c011 memdump_len
-00:c012 memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:0151 _wait_ly_4
-00:0157 _wait_ly_5
-00:020a setup_and_wait_mode2
-00:020a _wait_ly_6
-00:022d fail_halt
-00:0241 _wait_ly_7
-00:0247 _wait_ly_8
-00:025d _print_results_halt_1
-00:0260 _test_failure_cb_0
-00:0268 _print_sl_data55
-00:0273 _print_sl_out55

cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/test.sym

@@ -1,236 +0,0 @@
-; this file was created with wlalink by ville helin <vhelin@iki.fi>.
-; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/lcdon_timing-dmgABCXmgbS.gb".
-
-[labels]
-01:5087 print_load_font
-01:5094 print_string
-01:509e print_a
-01:50a8 print_newline
-01:50b3 print_digit
-01:50c0 print_regs
-01:50c9 _print_sl_data0
-01:50cf _print_sl_out0
-01:50dc _print_sl_data1
-01:50e2 _print_sl_out1
-01:50f4 _print_sl_data2
-01:50fa _print_sl_out2
-01:5107 _print_sl_data3
-01:510d _print_sl_out3
-01:511f _print_sl_data4
-01:5125 _print_sl_out4
-01:5132 _print_sl_data5
-01:5138 _print_sl_out5
-01:514a _print_sl_data6
-01:5150 _print_sl_out6
-01:515d _print_sl_data7
-01:5163 _print_sl_out7
-01:4000 font
-00:c01d regs_save
-00:c01d regs_save.f
-00:c01e regs_save.a
-00:c01f regs_save.c
-00:c020 regs_save.b
-00:c021 regs_save.e
-00:c022 regs_save.d
-00:c023 regs_save.l
-00:c024 regs_save.h
-00:c025 regs_flags
-00:c026 regs_assert
-00:c026 regs_assert.f
-00:c027 regs_assert.a
-00:c028 regs_assert.c
-00:c029 regs_assert.b
-00:c02a regs_assert.e
-00:c02b regs_assert.d
-00:c02c regs_assert.l
-00:c02d regs_assert.h
-00:c02e memdump_len
-00:c02f memdump_addr
-01:47f0 memcpy
-01:47f9 memset
-01:4802 memcmp
-01:4810 clear_vram
-01:481a clear_oam
-01:4824 disable_lcd_safe
-01:482a _wait_ly_0
-01:4830 _wait_ly_1
-01:4839 reset_screen
-01:484d process_results
-01:4861 _wait_ly_2
-01:4867 _wait_ly_3
-01:487d _print_results_halt_0
-01:4880 _process_results_cb
-01:488b _print_sl_data8
-01:4895 _print_sl_out8
-01:48af _print_sl_data9
-01:48ba _print_sl_out9
-01:48d2 _print_sl_data10
-01:48de _print_sl_out10
-01:48df dump_mem
-01:48fe _dump_mem_line
-01:4928 _check_asserts
-01:4936 _print_sl_data11
-01:4939 _print_sl_out11
-01:4945 _print_sl_data12
-01:4947 _print_sl_out12
-01:494f _print_sl_data13
-01:4952 _print_sl_out13
-01:495c __check_assert_fail0
-01:4967 _print_sl_data14
-01:496a _print_sl_out14
-01:496d __check_assert_ok0
-01:4975 _print_sl_data15
-01:497a _print_sl_out15
-01:497c __check_assert_skip0
-01:4984 _print_sl_data16
-01:498c _print_sl_out16
-01:498c __check_assert_out0
-01:4998 _print_sl_data17
-01:499a _print_sl_out17
-01:49a2 _print_sl_data18
-01:49a5 _print_sl_out18
-01:49af __check_assert_fail1
-01:49ba _print_sl_data19
-01:49bd _print_sl_out19
-01:49c0 __check_assert_ok1
-01:49c8 _print_sl_data20
-01:49cd _print_sl_out20
-01:49cf __check_assert_skip1
-01:49d7 _print_sl_data21
-01:49df _print_sl_out21
-01:49df __check_assert_out1
-01:49ea _print_sl_data22
-01:49ed _print_sl_out22
-01:49f9 _print_sl_data23
-01:49fb _print_sl_out23
-01:4a03 _print_sl_data24
-01:4a06 _print_sl_out24
-01:4a10 __check_assert_fail2
-01:4a1b _print_sl_data25
-01:4a1e _print_sl_out25
-01:4a21 __check_assert_ok2
-01:4a29 _print_sl_data26
-01:4a2e _print_sl_out26
-01:4a30 __check_assert_skip2
-01:4a38 _print_sl_data27
-01:4a40 _print_sl_out27
-01:4a40 __check_assert_out2
-01:4a4c _print_sl_data28
-01:4a4e _print_sl_out28
-01:4a56 _print_sl_data29
-01:4a59 _print_sl_out29
-01:4a63 __check_assert_fail3
-01:4a6e _print_sl_data30
-01:4a71 _print_sl_out30
-01:4a74 __check_assert_ok3
-01:4a7c _print_sl_data31
-01:4a81 _print_sl_out31
-01:4a83 __check_assert_skip3
-01:4a8b _print_sl_data32
-01:4a93 _print_sl_out32
-01:4a93 __check_assert_out3
-01:4a9e _print_sl_data33
-01:4aa1 _print_sl_out33
-01:4aad _print_sl_data34
-01:4aaf _print_sl_out34
-01:4ab7 _print_sl_data35
-01:4aba _print_sl_out35
-01:4ac4 __check_assert_fail4
-01:4acf _print_sl_data36
-01:4ad2 _print_sl_out36
-01:4ad5 __check_assert_ok4
-01:4add _print_sl_data37
-01:4ae2 _print_sl_out37
-01:4ae4 __check_assert_skip4
-01:4aec _print_sl_data38
-01:4af4 _print_sl_out38
-01:4af4 __check_assert_out4
-01:4b00 _print_sl_data39
-01:4b02 _print_sl_out39
-01:4b0a _print_sl_data40
-01:4b0d _print_sl_out40
-01:4b17 __check_assert_fail5
-01:4b22 _print_sl_data41
-01:4b25 _print_sl_out41
-01:4b28 __check_assert_ok5
-01:4b30 _print_sl_data42
-01:4b35 _print_sl_out42
-01:4b37 __check_assert_skip5
-01:4b3f _print_sl_data43
-01:4b47 _print_sl_out43
-01:4b47 __check_assert_out5
-01:4b52 _print_sl_data44
-01:4b55 _print_sl_out44
-01:4b61 _print_sl_data45
-01:4b63 _print_sl_out45
-01:4b6b _print_sl_data46
-01:4b6e _print_sl_out46
-01:4b78 __check_assert_fail6
-01:4b83 _print_sl_data47
-01:4b86 _print_sl_out47
-01:4b89 __check_assert_ok6
-01:4b91 _print_sl_data48
-01:4b96 _print_sl_out48
-01:4b98 __check_assert_skip6
-01:4ba0 _print_sl_data49
-01:4ba8 _print_sl_out49
-01:4ba8 __check_assert_out6
-01:4bb4 _print_sl_data50
-01:4bb6 _print_sl_out50
-01:4bbe _print_sl_data51
-01:4bc1 _print_sl_out51
-01:4bcb __check_assert_fail7
-01:4bd6 _print_sl_data52
-01:4bd9 _print_sl_out52
-01:4bdc __check_assert_ok7
-01:4be4 _print_sl_data53
-01:4be9 _print_sl_out53
-01:4beb __check_assert_skip7
-01:4bf3 _print_sl_data54
-01:4bfb _print_sl_out54
-01:4bfb __check_assert_out7
-00:015a test_ly
-00:0166 test_stat_lyc0
-00:0175 test_stat_lyc1
-00:0185 test_oam_access
-00:0191 test_vram_access
-00:019d test_finish
-00:01b1 _wait_ly_4
-00:01b7 _wait_ly_5
-00:01cd _print_results_halt_1
-00:01d0 _test_ok_cb_0
-00:01d8 _print_sl_data55
-00:01e0 _print_sl_out55
-01:4ed8 cycle_counts
-01:4ef0 expect_ly
-01:4f0b expect_stat_lyc0
-01:4f2e expect_stat_lyc1
-01:4f51 expect_oam_access
-01:4f74 expect_vram_access
-01:4f98 verify_results
-01:4faf verify_fail
-01:4fdd _wait_ly_6
-01:4fe3 _wait_ly_7
-01:4ff9 _print_results_halt_2
-01:4ffc _verify_fail_cb
-01:5004 _print_sl_data56
-01:5012 _print_sl_out56
-01:502e _print_sl_data57
-01:503a _print_sl_out57
-01:5055 _print_sl_data58
-01:5061 _print_sl_out58
-01:5072 _print_sl_data59
-01:507e _print_sl_out59
-00:c000 v_pass1_results
-00:c008 v_pass2_results
-00:c010 v_pass3_results
-00:c018 v_fail_round
-00:c019 v_fail_expect
-00:c01a v_fail_actual
-00:c01b v_fail_str
-00:c01b v_fail_str_l
-00:c01c v_fail_str_h
-01:4bff test_passes
-01:4bff test_pass1
-01:4cf1 test_pass2
-01:4de4 test_pass3