Jaklyy
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e93381dfa4
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-21 12:31:54 -04:00 |
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Jaklyy
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af09e37d53
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attempt at twl timings
also rework main ram's early finish handling
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2024-10-21 11:38:26 -04:00 |
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Jaklyy
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744f5c9fcd
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small fixes
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2024-10-19 16:51:40 -04:00 |
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Jaklyy
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a32d59774e
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-19 12:35:39 -04:00 |
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Jaklyy
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e254ac3240
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fix ldrd/strd itcm timings
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2024-10-19 12:35:27 -04:00 |
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Jaklyy
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8fff17f03f
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fix resets
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2024-10-19 11:01:16 -04:00 |
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Jaklyy
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d4216309a2
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hdfg
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2024-10-19 11:00:51 -04:00 |
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Jaklyy
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051b236839
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-18 21:10:39 -04:00 |
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Jaklyy
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e33d19cf14
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fix a few misc things?
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2024-10-18 21:08:56 -04:00 |
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Jaklyy
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9ed4c66592
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add support for 1 reg ldm/stm a9 timings and fix a bug
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2024-10-18 17:56:56 -04:00 |
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Jaklyy
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8ff0946b8a
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mrc causes interlocks
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2024-10-18 17:10:00 -04:00 |
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Jaklyy
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0e6d3fd834
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fix bad logical leaps
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2024-10-18 16:32:02 -04:00 |
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Jaklyy
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cc031cd4b8
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-18 15:01:14 -04:00 |
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Jaklyy
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e2a810147f
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re-add interlocks
breaks gcc debug builds for ??? reason
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2024-10-18 15:00:55 -04:00 |
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Jaklyy
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68e8ff41eb
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this barely makes a difference in practice but it's less inefficient
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2024-10-17 10:08:11 -04:00 |
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Jaklyy
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ffb24e7088
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wrong bitshift
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2024-10-16 22:42:24 -04:00 |
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Jaklyy
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26a6e887ad
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aarch64 neon impl take one
fingers crossed it compiles!
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2024-10-16 22:26:56 -04:00 |
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Jaklyy
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d7212643f1
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move arm9 code fetches into the cycle add routine
setting up for re-adding interlocks
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2024-10-16 12:21:48 -04:00 |
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Jaklyy
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9f2b097e96
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-15 22:36:29 -04:00 |
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Jaklyy
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52ddaa73cf
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fix resets
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2024-10-15 22:36:21 -04:00 |
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Jaklyy
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21763ceed3
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reduce memtimings lut granularity
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2024-10-15 21:20:10 -04:00 |
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Jaklyy
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c605c93d8e
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still dumb
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2024-10-15 21:08:46 -04:00 |
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Jaklyy
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3fcdc45029
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-15 21:08:13 -04:00 |
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Jaklyy
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c00b188c05
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im dumb
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2024-10-15 21:08:07 -04:00 |
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Jaklyy
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460fd45aed
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remove some old code
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2024-10-15 20:27:09 -04:00 |
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Jaklyy
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bb2727b786
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-15 20:25:16 -04:00 |
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Jaklyy
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05c153e9ab
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Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
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2024-10-15 20:23:14 -04:00 |
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Jaklyy
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5f003eb967
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fix builds with jit disabled
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2024-10-15 20:23:03 -04:00 |
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Jaklyy
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d476593eec
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add notes
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2024-10-15 12:40:35 -04:00 |
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Jaklyy
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d8d2fcd94a
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more optimizations
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2024-10-14 23:43:11 -04:00 |
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Jaklyy
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263dd20ec3
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nvmnvmnvm
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2024-10-14 22:48:25 -04:00 |
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Jaklyy
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ca7d938bb1
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update for new write buffer implementation
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2024-10-14 20:18:23 -04:00 |
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Jaklyy
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9f3ebeafa7
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-14 20:16:58 -04:00 |
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Jaklyy
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026719acef
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improve timing model
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2024-10-14 20:15:03 -04:00 |
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Jaklyy
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f74c21d110
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-13 20:07:04 -04:00 |
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Jaklyy
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801f43dfc5
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reimplement codemem
i dont feel like i actually had a good reason for disabling this...
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2024-10-13 20:06:39 -04:00 |
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Jaklyy
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1afefdce1d
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use sse for set lookups
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2024-10-13 08:39:07 -04:00 |
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Jaklyy
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206fc94d68
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Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
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2024-10-12 14:35:28 -04:00 |
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Jaklyy
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e0e78a2bc8
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make empty r-list instructions a bit nicer
pass bools as a single u8 instead and combine thumb and restore cpsr flags since they're mutually exclusive
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2024-10-12 11:10:06 -04:00 |
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Jaklyy
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a8722d8c56
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tcms shouldn't be cacheable
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2024-10-11 02:47:41 -04:00 |
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Jaklyy
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6b8671d80a
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Merge branch 'less-ambitious-timing-rework' into chemical-x
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2024-10-11 02:05:44 -04:00 |
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Jaklyy
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9f6cbd8e84
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implement drain write buffer cache command
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2024-10-10 23:24:20 -04:00 |
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Jaklyy
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3d246ddf73
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tcms just aren't bufferable
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2024-10-10 22:54:33 -04:00 |
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Jaklyy
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34bba2589e
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tcm (and cache?) reads dont trigger write buffer drains
additionally drains are triggered even in no cache + no buffer regions despite documentation not specifying such
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2024-10-10 20:52:47 -04:00 |
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Jaklyy
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5c120f45ee
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Merge branch 'interpreter-fixes' into less-ambitious-timing-rework
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2024-10-10 20:34:00 -04:00 |
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Jaklyy
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787d0c9afc
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mrc r15 updates flags
also my prior implementation made mrc w/ r15 raise an exception by accident
oops!
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2024-10-10 11:09:07 -04:00 |
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Jaklyy
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93dce82b07
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implement cmp with "rd == 15" on arm9
cmp and friends with bits 12-15 set to 1 borrow characteristics from their legacy 26 bit p variants
thumb version does nothing of note
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2024-10-10 10:48:17 -04:00 |
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Jaklyy
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3870216fd0
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correction:
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2024-10-10 03:53:51 -04:00 |
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Jaklyy
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53b38c363f
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ok no it didn't lie to me
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2024-10-10 03:32:53 -04:00 |
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Jaklyy
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e25dca0030
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writing to the write buffer has a 1 cycle delay before it can be done again
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2024-10-10 03:14:01 -04:00 |