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update for new write buffer implementation

This commit is contained in:
Jaklyy 2024-10-14 20:18:23 -04:00
parent 9f3ebeafa7
commit ca7d938bb1
1 changed files with 26 additions and 46 deletions
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72
src/CP15.cpp
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@ -896,56 +896,36 @@ void ARMv5::DCacheClearByASetAndWay(const u8 cacheSet, const u8 cacheLine)
if (DCacheTags[index] & CACHE_FLAG_DIRTY_LOWERHALF)
{
WriteBufferWrite(tag, 3, 1);
WriteBufferWrite(ptr[0], 2, MemTimings[tag >> 12][2], tag+0x00);
WriteBufferWrite(ptr[1], 2, MemTimings[tag >> 12][3], tag+0x04);
WriteBufferWrite(ptr[2], 2, MemTimings[tag >> 12][3], tag+0x08);
WriteBufferWrite(ptr[3], 2, MemTimings[tag >> 12][3], tag+0x0C);
if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
u8 cyclesn = NDS.ARM9MemTimings[tag>>14][2];
if ((tag >> 24) == 0x02) cyclesn = (cyclesn - 2) & 0x80;
u8 cycless = NDS.ARM9MemTimings[tag>>14][3];
if ((tag >> 24) == 0x02) cycless = (cycless - 2) & 0x80;
WriteBufferWrite(tag, 3, 0);
WriteBufferWrite(ptr[0], 2, cyclesn, tag+0x00);
WriteBufferWrite(ptr[1], 2, cycless, tag+0x04);
WriteBufferWrite(ptr[2], 2, cycless, tag+0x08);
WriteBufferWrite(ptr[3], 2, cycless, tag+0x0C);
DataCycles += 5;
/*//Log(LogLevel::Debug, "Writing back %i / %i, lower half -> %08lx\n", cacheSet, cacheLine, tag);
for (int i = 0; i < DCACHE_LINELENGTH / 2; i+=sizeof(u32))
{
//Log(LogLevel::Debug, " WB Value %08x\n", ptr[i >> 2]);
if (tag+i < ITCMSize)
{
*(u32*)&ITCM[(tag+i) & (ITCMPhysicalSize - 1)] = ptr[i >> 2];
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(tag+i);
} else
if (((tag+i) & DTCMMask) == DTCMBase)
{
*(u32*)&DTCM[(tag+i) & (DTCMPhysicalSize - 1)] = ptr[i >> 2];
} else
{
BusWrite32(tag+i, ptr[i >> 2]);
}
}
DataCycles += (NDS.ARM9MemTimings[tag >> 14][2] + (NDS.ARM9MemTimings[tag >> 14][3] * ((DCACHE_LINELENGTH / 8) - 1))) << NDS.ARM9ClockShift;*/
}
if (DCacheTags[index] & CACHE_FLAG_DIRTY_UPPERHALF)
{
//Log(LogLevel::Debug, "Writing back %i / %i, upper half-> %08lx\n", cacheSet, cacheLine, tag);
/*for (int i = DCACHE_LINELENGTH / 2; i < DCACHE_LINELENGTH; i+=sizeof(u32))
{
//Log(LogLevel::Debug, " WB Value %08x\n", ptr[i >> 2]);
if (tag+i < ITCMSize)
{
*(u32*)&ITCM[(tag+i) & (ITCMPhysicalSize - 1)] = ptr[i >> 2];
NDS.JIT.CheckAndInvalidate<0, ARMJIT_Memory::memregion_ITCM>(tag+i);
} else
if (((tag+i) & DTCMMask) == DTCMBase)
{
*(u32*)&DTCM[(tag+i) & (DTCMPhysicalSize - 1)] = ptr[i >> 2];
} else
{
BusWrite32(tag+i, ptr[i >> 2]);
}
}
DataCycles += (NDS.ARM9MemTimings[tag >> 14][2] + (NDS.ARM9MemTimings[tag >> 14][3] * ((DCACHE_LINELENGTH / 8) - 1))) << NDS.ARM9ClockShift;*/
WriteBufferWrite(tag+0x10, 3, 1);
WriteBufferWrite(ptr[4], 2, MemTimings[tag >> 12][2], tag+0x10);
WriteBufferWrite(ptr[5], 2, MemTimings[tag >> 12][3], tag+0x14);
WriteBufferWrite(ptr[6], 2, MemTimings[tag >> 12][3], tag+0x18);
WriteBufferWrite(ptr[7], 2, MemTimings[tag >> 12][3], tag+0x1C);
if (WBDelay > NDS.ARM9Timestamp) NDS.ARM9Timestamp = WBDelay;
u8 cyclesn = NDS.ARM9MemTimings[tag>>14][2];
if ((tag >> 24) == 0x02) cyclesn = (cyclesn - 2) & 0x80;
u8 cycless = NDS.ARM9MemTimings[tag>>14][3];
if ((tag >> 24) == 0x02) cycless = (cycless - 2) & 0x80;
WriteBufferWrite(tag+0x10, 3, 0);
WriteBufferWrite(ptr[4], 2, cyclesn, tag+0x10);
WriteBufferWrite(ptr[5], 2, cycless, tag+0x14);
WriteBufferWrite(ptr[6], 2, cycless, tag+0x18);
WriteBufferWrite(ptr[7], 2, cycless, tag+0x1C);
DataCycles += 5;
}
DCacheTags[index] &= ~(CACHE_FLAG_DIRTY_LOWERHALF | CACHE_FLAG_DIRTY_UPPERHALF);