StapleButter
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343797f47d
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* somewhat proper event scheduler
* support for timers
* fixes, additions, shit
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2016-12-05 17:08:24 +01:00 |
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StapleButter
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a14c01208a
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fix some shit. add support for SPI and firmware.
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2016-12-04 03:20:50 +01:00 |
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StapleButter
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d7c1d77ba2
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more instructions. shared WRAM.
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2016-12-03 18:29:19 +01:00 |
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StapleButter
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1e4086e1b6
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moar instructions and shit implemented
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2016-12-03 17:58:24 +01:00 |
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StapleButter
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f2858e1c47
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less amnesia! ITCM, DTCM, corresponding CP15 support
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2016-12-03 16:13:04 +01:00 |
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StapleButter
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53bef35cd1
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more crap implemented!
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2016-12-03 15:15:34 +01:00 |
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StapleButter
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948cdeab59
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amnesia is over
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2016-12-03 13:42:27 +01:00 |
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StapleButter
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30f85e3400
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more instructions. some handling of CPU mode switching.
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2016-12-03 04:41:10 +01:00 |
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StapleButter
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6213245f3a
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moar shit
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2016-12-03 04:05:23 +01:00 |
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StapleButter
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ae6e9d96da
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ARM ALU is done with. as well as other shit.
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2016-12-03 03:10:26 +01:00 |
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StapleButter
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844ca45055
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add MSR/MRS. also fix misc error with LDR ROR effect.
see shibboleet, I can do it too :>
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2016-12-03 02:09:04 +01:00 |
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StapleButter
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23d584ca4c
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implement LDR/STR/LDRB/STRB.
more macro soup.
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2016-12-03 01:31:33 +01:00 |
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StapleButter
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97ec988dae
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more shit! some start of ALU emulation
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2016-11-25 00:08:53 +01:00 |
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StapleButter
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f74fb2dd27
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well, adding shit. laying out the base for the interpreter. really dirty code.
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2016-11-24 18:31:49 +01:00 |
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StapleButter
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3505ec993b
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hey look, more crap
no MrRean this doesn't run NSMB yet
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2016-11-03 01:38:58 +01:00 |
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StapleButter
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5b7ae6dab3
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add more crap
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2016-05-16 17:48:40 +02:00 |
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StapleButter
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cfdfd4b231
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first real commit, some shit is in
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2016-05-16 03:40:11 +02:00 |
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StapleButter
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e0255fb957
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Initial commit
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2016-05-16 03:34:14 +02:00 |