ShuriZma
/
melonDS
mirror of https://github.com/melonDS-emu/melonDS.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

moar shit

This commit is contained in:
StapleButter 2016-12-03 04:05:23 +01:00
parent ae6e9d96da
commit 6213245f3a
6 changed files with 295 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

39
ARMInterpreter_Branch.cpp
View File

@ -1,3 +1,4 @@
#include <stdio.h>
#include "ARM.h"
@ -32,6 +33,22 @@ s32 A_BLX_IMM(ARM* cpu)
return C_S(2) + C_N(1);
}
s32 A_BX(ARM* cpu)
{
cpu->JumpTo(cpu->R[cpu->CurInstr & 0xF]);
return C_S(2) + C_N(1);
}
s32 A_BLX_REG(ARM* cpu)
{
u32 lr = cpu->R[15] - 4;
cpu->JumpTo(cpu->R[cpu->CurInstr & 0xF]);
cpu->R[14] = lr;
return C_S(2) + C_N(1);
}
s32 T_BCOND(ARM* cpu)
@ -46,6 +63,28 @@ s32 T_BCOND(ARM* cpu)
return C_S(1);
}
s32 T_BX(ARM* cpu)
{
cpu->JumpTo(cpu->R[(cpu->CurInstr >> 3) & 0xF]);
return C_S(2) + C_N(1);
}
s32 T_BLX_REG(ARM* cpu)
{
if (cpu->Num==1)
{
printf("!! THUMB BLX_REG ON ARM7\n");
return 1;
}
u32 lr = cpu->R[15] - 1;
cpu->JumpTo(cpu->R[(cpu->CurInstr >> 3) & 0xF]);
cpu->R[14] = lr;
return C_S(2) + C_N(1);
}
}

4
ARMInterpreter_Branch.h
View File

@ -7,8 +7,12 @@ namespace ARMInterpreter
s32 A_B(ARM* cpu);
s32 A_BL(ARM* cpu);
s32 A_BX(ARM* cpu);
s32 A_BLX_REG(ARM* cpu);
s32 T_BCOND(ARM* cpu);
s32 T_BX(ARM* cpu);
s32 T_BLX_REG(ARM* cpu);
}

158
ARMInterpreter_LoadStore.cpp
View File

@ -196,6 +196,164 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write16(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_STRH_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->Write16(addr, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
// TODO: CHECK LDRD/STRD TIMINGS!!
#define A_LDRD \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
cpu->R[r ] = cpu->Read32(offset ); \
cpu->R[r+1] = cpu->Read32(offset+4); \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset);
#define A_LDRD_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
cpu->R[r ] = cpu->Read32(addr ); \
cpu->R[r+1] = cpu->Read32(addr+4); \
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
#define A_STRD \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
cpu->Write32(offset , cpu->R[r ]); \
cpu->Write32(offset+4, cpu->R[r+1]); \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_STRD_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
cpu->Write32(offset , cpu->R[r ]); \
cpu->Write32(offset+4, cpu->R[r+1]); \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_LDRH \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(offset); \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_LDRH_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(addr); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_LDRSB \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(offset); \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_LDRSB_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(addr); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_LDRSH \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(offset); \
if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
return C_N(2) + cpu->MemWaitstate(3, offset);
#define A_LDRSH_POST \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(addr); \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
return C_N(2) + cpu->MemWaitstate(3, addr);
#define A_IMPLEMENT_HD_LDRSTR(x) \
\
s32 A_##x##_IMM(ARM* cpu) \
{ \
A_HD_CALC_OFFSET_IMM \
A_##x \
} \
\
s32 A_##x##_REG(ARM* cpu) \
{ \
A_HD_CALC_OFFSET_REG \
A_##x \
} \
s32 A_##x##_POST_IMM(ARM* cpu) \
{ \
A_HD_CALC_OFFSET_IMM \
A_##x##_POST \
} \
\
s32 A_##x##_POST_REG(ARM* cpu) \
{ \
A_HD_CALC_OFFSET_REG \
A_##x##_POST \
}
A_IMPLEMENT_HD_LDRSTR(STRH)
A_IMPLEMENT_HD_LDRSTR(LDRD)
A_IMPLEMENT_HD_LDRSTR(STRD)
A_IMPLEMENT_HD_LDRSTR(LDRH)
A_IMPLEMENT_HD_LDRSTR(LDRSB)
A_IMPLEMENT_HD_LDRSTR(LDRSH)
// ---- THUMB -----------------------
s32 T_LDR_PCREL(ARM* cpu)
{
u32 addr = cpu->R[15] + ((cpu->CurInstr & 0xFF) << 2);
cpu->R[(cpu->CurInstr >> 8) & 0x7] = cpu->Read32(addr);
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
}
s32 T_STR_REG(ARM* cpu)
{
u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
cpu->Write32(addr, cpu->R[cpu->CurInstr & 0x7]);
return C_N(2) + cpu->MemWaitstate(3, addr);
}
s32 T_STRB_REG(ARM* cpu)
{
u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
cpu->Write8(addr, cpu->R[cpu->CurInstr & 0x7]);
return C_N(2) + cpu->MemWaitstate(3, addr);
}
s32 T_LDR_REG(ARM* cpu)
{
u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
cpu->R[cpu->CurInstr & 0x7] = cpu->Read32(addr);
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
}
s32 T_LDRB_REG(ARM* cpu)
{
u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
cpu->R[cpu->CurInstr & 0x7] = cpu->Read8(addr);
return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
}
}

22
ARMInterpreter_LoadStore.h
View File

@ -23,6 +23,28 @@ A_PROTO_WB_LDRSTR(STRB)
A_PROTO_WB_LDRSTR(LDR)
A_PROTO_WB_LDRSTR(LDRB)
#define A_PROTO_HD_LDRSTR(x) \
\
s32 A_##x##_IMM(ARM* cpu); \
s32 A_##x##_REG(ARM* cpu); \
s32 A_##x##_POST_IMM(ARM* cpu); \
s32 A_##x##_POST_REG(ARM* cpu);
A_PROTO_HD_LDRSTR(STRH)
A_PROTO_HD_LDRSTR(LDRD)
A_PROTO_HD_LDRSTR(STRD)
A_PROTO_HD_LDRSTR(LDRH)
A_PROTO_HD_LDRSTR(LDRSB)
A_PROTO_HD_LDRSTR(LDRSH)
s32 T_LDR_PCREL(ARM* cpu);
s32 T_STR_REG(ARM* cpu);
s32 T_STRB_REG(ARM* cpu);
s32 T_LDR_REG(ARM* cpu);
s32 T_LDRB_REG(ARM* cpu);
}
#endif

132
ARM_InstrTable.h
View File

@ -4,14 +4,14 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0000 0000 0000
A_AND_REG_LSL_IMM, A_AND_REG_LSL_REG, A_AND_REG_LSR_IMM, A_AND_REG_LSR_REG,
A_AND_REG_ASR_IMM, A_AND_REG_ASR_REG, A_AND_REG_ROR_IMM, A_AND_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_POST_REG,
A_UNK, A_LDRD_POST_REG, A_UNK, A_STRD_POST_REG,
// 0000 0001 0000
A_AND_REG_LSL_IMM_S, A_AND_REG_LSL_REG_S, A_AND_REG_LSR_IMM_S, A_AND_REG_LSR_REG_S,
A_AND_REG_ASR_IMM_S, A_AND_REG_ASR_REG_S, A_AND_REG_ROR_IMM_S, A_AND_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_POST_REG,
A_UNK, A_LDRSB_POST_REG, A_UNK, A_LDRSH_POST_REG,
// 0000 0010 0000
A_EOR_REG_LSL_IMM, A_EOR_REG_LSL_REG, A_EOR_REG_LSR_IMM, A_EOR_REG_LSR_REG,
@ -28,14 +28,14 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0000 0100 0000
A_SUB_REG_LSL_IMM, A_SUB_REG_LSL_REG, A_SUB_REG_LSR_IMM, A_SUB_REG_LSR_REG,
A_SUB_REG_ASR_IMM, A_SUB_REG_ASR_REG, A_SUB_REG_ROR_IMM, A_SUB_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_POST_IMM,
A_UNK, A_LDRD_POST_IMM, A_UNK, A_STRD_POST_IMM,
// 0000 0101 0000
A_SUB_REG_LSL_IMM_S, A_SUB_REG_LSL_REG_S, A_SUB_REG_LSR_IMM_S, A_SUB_REG_LSR_REG_S,
A_SUB_REG_ASR_IMM_S, A_SUB_REG_ASR_REG_S, A_SUB_REG_ROR_IMM_S, A_SUB_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_POST_IMM,
A_UNK, A_LDRSB_POST_IMM, A_UNK, A_LDRSH_POST_IMM,
// 0000 0110 0000
A_RSB_REG_LSL_IMM, A_RSB_REG_LSL_REG, A_RSB_REG_LSR_IMM, A_RSB_REG_LSR_REG,
@ -52,14 +52,14 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0000 1000 0000
A_ADD_REG_LSL_IMM, A_ADD_REG_LSL_REG, A_ADD_REG_LSR_IMM, A_ADD_REG_LSR_REG,
A_ADD_REG_ASR_IMM, A_ADD_REG_ASR_REG, A_ADD_REG_ROR_IMM, A_ADD_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_POST_REG,
A_UNK, A_LDRD_POST_REG, A_UNK, A_STRD_POST_REG,
// 0000 1001 0000
A_ADD_REG_LSL_IMM_S, A_ADD_REG_LSL_REG_S, A_ADD_REG_LSR_IMM_S, A_ADD_REG_LSR_REG_S,
A_ADD_REG_ASR_IMM_S, A_ADD_REG_ASR_REG_S, A_ADD_REG_ROR_IMM_S, A_ADD_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_POST_REG,
A_UNK, A_LDRSB_POST_REG, A_UNK, A_LDRSH_POST_REG,
// 0000 1010 0000
A_ADC_REG_LSL_IMM, A_ADC_REG_LSL_REG, A_ADC_REG_LSR_IMM, A_ADC_REG_LSR_REG,
@ -76,14 +76,14 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0000 1100 0000
A_SBC_REG_LSL_IMM, A_SBC_REG_LSL_REG, A_SBC_REG_LSR_IMM, A_SBC_REG_LSR_REG,
A_SBC_REG_ASR_IMM, A_SBC_REG_ASR_REG, A_SBC_REG_ROR_IMM, A_SBC_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_POST_IMM,
A_UNK, A_LDRD_POST_IMM, A_UNK, A_STRD_POST_IMM,
// 0000 1101 0000
A_SBC_REG_LSL_IMM_S, A_SBC_REG_LSL_REG_S, A_SBC_REG_LSR_IMM_S, A_SBC_REG_LSR_REG_S,
A_SBC_REG_ASR_IMM_S, A_SBC_REG_ASR_REG_S, A_SBC_REG_ROR_IMM_S, A_SBC_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_POST_IMM,
A_UNK, A_LDRSB_POST_IMM, A_UNK, A_LDRSH_POST_IMM,
// 0000 1110 0000
A_RSC_REG_LSL_IMM, A_RSC_REG_LSL_REG, A_RSC_REG_LSR_IMM, A_RSC_REG_LSR_REG,
@ -102,98 +102,98 @@ INSTRFUNC_PROTO(ARMInstrTable[4096]) =
// 0001 0000 0000
A_MRS, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_REG,
A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG,
// 0001 0001 0000
A_TST_REG_LSL_IMM, A_TST_REG_LSL_REG, A_TST_REG_LSR_IMM, A_TST_REG_LSR_REG,
A_TST_REG_ASR_IMM, A_TST_REG_ASR_REG, A_TST_REG_ROR_IMM, A_TST_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_REG,
A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG,
// 0001 0010 0000
A_MSR_REG, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_MSR_REG, A_BX, A_UNK, A_BLX_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_REG,
A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG,
// 0001 0011 0000
A_TEQ_REG_LSL_IMM, A_TEQ_REG_LSL_REG, A_TEQ_REG_LSR_IMM, A_TEQ_REG_LSR_REG,
A_TEQ_REG_ASR_IMM, A_TEQ_REG_ASR_REG, A_TEQ_REG_ROR_IMM, A_TEQ_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_REG,
A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG,
// 0001 0100 0000
A_MRS, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_IMM,
A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM,
// 0001 0101 0000
A_CMP_REG_LSL_IMM, A_CMP_REG_LSL_REG, A_CMP_REG_LSR_IMM, A_CMP_REG_LSR_REG,
A_CMP_REG_ASR_IMM, A_CMP_REG_ASR_REG, A_CMP_REG_ROR_IMM, A_CMP_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_IMM,
A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM,
// 0001 0110 0000
A_MSR_REG, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_IMM,
A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM,
// 0001 0111 0000
A_CMN_REG_LSL_IMM, A_CMN_REG_LSL_REG, A_CMN_REG_LSR_IMM, A_CMN_REG_LSR_REG,
A_CMN_REG_ASR_IMM, A_CMN_REG_ASR_REG, A_CMN_REG_ROR_IMM, A_CMN_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_IMM,
A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM,
// 0001 1000 0000
A_ORR_REG_LSL_IMM, A_ORR_REG_LSL_REG, A_ORR_REG_LSR_IMM, A_ORR_REG_LSR_REG,
A_ORR_REG_ASR_IMM, A_ORR_REG_ASR_REG, A_ORR_REG_ROR_IMM, A_ORR_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_REG,
A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG,
// 0001 1001 0000
A_ORR_REG_LSL_IMM_S, A_ORR_REG_LSL_REG_S, A_ORR_REG_LSR_IMM_S, A_ORR_REG_LSR_REG_S,
A_ORR_REG_ASR_IMM_S, A_ORR_REG_ASR_REG_S, A_ORR_REG_ROR_IMM_S, A_ORR_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_REG,
A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG,
// 0001 1010 0000
A_MOV_REG_LSL_IMM, A_MOV_REG_LSL_REG, A_MOV_REG_LSR_IMM, A_MOV_REG_LSR_REG,
A_MOV_REG_ASR_IMM, A_MOV_REG_ASR_REG, A_MOV_REG_ROR_IMM, A_MOV_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_REG,
A_UNK, A_LDRD_REG, A_UNK, A_STRD_REG,
// 0001 1011 0000
A_MOV_REG_LSL_IMM_S, A_MOV_REG_LSL_REG_S, A_MOV_REG_LSR_IMM_S, A_MOV_REG_LSR_REG_S,
A_MOV_REG_ASR_IMM_S, A_MOV_REG_ASR_REG_S, A_MOV_REG_ROR_IMM_S, A_MOV_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_REG,
A_UNK, A_LDRSB_REG, A_UNK, A_LDRSH_REG,
// 0001 1100 0000
A_BIC_REG_LSL_IMM, A_BIC_REG_LSL_REG, A_BIC_REG_LSR_IMM, A_BIC_REG_LSR_REG,
A_BIC_REG_ASR_IMM, A_BIC_REG_ASR_REG, A_BIC_REG_ROR_IMM, A_BIC_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_IMM,
A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM,
// 0001 1101 0000
A_BIC_REG_LSL_IMM_S, A_BIC_REG_LSL_REG_S, A_BIC_REG_LSR_IMM_S, A_BIC_REG_LSR_REG_S,
A_BIC_REG_ASR_IMM_S, A_BIC_REG_ASR_REG_S, A_BIC_REG_ROR_IMM_S, A_BIC_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_IMM,
A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM,
// 0001 1110 0000
A_MVN_REG_LSL_IMM, A_MVN_REG_LSL_REG, A_MVN_REG_LSR_IMM, A_MVN_REG_LSR_REG,
A_MVN_REG_ASR_IMM, A_MVN_REG_ASR_REG, A_MVN_REG_ROR_IMM, A_MVN_REG_ROR_REG,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_STRH_IMM,
A_UNK, A_LDRD_IMM, A_UNK, A_STRD_IMM,
// 0001 1111 0000
A_MVN_REG_LSL_IMM_S, A_MVN_REG_LSL_REG_S, A_MVN_REG_LSR_IMM_S, A_MVN_REG_LSR_REG_S,
A_MVN_REG_ASR_IMM_S, A_MVN_REG_ASR_REG_S, A_MVN_REG_ROR_IMM_S, A_MVN_REG_ROR_REG_S,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_UNK,
A_UNK, A_UNK, A_UNK, A_LDRH_IMM,
A_UNK, A_LDRSB_IMM, A_UNK, A_LDRSH_IMM,
@ -1678,41 +1678,41 @@ INSTRFUNC_PROTO(THUMBInstrTable[1024]) =
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_BX, T_BX, T_BLX_REG, T_BLX_REG,
// 0100 1000 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
// 0100 1100 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL, T_LDR_PCREL,
// 0101 0000 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_STR_REG, T_STR_REG, T_STR_REG, T_STR_REG,
T_STR_REG, T_STR_REG, T_STR_REG, T_STR_REG,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
// 0101 0100 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_STRB_REG, T_STRB_REG, T_STRB_REG, T_STRB_REG,
T_STRB_REG, T_STRB_REG, T_STRB_REG, T_STRB_REG,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
// 0101 1000 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_LDR_REG, T_LDR_REG, T_LDR_REG, T_LDR_REG,
T_LDR_REG, T_LDR_REG, T_LDR_REG, T_LDR_REG,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
// 0101 1100 00
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,
T_LDRB_REG, T_LDRB_REG, T_LDRB_REG, T_LDRB_REG,
T_LDRB_REG, T_LDRB_REG, T_LDRB_REG, T_LDRB_REG,
T_UNK, T_UNK, T_UNK, T_UNK,
T_UNK, T_UNK, T_UNK, T_UNK,

11
melonDS.depend
View File

@ -23,7 +23,7 @@
"types.h"
"NDS.h"
1480730990 c:\documents\sources\melonds\arm_instrtable.h
1480734093 c:\documents\sources\melonds\arm_instrtable.h
1480725698 c:\documents\sources\melonds\arminterpreter.h
"types.h"
@ -38,9 +38,10 @@
"ARMInterpreter_LoadStore.h"
"ARM_InstrTable.h"
1480728965 c:\documents\sources\melonds\arminterpreter_branch.h
1480732290 c:\documents\sources\melonds\arminterpreter_branch.h
1480729161 source:c:\documents\sources\melonds\arminterpreter_branch.cpp
1480732453 source:c:\documents\sources\melonds\arminterpreter_branch.cpp
<stdio.h>
"ARM.h"
1480730181 c:\documents\sources\melonds\arminterpreter_alu.h
@ -48,8 +49,8 @@
1480730662 source:c:\documents\sources\melonds\arminterpreter_alu.cpp
"ARM.h"
1480724026 c:\documents\sources\melonds\arminterpreter_loadstore.h
1480734113 c:\documents\sources\melonds\arminterpreter_loadstore.h
1480725413 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
1480731825 source:c:\documents\sources\melonds\arminterpreter_loadstore.cpp
"ARM.h"