436b3c4c1d
update copyright year and add missing GPL headers
2021-03-12 20:07:40 +01:00
03b465c5e2
Fix edge case in the division engine, fix edge case in the CPU ( #1003 )
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* Fixed division edge case: Div64/32 and Div64/64 set the remainder to 0 if dividend == INT64_MIN && divisor == -1
* Fixed CPU edge case where ARM9 ALU ops would switch to Thumb even when they shouldn't
* Only clear the lowest bit of the jump address in ALU ops with rd==15 (on recommendation of RSDuck)
2021-02-19 23:58:41 +01:00
887ad27ed8
implement carry setting ALU op with imm
2020-07-25 22:08:43 +02:00
af31d25086
fix #672
2020-07-25 21:16:23 +02:00
83f8e11bc1
update copyright years
2020-02-14 20:18:08 +01:00
1b98a3e3a0
fix 'shift by register' operands: always only take the lower 8 bits of the register, fix handling for LSL/LSR >32
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fixes #479
2019-06-27 14:05:51 +02:00
b0efde8bf7
also, update copyright name
2019-01-22 15:58:29 +01:00
b6481a28ac
make nocashprint work from ARM code too.
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fixes #315
2018-12-31 20:58:58 +01:00
e7a4fe11ed
add nocashPrint type shit
2018-12-12 02:48:37 +01:00
172fb4876a
begin work on general timing renovation. way shitty because it behaves as if caches were off, so everything will be slow as shit.
2018-12-04 17:54:10 +01:00
fea7955675
fixor copyright years.
2018-09-15 02:32:13 +02:00
d50e7e4686
fix SMULWx/SMLAWx. fixes #78 , finally
2017-12-29 03:17:32 +01:00
49f8aec656
fix some shit
2017-06-13 17:44:35 +02:00
3499949129
* send undefined instructions to the proper exception handler
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* make ARM9-only instructions fail on ARM7
2017-06-13 15:09:39 +02:00
bbd251ddbc
fix QADD/QSUB/QDADD/QDSUB, those would write their result to the wrong register.
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also make them ARM9-only.
2017-06-13 11:17:22 +02:00
3a61ed0a91
allow crapoed THUMB hireg ADD/CMP/MOV
2017-03-31 02:20:29 +02:00
8a4ed8f41c
reorganize repo, move shit around
2017-03-16 23:01:22 +01:00
RSDuck