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fix 'shift by register' operands: always only take the lower 8 bits of the register, fix handling for LSL/LSR >32 

fixes #479
This commit is contained in:
Arisotura 2019-06-27 14:05:51 +02:00
parent 204b5d8700
commit 1b98a3e3a0
1 changed files with 5 additions and 5 deletions
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10
src/ARMInterpreter_ALU.cpp
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@ -106,12 +106,12 @@ namespace ARMInterpreter
x = ROR(x, (s&0x1F));
#define LSL_REG_S(x, s) \
if (s > 31) { cpu->SetC(x & (1<<0)); x = 0; } \
else if (s > 0) { cpu->SetC(x & (1<<(32-s))); x <<= s; }
if (s > 31) { cpu->SetC((s>32) ? 0 : (x & (1<<0))); x = 0; } \
else if (s > 0) { cpu->SetC(x & (1<<(32-s))); x <<= s; }
#define LSR_REG_S(x, s) \
if (s > 31) { cpu->SetC(x & (1<<31)); x = 0; } \
else if (s > 0) { cpu->SetC(x & (1<<(s-1))); x >>= s; }
if (s > 31) { cpu->SetC((s>32) ? 0 : (x & (1<<31))); x = 0; } \
else if (s > 0) { cpu->SetC(x & (1<<(s-1))); x >>= s; }
#define ASR_REG_S(x, s) \
if (s > 31) { cpu->SetC(x & (1<<31)); x = ((s32)x) >> 31; } \
@ -134,7 +134,7 @@ namespace ARMInterpreter
#define A_CALC_OP2_REG_SHIFT_REG(shiftop) \
u32 b = cpu->R[cpu->CurInstr&0xF]; \
if ((cpu->CurInstr&0xF)==15) b += 4; \
shiftop(b, cpu->R[(cpu->CurInstr>>8)&0xF]);
shiftop(b, (cpu->R[(cpu->CurInstr>>8)&0xF] & 0xFF));
#define A_IMPLEMENT_ALU_OP(x,s) \