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melonDS
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fix some shit

This commit is contained in:
StapleButter 2017-06-13 17:44:35 +02:00
parent 3499949129
commit 49f8aec656
3 changed files with 19 additions and 9 deletions
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10
src/ARMInterpreter.cpp
View File

@ -174,9 +174,14 @@ void A_MCR(ARM* cpu)
{
CP15::Write((cn<<8)|(cm<<4)|cpinfo, cpu->R[(cpu->CurInstr>>12)&0xF]);
}
else if (cpu->Num==1 && cp==14)
{
printf("MCR p14,%d,%d,%d on ARM7\n", cn, cm, cpinfo);
}
else
{
printf("bad MCR opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
return A_UNK(cpu); // TODO: check what kind of exception it really is
}
cpu->Cycles += 2; // TODO: checkme
@ -194,9 +199,14 @@ void A_MRC(ARM* cpu)
{
cpu->R[(cpu->CurInstr>>12)&0xF] = CP15::Read((cn<<8)|(cm<<4)|cpinfo);
}
else if (cpu->Num==1 && cp==14)
{
printf("MRC p14,%d,%d,%d on ARM7\n", cn, cm, cpinfo);
}
else
{
printf("bad MRC opcode p%d,%d,%d,%d on ARM%d\n", cp, cn, cm, cpinfo, cpu->Num?7:9);
return A_UNK(cpu); // TODO: check what kind of exception it really is
}
cpu->Cycles += 3; // TODO: checkme

10
src/ARMInterpreter_ALU.cpp
View File

@ -865,7 +865,7 @@ void A_SMLAL(ARM* cpu)
void A_SMLAxy(ARM* cpu)
{
if (cpu->Num != 0) return A_UNK(cpu);
if (cpu->Num != 0) return;
u32 rm = cpu->R[cpu->CurInstr & 0xF];
u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@ -886,7 +886,7 @@ void A_SMLAxy(ARM* cpu)
void A_SMLAWy(ARM* cpu)
{
if (cpu->Num != 0) return A_UNK(cpu);
if (cpu->Num != 0) return;
u32 rm = cpu->R[cpu->CurInstr & 0xF];
u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@ -905,7 +905,7 @@ void A_SMLAWy(ARM* cpu)
void A_SMULxy(ARM* cpu)
{
if (cpu->Num != 0) return A_UNK(cpu);
if (cpu->Num != 0) return;
u32 rm = cpu->R[cpu->CurInstr & 0xF];
u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@ -922,7 +922,7 @@ void A_SMULxy(ARM* cpu)
void A_SMULWy(ARM* cpu)
{
if (cpu->Num != 0) return A_UNK(cpu);
if (cpu->Num != 0) return;
u32 rm = cpu->R[cpu->CurInstr & 0xF];
u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];
@ -937,7 +937,7 @@ void A_SMULWy(ARM* cpu)
void A_SMLALxy(ARM* cpu)
{
if (cpu->Num != 0) return A_UNK(cpu);
if (cpu->Num != 0) return;
u32 rm = cpu->R[cpu->CurInstr & 0xF];
u32 rs = cpu->R[(cpu->CurInstr >> 8) & 0xF];

8
src/ARMInterpreter_LoadStore.cpp
View File

@ -220,7 +220,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
// TODO: CHECK LDRD/STRD TIMINGS!!
#define A_LDRD \
if (cpu->Num != 0) return A_UNK(cpu); \
if (cpu->Num != 0) return; \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
cpu->Cycles += 1; \
@ -229,7 +229,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
cpu->R[r+1] = cpu->DataRead32(offset+4); \
#define A_LDRD_POST \
if (cpu->Num != 0) return A_UNK(cpu); \
if (cpu->Num != 0) return; \
u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
cpu->Cycles += 1; \
@ -238,7 +238,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
cpu->R[r+1] = cpu->DataRead32(addr+4); \
#define A_STRD \
if (cpu->Num != 0) return A_UNK(cpu); \
if (cpu->Num != 0) return; \
offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
@ -246,7 +246,7 @@ A_IMPLEMENT_WB_LDRSTR(LDRB)
cpu->DataWrite32(offset+4, cpu->R[r+1]); \
#define A_STRD_POST \
if (cpu->Num != 0) return A_UNK(cpu); \
if (cpu->Num != 0) return; \
cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
u32 r = (cpu->CurInstr>>12) & 0xF; \
cpu->DataWrite32(offset , cpu->R[r ]); \