2017-01-18 00:33:06 +00:00
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/*
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Copyright 2016-2017 StapleButter
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include "NDS.h"
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#include "DMA.h"
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2017-01-22 19:34:59 +00:00
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#include "NDSCart.h"
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2017-01-18 00:33:06 +00:00
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// NOTES ON DMA SHIT
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//
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// * could use optimized code paths for common types of DMA transfers. for example, VRAM
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// * needs to eventually be made more accurate anyway. DMA isn't instant.
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DMA::DMA(u32 cpu, u32 num)
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{
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CPU = cpu;
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Num = num;
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Reset();
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}
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DMA::~DMA()
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{
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}
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void DMA::Reset()
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{
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SrcAddr = 0;
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DstAddr = 0;
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Cnt = 0;
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StartMode = 0;
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CurSrcAddr = 0;
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CurDstAddr = 0;
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RemCount = 0;
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SrcAddrInc = 0;
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DstAddrInc = 0;
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}
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void DMA::WriteCnt(u32 val)
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{
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u32 oldcnt = Cnt;
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Cnt = val;
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if ((!(oldcnt & 0x80000000)) && (val & 0x80000000))
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{
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CurSrcAddr = SrcAddr;
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CurDstAddr = DstAddr;
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2017-01-18 16:57:12 +00:00
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switch (Cnt & 0x00600000)
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2017-01-18 00:33:06 +00:00
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{
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case 0x00000000: DstAddrInc = 1; break;
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2017-01-18 16:57:12 +00:00
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case 0x00200000: DstAddrInc = -1; break;
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case 0x00400000: DstAddrInc = 0; break;
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case 0x00600000: DstAddrInc = 1; break;
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2017-01-18 00:33:06 +00:00
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}
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2017-01-18 16:57:12 +00:00
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switch (Cnt & 0x01800000)
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2017-01-18 00:33:06 +00:00
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{
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case 0x00000000: SrcAddrInc = 1; break;
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2017-01-18 16:57:12 +00:00
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case 0x00800000: SrcAddrInc = -1; break;
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case 0x01000000: SrcAddrInc = 0; break;
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case 0x01800000: SrcAddrInc = 1; printf("BAD DMA SRC INC MODE 3\n"); break;
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2017-01-18 00:33:06 +00:00
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}
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if (CPU == 0)
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StartMode = (Cnt >> 27) & 0x7;
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else
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2017-01-22 19:34:59 +00:00
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StartMode = ((Cnt >> 28) & 0x3) | 0x10;
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2017-01-18 00:33:06 +00:00
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if ((StartMode & 0x7) == 0)
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Start();
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2017-01-31 23:24:36 +00:00
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//else
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// printf("SPECIAL ARM%d DMA%d START MODE %02X\n", CPU?7:9, Num, StartMode);
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2017-01-18 00:33:06 +00:00
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}
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}
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void DMA::Start()
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{
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u32 countmask;
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if (CPU == 0)
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countmask = 0x001FFFFF;
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else
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countmask = (Num==3 ? 0x0000FFFF : 0x00003FFF);
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RemCount = Cnt & countmask;
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if (!RemCount)
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RemCount = countmask+1;
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if ((Cnt & 0x00060000) == 0x00060000)
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CurDstAddr = DstAddr;
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2017-01-22 19:34:59 +00:00
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// special path for cart DMA. this is a gross hack.
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// emulating it properly requires emulating cart transfer delays, so uh... TODO
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if (CurSrcAddr==0x04100010 && RemCount==1 && (Cnt & 0x07E00000)==0x07000000 &&
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((CPU==0 && StartMode==0x06) || (CPU==1 && StartMode==0x12)))
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{
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NDSCart::DMA(CurDstAddr);
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Cnt &= ~0x80000000;
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if (Cnt & 0x40000000)
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NDS::TriggerIRQ(CPU, NDS::IRQ_DMA0 + Num);
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return;
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}
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2017-01-20 14:13:44 +00:00
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//printf("ARM%d DMA%d %08X %08X->%08X %d bytes %dbit\n", CPU?7:9, Num, Cnt, CurSrcAddr, CurDstAddr, RemCount*((Cnt&0x04000000)?4:2), (Cnt&0x04000000)?32:16);
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2017-01-18 00:33:06 +00:00
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// TODO: NOT MAKE THE DMA INSTANT!!
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2017-01-18 16:57:12 +00:00
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if (!(Cnt & 0x04000000))
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2017-01-18 00:33:06 +00:00
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{
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u16 (*readfn)(u32) = CPU ? NDS::ARM7Read16 : NDS::ARM9Read16;
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void (*writefn)(u32,u16) = CPU ? NDS::ARM7Write16 : NDS::ARM9Write16;
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while (RemCount > 0)
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{
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writefn(CurDstAddr, readfn(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<1;
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CurDstAddr += DstAddrInc<<1;
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RemCount--;
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}
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}
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else
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{
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u32 (*readfn)(u32) = CPU ? NDS::ARM7Read32 : NDS::ARM9Read32;
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void (*writefn)(u32,u32) = CPU ? NDS::ARM7Write32 : NDS::ARM9Write32;
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while (RemCount > 0)
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{
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writefn(CurDstAddr, readfn(CurSrcAddr));
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CurSrcAddr += SrcAddrInc<<2;
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CurDstAddr += DstAddrInc<<2;
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RemCount--;
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}
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}
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if (!(Cnt & 0x02000000))
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Cnt &= ~0x80000000;
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if (Cnt & 0x40000000)
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NDS::TriggerIRQ(CPU, NDS::IRQ_DMA0 + Num);
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}
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