Commit Graph

64 Commits

Author SHA1 Message Date
Flyinghead 91b76f0c16 arm64 dynarec: missing edits 2019-01-22 18:40:36 +01:00
Flyinghead 75a04d6d28 arm64 dynarec: implement tail calling and block linking 2019-01-22 18:37:04 +01:00
Flyinghead a3682e7b22 arm64 dynarec: revert to non-explode spans and minor optimizations
Added some profiling
2019-01-21 12:54:29 +01:00
Flyinghead 573f285f3b arm64 dynarec: save x29 and x30 in ngen_mainloop prologue 2019-01-18 00:06:33 +01:00
Flyinghead cb8e81d473 arm64: direct memory access and jit rewrite
generates direct vmem read & write accesses
trap sigsegv and rewrite using slow path
add w29 to allocatable registers
get rid of literals and use pc-rel branching
minor optimizations and cleanup
2019-01-16 13:04:16 +01:00
Flyinghead c2a048e8d8 arm64: use explode_spans to allocate regs for V2 and F64 params 2019-01-15 08:47:07 +01:00
Flyinghead 523b110412 arm64: dynarec fixes 2019-01-13 11:32:28 +01:00
Flyinghead fc05727538 dynarecs clean-up
move GetRegPtr and ngen_FailedToFindBlock to sh4/dyna
2019-01-11 23:52:20 +01:00
Flyinghead e5ee48efa9 arm64: implement swaplb and pref. Various optimizations 2019-01-11 15:58:48 +01:00
Flyinghead 1c80207879 arm64: implement ftrv and frswap 2019-01-10 21:22:53 +01:00
Flyinghead 18a16f83ac arm64: more native opcodes implemented 2019-01-10 18:58:29 +01:00
Flyinghead a9a2aad8f6 arm64: use register spans allocation. Implement some opcodes natively 2019-01-09 16:35:23 +01:00
Flyinghead 3d8b01c515 arm64: Use x28 as sh4 regs base pointer. Reg cache to avoid fetches.
Block check optimization
2019-01-08 13:29:08 +01:00
Flyinghead 67a4eb8f1f arm64 dynarec using vixl 2019-01-07 21:50:46 +01:00