arm64 dynarec: revert to non-explode spans and minor optimizations
Added some profiling
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Flyinghead
parent
ac4fb796ca
commit
a3682e7b22
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@ -28,7 +28,7 @@
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#include "deps/vixl/aarch64/macro-assembler-aarch64.h"
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using namespace vixl::aarch64;
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#define EXPLODE_SPANS
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//#define EXPLODE_SPANS
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#include "hw/sh4/sh4_opcode_list.h"
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@ -54,7 +54,7 @@ struct DynaRBI : RuntimeBlockInfo
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};
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// Code borrowed from Dolphin https://github.com/dolphin-emu/dolphin
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static void CacheFlush(void* start, void* end)
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void Arm64CacheFlush(void* start, void* end)
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{
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if (start == end)
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return;
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@ -94,6 +94,26 @@ static void CacheFlush(void* start, void* end)
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#endif
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}
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double host_cpu_time;
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u64 guest_cpu_cycles;
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#ifdef PROFILING
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#include <time.h>
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static clock_t slice_start;
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extern "C"
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{
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static __attribute((used)) void start_slice()
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{
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slice_start = clock();
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}
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static __attribute((used)) void end_slice()
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{
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host_cpu_time += (double)(clock() - slice_start) / CLOCKS_PER_SEC;
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}
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}
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#endif
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void ngen_mainloop(void* v_cntx)
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{
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Sh4RCB* ctx = (Sh4RCB*)((u8*)v_cntx - sizeof(Sh4RCB));
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@ -105,11 +125,11 @@ void ngen_mainloop(void* v_cntx)
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"stp x23, x24, [sp, #32] \n\t"
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"stp x25, x26, [sp, #48] \n\t"
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"stp x27, x28, [sp, #64] \n\t"
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"stp x29, x30, [sp, #80] \n\t"
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"stp s14, s15, [sp, #80] \n\t"
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"stp s8, s9, [sp, #96] \n\t"
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"stp s10, s11, [sp, #112] \n\t"
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"stp s12, s13, [sp, #128] \n\t"
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"stp s14, s15, [sp, #144] \n\t"
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"stp x29, x30, [sp, #144] \n\t"
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// Use x28 as sh4 context pointer
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"mov x28, %0 \n\t"
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// Use x27 as cycle_counter
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@ -118,6 +138,9 @@ void ngen_mainloop(void* v_cntx)
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"run_loop: \n\t"
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"ldr w0, [x28, %[CpuRunning]] \n\t"
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"cbz w0, end_run_loop \n\t"
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#ifdef PROFILING
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"bl start_slice \n\t"
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#endif
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"slice_loop: \n\t"
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"ldr w0, [x28, %[pc]] \n\t"
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@ -127,15 +150,18 @@ void ngen_mainloop(void* v_cntx)
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"b.gt slice_loop \n\t"
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"add w27, w27, %[_SH4_TIMESLICE] \n\t"
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#ifdef PROFILING
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"bl end_slice \n\t"
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#endif
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"bl UpdateSystem_INTC \n\t"
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"b run_loop \n\t"
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"end_run_loop: \n\t"
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"ldp s14, s15, [sp, #144] \n\t"
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"ldp x29, x30, [sp, #144] \n\t"
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"ldp s12, s13, [sp, #128] \n\t"
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"ldp s10, s11, [sp, #112] \n\t"
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"ldp s8, s9, [sp, #96] \n\t"
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"ldp x29, x30, [sp, #80] \n\t"
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"ldp s14, s15, [sp, #80] \n\t"
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"ldp x27, x28, [sp, #64] \n\t"
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"ldp x25, x26, [sp, #48] \n\t"
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"ldp x23, x24, [sp, #32] \n\t"
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@ -260,6 +286,9 @@ public:
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void ngen_Compile(RuntimeBlockInfo* block, bool force_checks, bool reset, bool staging, bool optimise)
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{
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//printf("REC-ARM64 compiling %08x\n", block->addr);
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#ifdef PROFILING
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SaveFramePointer();
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#endif
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this->block = block;
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if (force_checks)
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CheckBlock(block);
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@ -269,7 +298,12 @@ public:
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// scheduler
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Sub(w27, w27, block->guest_cycles);
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#ifdef PROFILING
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Ldr(x11, (uintptr_t)&guest_cpu_cycles);
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Ldr(x0, MemOperand(x11));
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Add(x0, x0, block->guest_cycles);
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Str(x0, MemOperand(x11));
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#endif
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for (size_t i = 0; i < block->oplist.size(); i++)
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{
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shil_opcode& op = block->oplist[i];
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@ -352,11 +386,9 @@ public:
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break;
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case shop_swaplb:
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// TODO Optimize
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Mov(w9, Operand(regalloc.MapRegister(op.rs1), LSR, 16));
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Rev16(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rs1));
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Bfc(regalloc.MapRegister(op.rd), 16, 16);
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Orr(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rd), Operand(w9, LSL, 16));
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Bfi(regalloc.MapRegister(op.rd), w9, 16, 16);
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break;
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case shop_neg:
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@ -918,7 +950,7 @@ public:
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emit_Skip(block->host_code_size);
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}
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CacheFlush(GetBuffer()->GetStartAddress<void*>(), GetBuffer()->GetEndAddress<void*>());
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Arm64CacheFlush(GetBuffer()->GetStartAddress<void*>(), GetBuffer()->GetEndAddress<void*>());
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#if 0
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if (rewrite)
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{
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@ -944,7 +976,7 @@ private:
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void GenCallRuntime(R (*function)(P...))
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{
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SaveFramePointer();
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uintptr_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>();
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ptrdiff_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>();
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Label function_label;
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BindToOffset(&function_label, offset);
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Bl(&function_label);
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@ -1368,16 +1400,16 @@ void Arm64RegAlloc::Writeback_FPU(u32 reg, eFReg nreg)
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extern "C" void do_sqw_nommu_area_3(u32 dst, u8* sqb)
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{
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__asm__ volatile
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__asm__
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(
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"and x12, x0, #0x20 \n\t" // SQ# selection, isolate
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"add x12, x12, x1 \n\t" // SQ# selection, add to SQ ptr
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"ld2 { v0.2D, v1.2D }, [x12]\n\t"
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"movz x11, #0x0C00, lsl #16 \n\t"
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"add x11, x1, x11 \n\t" // get ram ptr from x1, part 1
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"and x12, x0, #0x20 \n\t" // SQ# selection, isolate
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"ubfx x0, x0, #5, #20 \n\t" // get ram offset
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"add x1, x12, x1 \n\t" // SQ# selection, add to SQ ptr
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"add x11, x11, #512 \n\t" // get ram ptr from x1, part 2
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"add x11, x11, x0, lsl #5 \n\t" // ram + offset
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"ld2 { v0.2D, v1.2D }, [x1] \n\t"
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"st2 { v0.2D, v1.2D }, [x11] \n\t"
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"ret \n"
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