arm64 dynarec: implement tail calling and block linking
This commit is contained in:
Flyinghead
parent
eb37dacadb
commit
75a04d6d28
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@ -34,7 +34,7 @@ enum eFReg {
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S17, S18, S19, S20, S21, S22, S23, S24, S25, S26, S27, S28, S29, S30, S31
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};
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static eReg alloc_regs[] = { W19, W20, W21, W22, W23, W24, W25, W26, W29, (eReg)-1 };
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static eReg alloc_regs[] = { W19, W20, W21, W22, W23, W24, W25, W26, (eReg)-1 };
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static eFReg alloc_fregs[] = { S8, S9, S10, S11, S12, S13, S14, S15, (eFReg)-1 };
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class Arm64Assembler;
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@ -42,13 +42,21 @@ using namespace vixl::aarch64;
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#undef do_sqw_nommu
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extern "C" void no_update();
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extern "C" void intc_sched();
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extern "C" void ngen_blockcheckfail(u32 pc);
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extern "C" void ngen_LinkBlock_Generic_stub();
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extern "C" void ngen_LinkBlock_cond_Branch_stub();
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extern "C" void ngen_LinkBlock_cond_Next_stub();
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extern "C" void ngen_FailedToFindBlock_();
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struct DynaRBI : RuntimeBlockInfo
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{
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virtual u32 Relink() {
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return 0;
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}
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virtual u32 Relink() override;
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virtual void Relocate(void* dst) {
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virtual void Relocate(void* dst) override {
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verify(false);
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}
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};
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@ -114,11 +122,53 @@ static __attribute((used)) void end_slice()
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}
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#endif
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__asm__
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(
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".hidden ngen_LinkBlock_cond_Branch_stub \n\t"
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".globl ngen_LinkBlock_cond_Branch_stub \n\t"
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"ngen_LinkBlock_cond_Branch_stub: \n\t"
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"mov w1, #1 \n\t"
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"b ngen_LinkBlock_Shared_stub \n"
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".hidden ngen_LinkBlock_cond_Next_stub \n\t"
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".globl ngen_LinkBlock_cond_Next_stub \n\t"
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"ngen_LinkBlock_cond_Next_stub: \n\t"
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"mov w1, #0 \n\t"
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"b ngen_LinkBlock_Shared_stub \n"
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".hidden ngen_LinkBlock_Generic_stub \n\t"
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".globl ngen_LinkBlock_Generic_stub \n\t"
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"ngen_LinkBlock_Generic_stub: \n\t"
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"mov w1, w29 \n\t" // djump/pc -> in case we need it ..
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//"b ngen_LinkBlock_Shared_stub \n"
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".hidden ngen_LinkBlock_Shared_stub \n\t"
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".globl ngen_LinkBlock_Shared_stub \n\t"
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"ngen_LinkBlock_Shared_stub: \n\t"
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"mov x0, lr \n\t"
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"sub x0, x0, #4 \n\t" // go before the call
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"bl rdv_LinkBlock \n\t"
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"br x0 \n"
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".hidden ngen_FailedToFindBlock_ \n\t"
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".globl ngen_FailedToFindBlock_ \n\t"
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"ngen_FailedToFindBlock_: \n\t"
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"mov w0, w29 \n\t"
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"bl rdv_FailedToFindBlock \n\t"
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"br x0 \n"
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".hidden ngen_blockcheckfail \n\t"
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".globl ngen_blockcheckfail \n\t"
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"ngen_blockcheckfail: \n\t"
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"bl rdv_BlockCheckFail \n\t"
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"br x0 \n"
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);
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void ngen_mainloop(void* v_cntx)
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{
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Sh4RCB* ctx = (Sh4RCB*)((u8*)v_cntx - sizeof(Sh4RCB));
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__asm__ volatile
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__asm__
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(
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"stp x19, x20, [sp, #-160]! \n\t"
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"stp x21, x22, [sp, #16] \n\t"
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@ -131,32 +181,48 @@ void ngen_mainloop(void* v_cntx)
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"stp s12, s13, [sp, #128] \n\t"
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"stp x29, x30, [sp, #144] \n\t"
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// Use x28 as sh4 context pointer
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"mov x28, %0 \n\t"
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"mov x28, %[cntx] \n\t"
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// Use x27 as cycle_counter
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"mov w27, %[_SH4_TIMESLICE] \n\t"
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// w29 is next_pc
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"ldr w29, [x28, %[pc]] \n\t"
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"b no_update \n"
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"run_loop: \n\t"
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"ldr w0, [x28, %[CpuRunning]] \n\t"
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"cbz w0, end_run_loop \n\t"
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#ifdef PROFILING
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"bl start_slice \n\t"
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#endif
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"slice_loop: \n\t"
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"ldr w0, [x28, %[pc]] \n\t"
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"bl bm_GetCode2 \n\t"
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"blr x0 \n\t"
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"cmp w27, #0 \n\t"
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"b.gt slice_loop \n\t"
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".hidden intc_sched \n\t"
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".globl intc_sched \n\t"
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"intc_sched: \n\t"
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"add w27, w27, %[_SH4_TIMESLICE] \n\t"
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#ifdef PROFILING
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"bl end_slice \n\t"
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#endif
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"bl UpdateSystem_INTC \n\t"
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"b run_loop \n\t"
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"mov x29, lr \n\r" // Trashing pc here but it will be reset at the end of the block or in DoInterrupts
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"bl UpdateSystem \n\t"
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"mov lr, x29 \n\t"
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"cbnz w0, .do_interrupts \n\t"
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"ret \n"
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"end_run_loop: \n\t"
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".do_interrupts: \n\t"
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"mov x0, x29 \n\t"
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"bl rdv_DoInterrupts \n\t" // Updates next_pc based on host pc
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"mov w29, w0 \n"
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".hidden no_update \n\t"
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".globl no_update \n\t"
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"no_update: \n\t" // next_pc _MUST_ be on w29
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"ldr w0, [x28, %[CpuRunning]] \n\t"
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"cbz w0, .end_mainloop \n\t"
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"movz x2, %[RCB_SIZE], lsl #16 \n\t"
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"sub x2, x28, x2 \n\t"
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"add x2, x2, %[SH4CTX_SIZE] \n\t"
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#if RAM_SIZE == 33554432
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"ubfx w1, w29, #1, #24 \n\t"
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#elif RAM_SIZE == 16777216
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"ubfx w1, w29, #1, #23 \n\t"
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#else
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#error "Define RAM_SIZE"
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#endif
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"ldr x0, [x2, x1, lsl #3] \n\t"
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"br x0 \n"
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".end_mainloop: \n\t"
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"ldp x29, x30, [sp, #144] \n\t"
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"ldp s12, s13, [sp, #128] \n\t"
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"ldp s10, s11, [sp, #112] \n\t"
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@ -167,17 +233,20 @@ void ngen_mainloop(void* v_cntx)
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"ldp x23, x24, [sp, #32] \n\t"
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"ldp x21, x22, [sp, #16] \n\t"
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"ldp x19, x20, [sp], #160 \n\t"
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:
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: [cntx] "r"(reinterpret_cast<uintptr_t>(&ctx->cntx)),
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[pc] "i"(offsetof(Sh4Context, pc)),
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[_SH4_TIMESLICE] "i"(SH4_TIMESLICE),
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[CpuRunning] "i"(offsetof(Sh4Context, CpuRunning))
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: "memory"
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:
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: [cntx] "r"(reinterpret_cast<uintptr_t>(&ctx->cntx)),
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[pc] "i"(offsetof(Sh4Context, pc)),
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[_SH4_TIMESLICE] "i"(SH4_TIMESLICE),
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[CpuRunning] "i"(offsetof(Sh4Context, CpuRunning)),
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[RCB_SIZE] "i" (sizeof(Sh4RCB) >> 16),
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[SH4CTX_SIZE] "i" (sizeof(Sh4Context))
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: "memory"
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);
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}
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void ngen_init()
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{
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ngen_FailedToFindBlock = &ngen_FailedToFindBlock_;
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}
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void ngen_ResetBlocks()
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@ -195,11 +264,6 @@ RuntimeBlockInfo* ngen_AllocateBlock()
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return new DynaRBI();
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}
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static void ngen_blockcheckfail(u32 pc) {
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printf("arm64 JIT: SMC invalidation at %08X\n", pc);
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rdv_BlockCheckFail(pc);
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}
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class Arm64Assembler : public MacroAssembler
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{
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typedef void (MacroAssembler::*Arm64Op_RRO)(const Register&, const Register&, const Operand&);
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@ -297,7 +361,12 @@ public:
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regalloc.DoAlloc(block);
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// scheduler
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Sub(w27, w27, block->guest_cycles);
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Subs(w27, w27, block->guest_cycles);
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Label cycles_remaining;
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B(&cycles_remaining, pl);
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GenCallRuntime(intc_sched);
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Bind(&cycles_remaining);
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#ifdef PROFILING
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Ldr(x11, (uintptr_t)&guest_cpu_cycles);
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Ldr(x0, MemOperand(x11));
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@ -325,12 +394,11 @@ public:
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case shop_jcond:
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case shop_jdyn:
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if (op.rs2.is_imm())
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{
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Add(w10, regalloc.MapRegister(op.rs1), op.rs2._imm);
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Mov(regalloc.MapRegister(op.rd), w10);
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}
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Add(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rs1), op.rs2._imm);
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else
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Mov(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rs1));
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// Save it for the branching at the end of the block
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Mov(w29, regalloc.MapRegister(op.rd));
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break;
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case shop_mov32:
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@ -450,9 +518,9 @@ public:
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break;
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case shop_rocr:
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Ubfm(w0, regalloc.MapRegister(op.rs1), 0, 0); // w0 = rs1[0]
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Ubfx(w0, regalloc.MapRegister(op.rs1), 0, 1); // w0 = rs1[0] (new C)
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Mov(regalloc.MapRegister(op.rd), Operand(regalloc.MapRegister(op.rs1), LSR, 1)); // rd = rs1 >> 1
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Orr(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rd), Operand(regalloc.MapRegister(op.rs2), LSL, 31)); // rd |= C << 31
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Bfi(regalloc.MapRegister(op.rd), regalloc.MapRegister(op.rs2), 31, 1); // rd |= C << 31
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Mov(regalloc.MapRegister(op.rd2), w0); // rd2 = w0 (new C)
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break;
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case shop_rocl:
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@ -694,73 +762,10 @@ public:
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regalloc.OpEnd(&op);
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}
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switch (block->BlockType)
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{
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block->relink_offset = (u32)GetBuffer()->GetCursorOffset();
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block->relink_data = 0;
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case BET_StaticJump:
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case BET_StaticCall:
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// next_pc = block->BranchBlock;
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Ldr(w10, block->BranchBlock);
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Str(w10, sh4_context_mem_operand(&next_pc));
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break;
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case BET_Cond_0:
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case BET_Cond_1:
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{
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// next_pc = next_pc_value;
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// if (*jdyn == 0)
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// next_pc = branch_pc_value;
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Mov(w10, block->NextBlock);
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if (block->has_jcond)
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Ldr(w11, sh4_context_mem_operand(&Sh4cntx.jdyn));
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else
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Ldr(w11, sh4_context_mem_operand(&sr.T));
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Cmp(w11, block->BlockType & 1);
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Label branch_not_taken;
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B(ne, &branch_not_taken);
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Mov(w10, block->BranchBlock);
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Bind(&branch_not_taken);
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Str(w10, sh4_context_mem_operand(&next_pc));
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}
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break;
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case BET_DynamicJump:
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case BET_DynamicCall:
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case BET_DynamicRet:
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// next_pc = *jdyn;
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Ldr(w10, sh4_context_mem_operand(&Sh4cntx.jdyn));
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Str(w10, sh4_context_mem_operand(&next_pc));
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break;
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case BET_DynamicIntr:
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case BET_StaticIntr:
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if (block->BlockType == BET_DynamicIntr)
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{
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// next_pc = *jdyn;
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Ldr(w10, sh4_context_mem_operand(&Sh4cntx.jdyn));
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}
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else
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{
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// next_pc = next_pc_value;
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Mov(w10, block->NextBlock);
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}
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Str(w10, sh4_context_mem_operand(&next_pc));
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GenCallRuntime(UpdateINTC);
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break;
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default:
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die("Invalid block end type");
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}
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if (frame_reg_saved)
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Ldr(x30, MemOperand(sp, 16, PostIndex));
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Ret();
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RelinkBlock(block);
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Finalize();
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}
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@ -935,6 +940,96 @@ public:
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frame_reg_saved = true;
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}
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u32 RelinkBlock(RuntimeBlockInfo *block)
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{
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ptrdiff_t start_offset = GetBuffer()->GetCursorOffset();
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switch (block->BlockType)
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{
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case BET_StaticJump:
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case BET_StaticCall:
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// next_pc = block->BranchBlock;
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if (block->pBranchBlock == NULL)
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GenCallRuntime(ngen_LinkBlock_Generic_stub);
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else
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GenBranch(block->pBranchBlock->code);
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break;
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case BET_Cond_0:
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case BET_Cond_1:
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{
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// next_pc = next_pc_value;
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// if (*jdyn == 0)
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// next_pc = branch_pc_value;
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if (block->has_jcond)
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Ldr(w11, sh4_context_mem_operand(&Sh4cntx.jdyn));
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else
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Ldr(w11, sh4_context_mem_operand(&sr.T));
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Cmp(w11, block->BlockType & 1);
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Label branch_not_taken;
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B(ne, &branch_not_taken);
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if (block->pBranchBlock != NULL)
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GenBranch(block->pBranchBlock->code);
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else
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GenCallRuntime(ngen_LinkBlock_cond_Branch_stub);
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Bind(&branch_not_taken);
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if (block->pNextBlock != NULL)
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GenBranch(block->pNextBlock->code);
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else
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GenCallRuntime(ngen_LinkBlock_cond_Next_stub);
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}
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break;
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case BET_DynamicJump:
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case BET_DynamicCall:
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case BET_DynamicRet:
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// next_pc = *jdyn;
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Str(w29, sh4_context_mem_operand(&next_pc));
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// TODO Call no_update instead (and check CpuRunning less frequently?)
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Mov(x2, sizeof(Sh4RCB));
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Sub(x2, x28, x2);
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Add(x2, x2, sizeof(Sh4Context)); // x2 now points to FPCB
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#if RAM_SIZE == 33554432
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Ubfx(w1, w29, 1, 24);
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#else
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Ubfx(w1, w29, 1, 23);
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#endif
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Ldr(x15, MemOperand(x2, x1, LSL, 3)); // Get block entry point
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Br(x15);
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break;
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case BET_DynamicIntr:
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case BET_StaticIntr:
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if (block->BlockType == BET_StaticIntr)
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// next_pc = next_pc_value;
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Mov(w29, block->NextBlock);
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// else next_pc = *jdyn (already in w29)
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Str(w29, sh4_context_mem_operand(&next_pc));
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GenCallRuntime(UpdateINTC);
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Ldr(w29, sh4_context_mem_operand(&next_pc));
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GenBranch(no_update);
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break;
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default:
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die("Invalid block end type");
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}
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return GetBuffer()->GetCursorOffset() - start_offset;
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}
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void Finalize(bool rewrite = false)
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{
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Label code_end;
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@ -952,11 +1047,11 @@ public:
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}
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Arm64CacheFlush(GetBuffer()->GetStartAddress<void*>(), GetBuffer()->GetEndAddress<void*>());
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#if 0
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if (rewrite)
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// if (rewrite)
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{
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Instruction* instr_start = GetBuffer()->GetStartAddress<Instruction*>();
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Instruction* instr_end = GetLabelAddress<Instruction*>(&code_end);
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// Instruction* instr_end = (Instruction*)((u8 *)block->code + block->host_code_size);
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Instruction* instr_start = (Instruction*)block->code;
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// Instruction* instr_end = GetLabelAddress<Instruction*>(&code_end);
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Instruction* instr_end = (Instruction*)((u8 *)block->code + block->host_code_size);
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Decoder decoder;
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Disassembler disasm;
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decoder.AppendVisitor(&disasm);
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@ -977,11 +1072,27 @@ private:
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{
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SaveFramePointer();
|
||||
ptrdiff_t offset = reinterpret_cast<uintptr_t>(function) - GetBuffer()->GetStartAddress<uintptr_t>();
|
||||
verify(offset >= -128 * 1024 * 1024 && offset <= 128 * 1024 * 1024);
|
||||
verify((offset & 3) == 0);
|
||||
Label function_label;
|
||||
BindToOffset(&function_label, offset);
|
||||
Bl(&function_label);
|
||||
}
|
||||
|
||||
template <typename R, typename... P>
|
||||
void GenBranch(R (*code)(P...), Condition cond = al)
|
||||
{
|
||||
ptrdiff_t offset = reinterpret_cast<uintptr_t>(code) - GetBuffer()->GetStartAddress<uintptr_t>();
|
||||
verify(offset >= -128 * 1024 * 1024 && offset < 128 * 1024 * 1024);
|
||||
verify((offset & 3) == 0);
|
||||
Label code_label;
|
||||
BindToOffset(&code_label, offset);
|
||||
if (cond == al)
|
||||
B(&code_label);
|
||||
else
|
||||
B(&code_label, cond);
|
||||
}
|
||||
|
||||
void GenReadMemory(const shil_opcode& op, size_t opid)
|
||||
{
|
||||
u32 size = op.flags & 0x7f;
|
||||
|
|
@ -989,8 +1100,6 @@ private:
|
|||
if (GenReadMemoryImmediate(op))
|
||||
return;
|
||||
|
||||
SaveFramePointer(); // needed if rewritten
|
||||
|
||||
GenMemAddr(op, call_regs[0]);
|
||||
|
||||
if (GenReadMemoryFast(op, opid))
|
||||
|
|
@ -1121,8 +1230,6 @@ private:
|
|||
|
||||
void GenWriteMemory(const shil_opcode& op, size_t opid)
|
||||
{
|
||||
SaveFramePointer(); // needed if rewritten
|
||||
|
||||
GenMemAddr(op, call_regs[0]);
|
||||
|
||||
u32 size = op.flags & 0x7f;
|
||||
|
|
@ -1287,15 +1394,6 @@ private:
|
|||
}
|
||||
}
|
||||
|
||||
void SaveFramePointer()
|
||||
{
|
||||
if (!frame_reg_saved)
|
||||
{
|
||||
Str(x30, MemOperand(sp, -16, PreIndex));
|
||||
frame_reg_saved = true;
|
||||
}
|
||||
}
|
||||
|
||||
struct CC_PS
|
||||
{
|
||||
CanonicalParamType type;
|
||||
|
|
@ -1306,7 +1404,6 @@ private:
|
|||
std::vector<const XRegister*> call_regs64;
|
||||
std::vector<const VRegister*> call_fregs;
|
||||
Arm64RegAlloc regalloc;
|
||||
bool frame_reg_saved = false;
|
||||
RuntimeBlockInfo* block;
|
||||
const int read_memory_rewrite_size = 6; // worst case for u64: add, bfc, ldr, fmov, lsr, fmov
|
||||
// FIXME rewrite size per read/write size?
|
||||
|
|
@ -1349,12 +1446,11 @@ void ngen_CC_Finish(shil_opcode* op)
|
|||
|
||||
bool ngen_Rewrite(unat& host_pc, unat, unat)
|
||||
{
|
||||
u32 guest_pc = p_sh4rcb->cntx.pc;
|
||||
//printf("ngen_Rewrite pc %p code addr %08x\n", host_pc, guest_pc);
|
||||
RuntimeBlockInfo *block = bm_GetBlock(guest_pc);
|
||||
//printf("ngen_Rewrite pc %p\n", host_pc);
|
||||
RuntimeBlockInfo *block = bm_GetBlock((void *)host_pc);
|
||||
if (block == NULL)
|
||||
{
|
||||
printf("ngen_Rewrite: Block at %08x not found\n", guest_pc);
|
||||
printf("ngen_Rewrite: Block at %p not found\n", (void *)host_pc);
|
||||
return false;
|
||||
}
|
||||
u32 *code_ptr = (u32*)host_pc;
|
||||
|
|
@ -1380,6 +1476,18 @@ bool ngen_Rewrite(unat& host_pc, unat, unat)
|
|||
return true;
|
||||
}
|
||||
|
||||
u32 DynaRBI::Relink()
|
||||
{
|
||||
//printf("DynaRBI::Relink %08x\n", this->addr);
|
||||
Arm64Assembler *compiler = new Arm64Assembler((u8 *)this->code + this->relink_offset);
|
||||
|
||||
u32 code_size = compiler->RelinkBlock(this);
|
||||
compiler->Finalize(true);
|
||||
delete compiler;
|
||||
|
||||
return code_size;
|
||||
}
|
||||
|
||||
void Arm64RegAlloc::Preload(u32 reg, eReg nreg)
|
||||
{
|
||||
assembler->Ldr(Register(nreg, 32), assembler->sh4_context_mem_operand(GetRegPtr(reg)));
|
||||
|
|
|
|||
Loading…
Reference in New Issue