Pokechu22
5bf59f3ce4
docs/DSP: A failed RETcc only inceases PC by 1, not 2
...
This is because RETcc is a single-word instruction.
2021-08-21 17:07:14 -07:00
Pokechu22
1b84721b7f
docs/DSP: Add RTIcc
2021-08-21 17:07:14 -07:00
Pokechu22
5611bd8f23
docs/DSP: Change conditional names to match Dolphin
2021-08-21 17:07:14 -07:00
Pokechu22
af10eab938
docs/DSP: Split SRSH from SRS
2021-08-21 17:07:14 -07:00
Pokechu22
408623b6e9
docs/DSP: Document behavior of LRS/SRS/SI with CR
2021-08-21 17:07:14 -07:00
Pokechu22
8fa649e1d6
docs/DSP: Document masking/sign extension behavior of registers
2021-08-21 17:07:14 -07:00
Pokechu22
7c645e1865
docs/DSP: Fix registers used by MOVAX and MOV
2021-08-21 17:07:14 -07:00
Pokechu22
be753e5a45
docs/DSP: MADDC operates on acS.m, not acS.l
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This matches the prose and Dolphin's implementation.
2021-08-21 17:07:13 -07:00
Pokechu22
0796fada17
docs/DSP: Add information about flags for every instruction
2021-08-21 17:07:13 -07:00
Pokechu22
9249454f33
docs/DSP: Document overflow and carry behavior
2021-08-21 17:07:13 -07:00
Pokechu22
a8ec0ad27f
docs/DSP: Fix MULXAC bytes
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The previous encoding was for MULXMVZ.
2021-08-21 16:05:06 -07:00
Pokechu22
2db2683ea9
docs/DSP: Fix 'S format
2021-08-21 16:05:06 -07:00
Pokechu22
139e05800f
docs/DSP: Fix 'LS encoding
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The old encoding was a copy of 'LN.
2021-08-21 16:05:06 -07:00
Pokechu22
8767df40e5
docs/DSP: Fix acD/acR conflation in shift instructions
2021-08-21 16:05:06 -07:00
Pokechu22
332bb6fd55
docs/DSP: Fix operation for LSR/ASR
2021-08-21 16:05:06 -07:00
Pokechu22
2eb791d5e1
docs/DSP: Note that ADDAXL is unsigned
2021-08-21 16:05:06 -07:00
Pokechu22
953670b057
docs/DSP: Fix operation of ADDR and SUBR
2021-08-21 16:05:06 -07:00
Pokechu22
8881ecef19
docs/DSP: Adjust operation for CMPI and CMPIS
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This more clearly indicates what it is supposed to do.
2021-08-21 16:05:06 -07:00
Pokechu22
79664d419c
docs/DSP: Document rounding behavior of CLRL
2021-08-21 16:05:06 -07:00
Pokechu22
1bcea561e9
docs/DSP: Add 'NOP
2021-08-21 16:05:05 -07:00
Pokechu22
29b61d463e
docs/DSP: Document 'LD and 'LDAX
2021-08-21 16:05:05 -07:00
Pokechu22
031621bf51
docs/DSP: Document behavior and instructions when the first nybble is 3
2021-08-21 16:05:05 -07:00
Pokechu22
211c2b5d99
docs/DSP: Add most missing instructions
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These instructions were already implememented by Dolphin, but never added to the manual. Extension instructions will be handled in a later commit, as wlil instructions that were not previously implememented by Dolphin.
2021-08-21 16:05:05 -07:00
Pokechu22
446b1d2f13
docs/DSP: Adjust bit names in opcode table
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The old names did not match the ones used by the instructions themselves, and were generally fairly inconsistent.
2021-08-21 16:05:05 -07:00
Pokechu22
16da6e214d
docs/DSP: Hyperlink opcode names
2021-08-21 16:05:03 -07:00
Pokechu22
ccc5085988
docs/DSP: Rename 'SLMN to 'SLNM
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This is for consistency with Dolphin, the opcode table, and 'LSNM.
2021-08-21 16:03:50 -07:00
Pokechu22
2a9e1a3b5d
docs/DSP: Document accelerator hardware registers
2021-08-21 16:03:50 -07:00
Pokechu22
c9ed9dd0a7
docs/DSP: Adjust formatting of RegisterBitOverview
2021-08-21 16:03:50 -07:00
Pokechu22
9a269929ec
docs/DSP: Improve DMA hardware register information
2021-08-21 16:03:50 -07:00
Pokechu22
b99fbf7e9c
docs/DSP: Sort hardware registers by address
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The actual documentation for registers is not changed in this commit; nor are any new registers added. This is purely to make later diffs more readable.
2021-08-21 16:03:50 -07:00
Pokechu22
6df892dca7
docs/DSP: Expand DSP Memory Map section
2021-08-21 16:03:50 -07:00
Pokechu22
cfc6de8545
docs/DSP: Fix LOOPI, BLOOP, Jcc, and CALLcc opcode table operands
2021-08-21 16:03:50 -07:00
Pokechu22
5a0155a1cb
docs/DSP: Fix ANDCF and ANDF being swapped
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This was implemented in Dolphin in 7c4e654253
. That change also noted that JZR/JNZ were swapped; this was already fixed in facd1dca12
.
2021-08-21 16:03:50 -07:00
Pokechu22
000f7b102a
docs/DSP: Fix SBCLR and SBSET being backwards
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Dolphin has them with SBCLR as 1200 and SBSET as 1300 since the inital megacommit: 775dc8a9c0/Source/Plugins/Plugin_DSP_LLE/Src/opcodes.cpp (L67-L68)
2021-08-21 16:03:49 -07:00
Pokechu22
13051ee291
docs/DSP: Elaborate on SBSET and SBCLR
2021-08-21 16:03:49 -07:00
Pokechu22
bb1ecd2a81
docs/DSP: Add RTI to opcode list
2021-08-21 16:03:41 -07:00
Pokechu22
2c73de7ada
docs/DSP: Add missing already-documented instructions to opcode table
2021-08-21 11:40:54 -07:00
Pokechu22
d9f8df3cbe
docs/DSP: Fix typo in HALT encoding
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"I think I saw a two"
2021-08-21 11:40:54 -07:00
Pokechu22
35720284f3
docs/DSP: Fix various spelling/grammar/punctuation issues
2021-08-21 11:40:54 -07:00
Pokechu22
2df33ddbbc
docs/DSP: Create .gitignore
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This is from https://github.com/github/gitignore/blob/master/TeX.gitignore (CC0)
2021-08-21 11:40:54 -07:00
Pokechu22
c1242fbd6c
docs/DSP: Update version and history
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The GFDL requires the history section to be updated. Although there was no actual release, this makes it attribution clearer and separates it from my changes.
2021-08-21 11:40:22 -07:00
Dentomologist
87924f2ddd
DolphinQt: Remove Windows dialog help buttons
2021-08-21 10:53:12 -07:00
Mai M
17a01c894b
Merge pull request #10044 from AdmiralCurtiss/invalidate-icache-lines-fix
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PowerPC: Fix for calling InvalidateICacheLines() with a count of 1 causing a (harmless) second invalidation.
2021-08-19 19:23:11 -04:00
JosJuice
90fcaf7e96
Jit: Use one less register in dcbx
...
We were using a "value" register to avoid clobbering physical_addr,
but this isn't actually needed anymore. The only bits we need from
physical_addr after we start clobbering it are bits 5-9, and
those bits are identical in effective_addr and physical_addr,
so we can read them from effective_addr instead.
2021-08-19 23:26:11 +02:00
Admiral H. Curtiss
f5cd17925a
PowerPC: Fix for calling InvalidateICacheLines() with a count of 1 causing a (harmless) second invalidation.
2021-08-19 22:54:34 +02:00
Tilka
3aaab25810
Merge pull request #10032 from Pokechu22/dsp-lle-masks
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DSP masking and sign extension fixes
2021-08-18 20:20:31 +01:00
JosJuice
4f09c320e8
Interpreter: Simplify mcrfs implementation
2021-08-18 18:18:19 +02:00
Lioncash
b7b45eb111
Interpreter: Make signedness and narrowing conversions explicit
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Makes our conversions between the different signs explicit to indicate
that they're intentional and also silences compiler warnings when
compiling with sign conversion or stricter truncation warnings enabled.
2021-08-18 09:56:00 -04:00
Mai M
33154de614
Merge pull request #10039 from OatmealDome/spdx-leftovers
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Fix some missed items from SPDX transition
2021-08-17 23:02:32 -04:00
Mai M
6863b7ae9e
Merge pull request #10036 from JosJuice/jitarm64-psq-x
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JitArm64: Implement indexed paired loadstore instructions
2021-08-17 23:00:57 -04:00