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docs/DSP: Elaborate on SBSET and SBCLR

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Pokechu22 2021-07-15 11:30:37 -07:00
parent bb1ecd2a81
commit 13051ee291
1 changed files with 4 additions and 4 deletions
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8
docs/DSP/GameCube_DSP_Users_Manual/GameCube_DSP_Users_Manual.tex
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@ -2921,11 +2921,11 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a
\end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription}
\item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}.
\item Set bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be set with this instruction.
\end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation}
$sr |= (I + 6)
$sr |= 1 << (I + 6)
$pc++
\end{DSPOpcodeOperation}
\end{DSPOpcode}
@ -2940,11 +2940,11 @@ There are two pairs of conditions that work similarly: \texttt{EQ}/\texttt{NE} a
\end{DSPOpcodeFormat}
\begin{DSPOpcodeDescription}
\item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}.
\item Clear bit of status register \Register{\$sr}. Bit number is calculated by adding 6 to immediate value \Value{I}; thus, bits 6 through 13 (\texttt{LZ} through \texttt{AM}) can be cleared with this instruction.
\end{DSPOpcodeDescription}
\begin{DSPOpcodeOperation}
$sr &= ~(I + 6)
$sr &= ~(1 << (I + 6))
$pc++
\end{DSPOpcodeOperation}
\end{DSPOpcode}