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78 Commits

Author SHA1 Message Date
JosJuice 9ad4f724e4 Arm64Emitter: Use ORR in MOVI2R 2021-02-13 21:04:13 +01:00
JosJuice 0d5ed06daf Arm64Emitter: Improve MOVI2R 
More or less a complete rewrite of the function which aims
to be equally good or better for each given input, without
relying on special cases like the old implementation did.

In particular, we now have more extensive support for
MOVN, as mentioned in a TODO comment.
 2021-02-13 20:23:03 +01:00
JosJuice 4e107935ac Arm64Emitter: Allow specifying 21th bit of ADRP imm 2021-02-13 11:33:27 +01:00
JosJuice d226b8f825 Arm64Emitter: Remove optimize parameter from MOVI2R 
I don't really see the use of this. (Maybe in the past it
was used for when we need a constant number of instructions
for backpatching? But we don't use MOVI2R for that now.)
 2021-02-13 11:33:27 +01:00
JosJuice efeda3b759 JitArm64: More constant propagation optimizations 
PR 9262 added a bunch of Jit64 optimizations, some of
which were already in JitArm64 and some which weren't.
This change ports the latter ones to JitArm64.
 2021-02-07 13:55:35 +01:00
MerryMage be6aec9932 Arm64Emitter: Add BFXIL 2021-01-31 12:04:57 +00:00
JosJuice 67491979ab JitArm64: Avoid using X30 with BLR 
At least on some CPUs (I found out about this from the
Arm Cortex-A76 Software Optimization Guide), using X30
with BLR is one cycle slower than using another register.
 2021-01-23 10:32:44 +01:00
Dentomologist e3237661ec Arm64Emitter: Convert ShiftType to enum class 2021-01-17 16:21:38 -08:00
Dentomologist 70c54065ab Arm64Emitter: Convert IndexType to enum class 2021-01-15 23:27:11 -08:00
Lioncash 36af39853d Arm64Emitter: Remove unused OpType enum 
This isn't used anywhere, so we can remove it.
 2021-01-01 11:06:05 -05:00
Lioncash 95cc53edec Arm64Emitter: Convert ArithOption enums into enum classes 
Makes the enums strongly typed. While we're at it, we can also make
these enums private.
 2021-01-01 07:10:41 -05:00
Lioncash cca0dffebd Arm64Emitter: Add shorthand member functions for hint instructions 
Allows for more concise code.
 2020-12-30 20:49:20 -05:00
Lioncash 6046a15267 Arm64Emitter: Make ShiftAmount enum an enum class 
Reduces namespace pollution and makes the enum strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash fab2053439 Arm64Emitter: Make RoundingMode enum an enum class 
Prevents namespace pollution and makes the enum members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash d87ec71615 Arm64Emitter: Make PStateField enum an enum class 
Prevents namespace pollution and makes the enum members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash 5c3f2fde22 Arm64Emitter: Make BarrierType enum an enum class 
Prevents namespace pollution and enforces strong typing.
 2020-12-30 20:49:20 -05:00
Lioncash f21c740919 Arm64Emitter: Make SystemHint enum an enum class 
Avoids polluting the namespace and makes the members strongly typed.
 2020-12-30 20:49:20 -05:00
Lioncash 5011c155ec Arm64Emitter: Make type member of FixupBranch an enum class 
Eliminates some magic numbers and makes the type member strongly typed.
 2020-12-30 20:49:20 -05:00
Admiral H. Curtiss 5b52b3e9cb x64Emitter: Check end of allocated space when emitting code. 2020-08-24 19:31:32 +02:00
Techjar ff972e3673 Reformat repo to clang-format 7.0 rules 2019-05-06 18:48:04 +00:00
Lioncash 208be26bb4 Arm64Emitter: Make the Align* functions return a non-const data pointer 
Similar in nature to e28d063539 in which
this same change was applied to the x64 emitter.

There's no real requirement to make this const, and this should also
be decided by the calling code, considering we had places that would
simply cast away the const and carry on
 2018-08-27 09:44:38 -04:00
Lioncash 1c63a48fab Common/CodeBlock: Namespace code under the Common namespace 
Brings more common code under the Common namespace.
 2018-05-17 15:57:29 -04:00
Lioncash 91cefe6c8a
Arm64Emitter: Make IsImmArithmetic, IsImmLogical, FPImm8ToFloat, and FPImm8FromFloat internally linked 
These aren't used anywhere outside of the emitter. Centralizes them under an anonymous namespace.
 2018-03-23 19:17:26 -04:00
Lioncash 50a476c371 Assert: Uppercase assertion macros 
Macros should be all upper-cased. This is also kind of a wart that's
been sticking out for quite a while now (we avoid prefixing
underscores).
 2018-03-14 22:03:12 -04:00
degasus 304e601ad3 JitArm64: Reimplement aarch64 cycle counters. 
CNTVCT_EL0 is force-enabled on all linux plattforms.
Windows is untested, but as this is the best way to get *any* low
overhead performance counters, they likely use it as well.
 2017-09-02 13:24:37 +02:00
Markus Wick d78009877b JitArm64: Fix LSL/LSR/ROR/ASR wrappers. 
The other method has a latency of 2 cycles. This also improves the
throughput a lot.
 2017-08-12 00:00:41 +02:00
Tillmann Karras c54c49714d Arm64Emitter: add FRECPE 2017-05-03 08:02:35 +01:00
Michael Maltese 3d7bace9da Arm64Emitter: extract lambda to AddImmediate() 
Fixes warning:

```
Source/Core/Common/Arm64Emitter.cpp:4108:31: error: declaration shadows a local variable [-Werror,-Wshadow]
    auto addi = [this](ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags) {
                                ^
  /var/lib/buildbot/slave/pr-android/build/Source/Core/Common/Arm64Emitter.cpp:4105:46: note: previous declaration is here
  void ARM64XEmitter::ADDI2R_internal(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool negative, bool flags,
                                               ^
```
 2017-03-25 14:21:19 -07:00
Lioncash a7ec2d3831 Arm64Emitter: Get rid of pointer casts in PoisonMemory 
The previous code invokes undefined behavior.
 2017-03-23 07:10:21 -04:00
degasus f1a67bb1a2 JitArm64: Implement divwx 2016-10-29 13:35:23 +02:00
degasus 8ad98d0046 ArmEmitter: Merge AddI2R helpers. 2016-10-27 19:19:06 +02:00
degasus 694e9b4132 JitArm64: ADDI2R optimizations 2. 2016-10-27 19:19:06 +02:00
degasus df250b84cc JitArm64: Avoid MOVI2R is possible. 
Just use all kind of ADDI2R, SUBI2R, ...
They have some optimizations internally.
 2016-10-26 21:54:09 +02:00
Pierre Bourdon 3570c7f03a Reformat all the things. Have fun with merge conflicts. 2016-06-24 10:43:46 +02:00
degasus 9ed465f4ac JitArm64: Implement mulhwx 2016-03-04 22:51:46 +01:00
mathieui 4b06e92731 A few more asterisks, mostly casts 2016-01-21 22:20:22 +01:00
mathieui 3e283ea9f1 More asterisks 2016-01-21 21:16:51 +01:00
mathieui 78aa398e7c Common: asterisks go against the type name 
not the variable name
 2016-01-21 20:46:25 +01:00
Lioncash 2630752ffe Arm64Emitter: Get rid of a pointer cast 2015-10-22 15:32:11 -04:00
Lioncash 018c85c248 Arm64Emitter: Mark trivial functions as constexpr 2015-10-22 15:22:38 -04:00
Lioncash 19ac565e0d Common: Move asserts to their own header 2015-09-26 18:51:27 -04:00
Ryan Houdek d495ad5104 [AArch64] Make TST reg, reg emitter alias 2015-08-31 14:03:32 -05:00
Ryan Houdek b907576510 [AArch64] Support profiling by cycle counters if they are available to EL0 2015-08-30 10:25:16 -05:00
Ryan Houdek 4fa23abbe1 [AArch64] Implement MOVI and ORR(imm) in the NEON emitter. 2015-08-23 15:34:53 -05:00
degasus 9bfff0d461 JitArm64: Fix jit clearing 
We have to reset m_lastCacheFlushEnd on clearing.
 2015-08-15 11:41:01 +02:00
degasus b8dd68beef JitArm64: Far Code Cache 2015-07-12 09:41:32 +02:00
Jeffrey Pfau c9a25f9484 Common: CallLambdaTrampoline can return a value 
As it is currently written, CallLambdaTrampoline does not return a
value. However, some of the functions that are being wrapped may
return a value that the JIT is expected to understand. A compiler
*cough cough clang* may opt to alter %rax after the wrapped lambda
returns, e.g. popping a previous value, which can clobber the
return value. If we actually have a return value, then the compiler
must not clobber it.
 2015-07-04 00:57:41 -07:00
Ryan Houdek afc3d30f5c [AArch64] Implement BFI & UBFIZ in the emitter. 
Also fixes a bug in the UBFX instruction emitter. Naughty Naughty PPSSPP, not testing emitter functions you add.
 2015-06-29 19:00:22 -05:00
Ryan Houdek 5dc148159f [AArch64] Implement {U, S}QXTN{,2} 
Also split out XTN to XTN and XTN2.
 2015-06-13 23:16:17 -05:00
Ryan Houdek 3d2b116323 [AArch64] Implement a couple instructions in the emitter. 
Implements LD2R.
Implements LD1R/LD2R with post-indexing support.
Implements vector min/max instructions.
 2015-06-09 18:10:56 -05:00