Commit Graph

96 Commits

Author SHA1 Message Date
Fiora 997c5c2d0e x64Emitter: add LZCNT/TZCNT support and detection
Also add a unit test.
2014-09-14 05:31:22 -07:00
Fiora 18d83a310e X64Emitter: support shorter mov reg, imm opcodes
Also refactor WriteNormalOp a little bit and add comments.
2014-09-11 11:40:30 -07:00
Rohit Nirmal fbc64984ca Include CommonTypes.h instead of Common.h. 2014-09-08 15:39:58 -04:00
Rohit Nirmal 629ceaf2b1 Split some parts of UpdateBoundingBox into multiple lines. Also,
fix issues causing failure on Lint.
2014-09-06 09:49:27 -05:00
Rohit Nirmal 1ecb318bcc Fix some formatting (new lines on collapsed single-line conditionals,
new lines for opening braces).
2014-09-06 01:23:05 -05:00
Fiora 5088a2b4e2 x64Emitter: add BMI1/BMI2 support
TZCNT and LZCNT use a completely different encoding scheme, so they should
probably go in a separate patch.

Also add some tests.
2014-09-03 10:04:01 -07:00
shuffle2 532b7bb7da Merge pull request #893 from rohitnirmal/scan-build-fixes
Scan build fixes
2014-09-02 23:15:18 -07:00
Fiora 9e4419e786 x64Emitter: add support for shorter EAX forms of instructions
Should save a few bytes of code size here and there.
2014-09-02 21:52:41 -07:00
Pierre Bourdon e72146d19c x64Emitter: Do not assert-fail on redundant MOVs, instead show an error log 2014-09-02 10:17:32 +02:00
Pierre Bourdon cc0b048c0b x64Emitter: Support FLD/FSTP with 80 bits operands 2014-09-02 09:52:59 +02:00
Pierre Bourdon f99f302c91 x64Emitter: assert instead of crashing when generating MOVZX with a wrong size 2014-09-02 09:52:04 +02:00
Pierre Bourdon b1738b60fc x64Emitter: Fix MUL with AH/BH/CH/DH registers. 2014-09-02 09:52:04 +02:00
Pierre Bourdon f0e8b1fda8 x64Emitter: Error out on 8 bits CMOV, and emit 16 bits CMOV properly 2014-09-02 09:52:04 +02:00
Pierre Bourdon d4ec9737bd x64Emitter: Assert when using an invalid POP instead of generating an INT3 2014-09-02 09:52:04 +02:00
Pierre Bourdon 9c4daac3a4 x64Emitter: RDTSC now without a typo'd name 2014-09-02 09:52:04 +02:00
Lioncash ec9fc6bfc1 Common: Remove unnecessary "using namespace Gen;" from x64emitter 2014-09-01 23:10:56 -04:00
Lioncash ba4934b75e Common: Clean up brace placements 2014-08-30 18:06:35 -04:00
Fiora f9d4ff0d5d x64Emitter: add support for some missing CVT instructions 2014-08-27 20:15:42 -07:00
Rohit Nirmal 4c14ebdf32 Remove pointless initializations. 2014-08-27 20:36:49 -05:00
Tillmann Karras 80be585fef x64Emitter: remove redundant "Gen::" 2014-08-20 02:56:07 +02:00
Tillmann Karras a363f4fa3e x64Emitter: make 'packed' parameter a bool 2014-08-20 02:54:30 +02:00
Fiora 802b28daf9 x64Emitter: refactor to support longer opcodes
Also add some new SSE4 opcodes.
2014-08-17 04:48:17 -07:00
Fiora 75b3e425fd x64Emitter: optimize immediate sizes
A nice alternative than trying to do it throughout the JIT.
2014-08-07 13:07:27 -04:00
Ryan Houdek 0c24e1dcf2 Remove the rest of x86_32 support from Common. 2014-08-03 13:49:46 -05:00
Pierre Bourdon 9b9817f927 x64Emitter: Fix REX encoding for SETcc
Previously using the new "lower 8 bits" registers (SIL, SPL, ...) caused SETcc
to write to other registers (for example, SETcc SIL would generate SETcc DH).
2014-07-30 06:41:29 -07:00
Tillmann Karras 6df48ed432 x64Emitter: add CVTTPD2DQ 2014-07-15 23:53:56 +02:00
Lioncash bd377b9580 Merge pull request #443 from magumagu/loadstore-cleanup
Loadstore cleanup
2014-06-26 21:32:59 -04:00
Lioncash ca5340ebde Centralize the logging code into its own folder in Common. 2014-06-25 22:11:42 -04:00
magumagu 06864e9fee JIT: Clean up float loads and stores.
Less code is good, and this should make future changes to memory handling
easier.
2014-06-20 12:52:39 -07:00
Tillmann Karras f8280401f6 x64Emitter: J_CC: use 32 bit offset automatically 2014-06-03 23:08:58 +02:00
Tillmann Karras e659f5ac58 JitBackpatch: fix NOP padding
The new NOP emitter breaks when called with a negative count. As it
turns out, it did happen when deoptimizing 8 bit MOVs because they are
only 4 bytes long and need no BSWAP.
2014-04-30 15:26:11 +02:00
Tillmann Karras 957649b7af Optimize NOPs 2014-04-23 21:15:09 +02:00
Pierre Bourdon b2597739ff x64Emitter: Add the MOVBE instruction. 2014-04-11 23:33:21 +02:00
Pierre Bourdon 664c8d30a0 Remove all trailing whitespaces from our codebase. 2014-03-29 11:05:44 +01:00
magumagu 03292eabc2 Fix OpArg::WriteRex with 8-bit memory operand.
Previously he function was misbehaving because of a missing check for
whether an 8-bit operand was a register operand; it would therefore
emit unnecessary REX prefixes, incorrectly assert on 32-bit targets, and
could potentially emit wrong code in rare cases (like a memory to register
operation involving AH.)

Also, some cleanup while I was in the area to make the function easier to
read.
2014-03-25 14:09:15 -07:00
Matthew Parlane 31cfc73a09 Fixes spacing for "for", "while", "switch" and "if"
Also moved && and || to ends of lines instead of start.
Fixed misc vertical alignments and some { needed newlining.
2014-03-11 00:35:07 +13:00
Ryan Houdek 4f02132f93 Make our architecture defines less stupid.
Our defines were never clear between what meant 64bit or x86_64
This makes a clear cut between bitness and architecture.
This commit also has the side effect of bringing up aarch64 compiling support.
2014-03-04 09:36:59 -06:00
Pierre Bourdon 311caef094 Merge pull request #25 from Tilka/ppc_fp
Fix non-IEEE mode
2014-02-23 04:15:37 +01:00
Pierre Bourdon 83b7bb64aa Make Common/ mostly IWYU clean (and fix errors in rest of the project detected by this change). 2014-02-22 23:37:29 +01:00
Lioncash 2afe215271 Convert all includes to relative paths. 2014-02-18 02:19:10 -05:00
Scott Mansell cf5938c4df x64Emitter: Fix the PSUBQ instruction's opcode 2014-02-12 23:12:17 +01:00
Scott Mansell 1eb8168488 x64Emitter: Add the xmm, xmm form of PSRLQ instruction. 2014-02-12 23:12:16 +01:00
Tillmann Karras db196d8c5b Jit64[IL]: fix float conversions
Floating-point is complicated...

Some background: Denormals are floats that are too close to zero to be
stored in a normalized way (their exponent would need more bits). Since
they are stored unnormalized, they are hard to work with, even in
hardware.  That's why both PowerPC and SSE can be configured to operate
in faster but non-standard-conpliant modes in which these numbers are
simply rounded ('flushed') to zero.

Internally, we do the same as the PowerPC CPU and store all floats in
double format. This means that for loading and storing singles we need a
conversion. The PowerPC CPU does this in hardware. We previously did
this using CVTSS2SD/CVTSD2SS. Unfortunately, these instructions are
considered arithmetic and therefore flush denormals to zero if non-IEEE
mode is active. This normally wouldn't be a problem since the next
arithmetic floating-point instruction would do the same anyway but as it
turns out some games actually use floating-point instructions for
copying arbitrary data.

My idea for fixing this problem was to use x87 instructions since the
x87 FPU never supported flush-to-zero and thus doesn't mangle denormals.
However, there is one more problem to deal with: SNaNs are automatically
converted to QNaNs (by setting the most-significant bit of the
fraction). I opted to fix this by manually resetting the QNaN bit of all
values with all-1s exponent.
2014-02-12 23:12:15 +01:00
Tillmann Karras c25c4a6e20 x64: add support for some x87 instructions 2014-02-12 22:45:01 +01:00
Tillmann Karras b34fe2b8f1 x64: fix parameter names of WriteModRM() 2014-01-25 17:36:09 +01:00
Jasper St. Pierre 34692ab826 Remove unnecessary Src/ folders 2013-12-31 14:03:19 -05:00