x64Emitter: add BMI1/BMI2 support
TZCNT and LZCNT use a completely different encoding scheme, so they should probably go in a separate patch. Also add some tests.
This commit is contained in:
Fiora
parent
b583879c2a
commit
5088a2b4e2
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@ -152,22 +152,13 @@ void OpArg::WriteRex(XEmitter *emit, int opBits, int bits, int customOp) const
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}
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}
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void OpArg::WriteVex(XEmitter* emit, int size, bool packed, X64Reg regOp1, X64Reg regOp2) const
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void OpArg::WriteVex(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W) const
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{
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int R = !(regOp1 & 8);
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int X = !(indexReg & 8);
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int B = !(offsetOrBaseReg & 8);
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// not so sure about this one...
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int W = 0;
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// aka map_select in AMD manuals
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// only support VEX opcode map 1 for now (analog to secondary opcode map)
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int mmmmm = 1;
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int vvvv = (regOp2 == X64Reg::INVALID_REG) ? 0xf : (regOp2 ^ 0xf);
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int L = size == 256;
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int pp = (packed << 1) | (size == 64);
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// do we need any VEX fields that only appear in the three-byte form?
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if (X == 1 && B == 1 && W == 0 && mmmmm == 1)
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@ -189,7 +180,7 @@ void OpArg::WriteVex(XEmitter* emit, int size, bool packed, X64Reg regOp1, X64Re
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void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg,
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bool warn_64bit_offset) const
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{
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if (_operandReg == 0xff)
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if (_operandReg == INVALID_REG)
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_operandReg = (X64Reg)this->operandReg;
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int mod = 0;
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int ireg = indexReg;
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@ -878,7 +869,7 @@ void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
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if (bits == 16) Write8(0x66); //TODO: performance warning
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src.WriteRex(this, bits, bits);
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Write8(0x8D);
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src.WriteRest(this, 0, (X64Reg)0xFF, bits == 64);
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src.WriteRest(this, 0, INVALID_REG, bits == 64);
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}
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//shift can be either imm8 or cl
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@ -1284,11 +1275,7 @@ void XEmitter::WriteSSEOp(int size, u16 sseOp, bool packed, X64Reg regOp, OpArg
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arg.WriteRex(this, 0, 0);
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Write8(0x0F);
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if (sseOp > 0xFF)
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{
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// Currently, only 0x38 and 0x3A are used as secondary escape byte.
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_assert_msg_(DYNA_REC, ((sseOp >> 8) & 0xFD) == 0x38, "Invalid SSE opcode: 0F%04X", sseOp);
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Write8((sseOp >> 8) & 0xFF);
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}
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Write8(sseOp & 0xFF);
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arg.WriteRest(this, extrabytes);
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}
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@ -1302,17 +1289,59 @@ void XEmitter::WriteAVXOp(int size, u16 sseOp, bool packed, X64Reg regOp1, X64Re
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{
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if (!cpu_info.bAVX)
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PanicAlert("Trying to use AVX on a system that doesn't support it. Bad programmer.");
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arg.WriteVex(this, size, packed, regOp1, regOp2);
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if (sseOp > 0xFF)
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{
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// Currently, only 0x38 and 0x3A are used as secondary escape byte.
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_assert_msg_(DYNA_REC, ((sseOp >> 8) & 0xFD) == 0x38, "Invalid SSE opcode: 0F%04X", sseOp);
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Write8((sseOp >> 8) & 0xFF);
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}
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// Currently, only 0x38 and 0x3A are used as secondary escape byte.
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int mmmmm;
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if ((sseOp >> 8) == 0x3A)
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mmmmm = 3;
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else if ((sseOp >> 8) == 0x38)
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mmmmm = 2;
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else
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mmmmm = 1;
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// FIXME: we currently don't support 256-bit instructions, and "size" is not the vector size here
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arg.WriteVex(this, regOp1, regOp2, 0, (packed << 1) | (size == 64), mmmmm);
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Write8(sseOp & 0xFF);
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arg.WriteRest(this, extrabytes, regOp1);
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}
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// Like the above, but more general; covers GPR-based VEX operations, like BMI1/2
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void XEmitter::WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
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{
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if (size != 32 && size != 64)
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PanicAlert("VEX GPR instructions only support 32-bit and 64-bit modes!");
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int mmmmm, pp;
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if ((op >> 8) == 0x3A)
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mmmmm = 3;
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else if ((op >> 8) == 0x38)
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mmmmm = 2;
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else
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mmmmm = 1;
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if (opPrefix == 0x66)
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pp = 1;
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else if (opPrefix == 0xF3)
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pp = 2;
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else if (opPrefix == 0xF2)
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pp = 3;
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else
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pp = 0;
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arg.WriteVex(this, regOp1, regOp2, 0, pp, mmmmm, size == 64);
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Write8(op & 0xFF);
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arg.WriteRest(this, extrabytes, regOp1);
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}
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void XEmitter::WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
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{
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if (!cpu_info.bBMI1)
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PanicAlert("Trying to use BMI1 on a system that doesn't support it. Bad programmer.");
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WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes);
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}
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void XEmitter::WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes)
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{
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if (!cpu_info.bBMI2)
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PanicAlert("Trying to use BMI2 on a system that doesn't support it. Bad programmer.");
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WriteVEXOp(size, opPrefix, op, regOp1, regOp2, arg, extrabytes);
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}
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void XEmitter::MOVD_xmm(X64Reg dest, const OpArg &arg) {WriteSSEOp(64, 0x6E, true, dest, arg, 0);}
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void XEmitter::MOVD_xmm(const OpArg &arg, X64Reg src) {WriteSSEOp(64, 0x7E, true, src, arg, 0);}
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@ -1663,6 +1692,20 @@ void XEmitter::VSQRTSD(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64,
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void XEmitter::VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseAND, false, regOp1, regOp2, arg);}
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void XEmitter::VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteAVXOp(64, sseANDN, false, regOp1, regOp2, arg);}
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void XEmitter::SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF3, 0x38F7, regOp1, regOp2, arg);}
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void XEmitter::SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x66, 0x38F7, regOp1, regOp2, arg);}
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void XEmitter::SHRX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0xF2, 0x38F7, regOp1, regOp2, arg);}
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void XEmitter::RORX(int bits, X64Reg regOp, OpArg arg, u8 rotate) {WriteBMI2Op(bits, 0xF2, 0x3AF0, regOp, INVALID_REG, arg, 1); Write8(rotate);}
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void XEmitter::PEXT(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF3, 0x38F5, regOp1, regOp2, arg);}
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void XEmitter::PDEP(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF2, 0x38F5, regOp1, regOp2, arg);}
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void XEmitter::MULX(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI2Op(bits, 0xF2, 0x38F6, regOp2, regOp1, arg);}
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void XEmitter::BZHI(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2) {WriteBMI2Op(bits, 0x00, 0x38F5, regOp1, regOp2, arg);}
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void XEmitter::BLSR(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x1, regOp, arg);}
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void XEmitter::BLSMSK(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x2, regOp, arg);}
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void XEmitter::BLSI(int bits, X64Reg regOp, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F3, (X64Reg)0x3, regOp, arg);}
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void XEmitter::BEXTR(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2){WriteBMI1Op(bits, 0x00, 0x38F7, regOp1, regOp2, arg);}
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void XEmitter::ANDN(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg) {WriteBMI1Op(bits, 0x00, 0x38F2, regOp1, regOp2, arg);}
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// Prefixes
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void XEmitter::LOCK() { Write8(0xF0); }
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@ -127,8 +127,8 @@ struct OpArg
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offset = _offset;
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}
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteVex(XEmitter* emit, int size, bool packed, X64Reg regOp1, X64Reg regOp2) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF, bool warn_64bit_offset = true) const;
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void WriteVex(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp, int mmmmm, int W = 0) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=INVALID_REG, bool warn_64bit_offset = true) const;
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void WriteFloatModRM(XEmitter *emit, FloatOp op);
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
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// This one is public - must be written to
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@ -275,6 +275,9 @@ private:
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void WriteSSE41Op(int size, u16 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u16 sseOp, bool packed, X64Reg regOp, OpArg arg, int extrabytes = 0);
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void WriteAVXOp(int size, u16 sseOp, bool packed, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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@ -708,6 +711,21 @@ public:
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void VPAND(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void VPANDN(X64Reg regOp1, X64Reg regOp2, OpArg arg);
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// VEX GPR instructions
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void SARX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
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void SHLX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
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void SHRX(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
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void RORX(int bits, X64Reg regOp, OpArg arg, u8 rotate);
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void PEXT(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void PDEP(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void MULX(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void BZHI(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
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void BLSR(int bits, X64Reg regOp, OpArg arg);
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void BLSMSK(int bits, X64Reg regOp, OpArg arg);
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void BLSI(int bits, X64Reg regOp, OpArg arg);
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void BEXTR(int bits, X64Reg regOp1, OpArg arg, X64Reg regOp2);
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void ANDN(int bits, X64Reg regOp1, X64Reg regOp2, OpArg arg);
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void RDTSC();
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// Utility functions
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@ -833,4 +833,121 @@ TWO_OP_SSE_TEST(PMOVZXDQ, "qword")
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// TODO: AVX
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// for VEX GPR instructions that take the form op reg, r/m, reg
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#define VEX_RMR_TEST(Name) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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struct { \
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int bits; \
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std::vector<NamedReg> regs; \
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std::string out_name; \
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std::string size; \
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} regsets[] = { \
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{ 32, reg32names, "eax", "dword" }, \
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{ 64, reg64names, "rax", "qword" }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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emitter->Name(regset.bits, r.reg, R(RAX), RAX); \
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emitter->Name(regset.bits, RAX, R(r.reg), RAX); \
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emitter->Name(regset.bits, RAX, MatR(R12), r.reg); \
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ExpectDisassembly(#Name " " + r.name + ", " + regset.out_name + ", " + regset.out_name + " " \
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#Name " " + regset.out_name + ", " + r.name + ", " + regset.out_name + " " \
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#Name " " + regset.out_name + ", " + regset.size + " ptr ds:[r12], " + r.name + " "); \
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} \
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}
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VEX_RMR_TEST(SHRX)
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VEX_RMR_TEST(SARX)
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VEX_RMR_TEST(SHLX)
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VEX_RMR_TEST(BEXTR)
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VEX_RMR_TEST(BZHI)
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// for VEX GPR instructions that take the form op reg, reg, r/m
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#define VEX_RRM_TEST(Name) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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struct { \
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int bits; \
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std::vector<NamedReg> regs; \
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std::string out_name; \
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std::string size; \
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} regsets[] = { \
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{ 32, reg32names, "eax", "dword" }, \
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{ 64, reg64names, "rax", "qword" }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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emitter->Name(regset.bits, r.reg, RAX, R(RAX)); \
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emitter->Name(regset.bits, RAX, RAX, R(r.reg)); \
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emitter->Name(regset.bits, RAX, r.reg, MatR(R12)); \
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ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", " + regset.out_name + " " \
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#Name " " + regset.out_name + ", " + regset.out_name + ", " + r.name + " " \
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#Name " " + regset.out_name + ", " + r.name + ", " + regset.size + " ptr ds:[r12] "); \
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} \
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}
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VEX_RRM_TEST(PEXT)
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VEX_RRM_TEST(PDEP)
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VEX_RRM_TEST(MULX)
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VEX_RRM_TEST(ANDN)
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// for VEX GPR instructions that take the form op reg, r/m
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#define VEX_RM_TEST(Name) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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struct { \
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int bits; \
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std::vector<NamedReg> regs; \
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std::string out_name; \
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std::string size; \
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} regsets[] = { \
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{ 32, reg32names, "eax", "dword" }, \
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{ 64, reg64names, "rax", "qword" }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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emitter->Name(regset.bits, r.reg, R(RAX)); \
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emitter->Name(regset.bits, RAX, R(r.reg)); \
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emitter->Name(regset.bits, r.reg, MatR(R12)); \
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ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + " " \
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#Name " " + regset.out_name + ", " + r.name + " " \
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#Name " " + r.name + ", " + regset.size + " ptr ds:[r12] "); \
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} \
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}
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VEX_RM_TEST(BLSR)
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VEX_RM_TEST(BLSMSK)
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VEX_RM_TEST(BLSI)
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// for VEX GPR instructions that take the form op reg, r/m, imm
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#define VEX_RMI_TEST(Name) \
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TEST_F(x64EmitterTest, Name) \
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{ \
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struct { \
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int bits; \
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std::vector<NamedReg> regs; \
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std::string out_name; \
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std::string size; \
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} regsets[] = { \
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{ 32, reg32names, "eax", "dword" }, \
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{ 64, reg64names, "rax", "qword" }, \
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}; \
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for (const auto& regset : regsets) \
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for (const auto& r : regset.regs) \
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{ \
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emitter->Name(regset.bits, r.reg, R(RAX), 4); \
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emitter->Name(regset.bits, RAX, R(r.reg), 4); \
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emitter->Name(regset.bits, r.reg, MatR(R12), 4); \
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ExpectDisassembly(#Name " " + r.name+ ", " + regset.out_name + ", 0x04 " \
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#Name " " + regset.out_name + ", " + r.name + ", 0x04 " \
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#Name " " + r.name + ", " + regset.size + " ptr ds:[r12], 0x04 "); \
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} \
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}
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VEX_RMI_TEST(RORX)
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} // namespace Gen
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