dolphin/Source/Core/VideoCommon/CommandProcessor.cpp

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// Copyright 2008 Dolphin Emulator Project
2015-05-17 23:08:10 +00:00
// Licensed under GPLv2+
// Refer to the license.txt file included.
#include <atomic>
#include <cstring>
#include "Common/Assert.h"
#include "Common/Atomic.h"
#include "Common/ChunkFile.h"
#include "Common/CommonTypes.h"
#include "Common/Flag.h"
#include "Common/Logging/Log.h"
#include "Core/ConfigManager.h"
#include "Core/CoreTiming.h"
#include "Core/HW/GPFifo.h"
#include "Core/HW/MMIO.h"
#include "Core/HW/ProcessorInterface.h"
#include "VideoCommon/CommandProcessor.h"
#include "VideoCommon/Fifo.h"
namespace CommandProcessor
{
static CoreTiming::EventType* et_UpdateInterrupts;
// TODO(ector): Warn on bbox read/write
// STATE_TO_SAVE
SCPFifoStruct fifo;
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static UCPStatusReg m_CPStatusReg;
static UCPCtrlReg m_CPCtrlReg;
static UCPClearReg m_CPClearReg;
2014-07-08 13:58:25 +00:00
static u16 m_bboxleft;
static u16 m_bboxtop;
static u16 m_bboxright;
static u16 m_bboxbottom;
static u16 m_tokenReg;
static Common::Flag s_interrupt_set;
static Common::Flag s_interrupt_waiting;
2014-07-08 12:29:26 +00:00
static bool IsOnThread()
{
return SConfig::GetInstance().bCPUThread;
}
static void UpdateInterrupts_Wrapper(u64 userdata, s64 cyclesLate)
{
UpdateInterrupts(userdata);
}
void SCPFifoStruct::DoState(PointerWrap& p)
{
p.Do(CPBase);
p.Do(CPEnd);
p.Do(CPHiWatermark);
p.Do(CPLoWatermark);
p.Do(CPReadWriteDistance);
p.Do(CPWritePointer);
p.Do(CPReadPointer);
p.Do(CPBreakpoint);
p.Do(SafeCPReadPointer);
p.Do(bFF_GPLinkEnable);
p.Do(bFF_GPReadEnable);
p.Do(bFF_BPEnable);
p.Do(bFF_BPInt);
p.Do(bFF_Breakpoint);
p.Do(bFF_LoWatermarkInt);
p.Do(bFF_HiWatermarkInt);
p.Do(bFF_LoWatermark);
p.Do(bFF_HiWatermark);
}
void DoState(PointerWrap& p)
{
p.DoPOD(m_CPStatusReg);
p.DoPOD(m_CPCtrlReg);
p.DoPOD(m_CPClearReg);
p.Do(m_bboxleft);
p.Do(m_bboxtop);
p.Do(m_bboxright);
p.Do(m_bboxbottom);
p.Do(m_tokenReg);
fifo.DoState(p);
p.Do(s_interrupt_set);
p.Do(s_interrupt_waiting);
}
Add the 'desynced GPU thread' mode. It's a relatively big commit (less big with -w), but it's hard to test any of this separately... The basic problem is that in netplay or movies, the state of the CPU must be deterministic, including when the game receives notification that the GPU has processed FIFO data. Dual core mode notifies the game whenever the GPU thread actually gets around to doing the work, so it isn't deterministic. Single core mode is because it notifies the game 'instantly' (after processing the data synchronously), but it's too slow for many systems and games. My old dc-netplay branch worked as follows: everything worked as normal except the state of the CP registers was a lie, and the CPU thread only delivered results when idle detection triggered (waiting for the GPU if they weren't ready at that point). Usually, a game is idle iff all the work for the frame has been done, except for a small amount of work depending on the GPU result, so neither the CPU or the GPU waiting on the other affected performance much. However, it's possible that the game could be waiting for some earlier interrupt, and any of several games which, for whatever reason, never went into a detectable idle (even when I tried to improve the detection) would never receive results at all. (The current method should have better compatibility, but it also has slightly higher overhead and breaks some other things, so I want to reimplement this, hopefully with less impact on the code, in the future.) With this commit, the basic idea is that the CPU thread acts as if the work has been done instantly, like single core mode, but actually hands it off asynchronously to the GPU thread (after backing up some data that the game might change in memory before it's actually done). Since the work isn't done, any feedback from the GPU to the CPU, such as real XFB/EFB copies (virtual are OK), EFB pokes, performance queries, etc. is broken; but most games work with these options disabled, and there is no need to try to detect what the CPU thread is doing. Technically: when the flag g_use_deterministic_gpu_thread (currently stuck on) is on, the CPU thread calls RunGpu like in single core mode. This function synchronously copies the data from the FIFO to the internal video buffer and updates the CP registers, interrupts, etc. However, instead of the regular ReadDataFromFifo followed by running the opcode decoder, it runs ReadDataFromFifoOnCPU -> OpcodeDecoder_Preprocess, which relatively quickly scans through the FIFO data, detects SetFinish calls etc., which are immediately fired, and saves certain associated data from memory (e.g. display lists) in AuxBuffers (a parallel stream to the main FIFO, which is a bit slow at the moment), before handing the data off to the GPU thread to actually render. That makes up the bulk of this commit. In various circumstances, including the aforementioned EFB pokes and performance queries as well as swap requests (i.e. the end of a frame - we don't want the CPU potentially pumping out frames too quickly and the GPU falling behind*), SyncGPU is called to wait for actual completion. The overhead mainly comes from OpcodeDecoder_Preprocess (which is, again, synchronous), as well as the actual copying. Currently, display lists and such are escrowed from main memory even though they usually won't change over the course of a frame, and textures are not even though they might, resulting in a small chance of graphical glitches. When the texture locking (i.e. fault on write) code lands, I can make this all correct and maybe a little faster. * This suggests an alternate determinism method of just delaying results until a short time before the end of each frame. For all I know this might mostly work - I haven't tried it - but if any significant work hinges on the competion of render to texture etc., the frame will be missed.
2014-08-28 02:56:19 +00:00
static inline void WriteLow(volatile u32& _reg, u16 lowbits)
{
Common::AtomicStore(_reg, (_reg & 0xFFFF0000) | lowbits);
}
static inline void WriteHigh(volatile u32& _reg, u16 highbits)
{
Common::AtomicStore(_reg, (_reg & 0x0000FFFF) | ((u32)highbits << 16));
}
static inline u16 ReadLow(u32 _reg)
{
return (u16)(_reg & 0xFFFF);
}
static inline u16 ReadHigh(u32 _reg)
{
return (u16)(_reg >> 16);
}
void Init()
{
m_CPStatusReg.Hex = 0;
m_CPStatusReg.CommandIdle = 1;
m_CPStatusReg.ReadIdle = 1;
m_CPCtrlReg.Hex = 0;
2012-01-02 10:20:22 +00:00
m_CPClearReg.Hex = 0;
m_bboxleft = 0;
m_bboxtop = 0;
m_bboxright = 640;
m_bboxbottom = 480;
m_tokenReg = 0;
memset(&fifo, 0, sizeof(fifo));
fifo.bFF_Breakpoint = 0;
fifo.bFF_HiWatermark = 0;
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
fifo.bFF_HiWatermarkInt = 0;
fifo.bFF_LoWatermark = 0;
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
fifo.bFF_LoWatermarkInt = 0;
s_interrupt_set.Clear();
s_interrupt_waiting.Clear();
et_UpdateInterrupts = CoreTiming::RegisterEvent("CPInterrupt", UpdateInterrupts_Wrapper);
}
u32 GetPhysicalAddressMask()
{
// Physical addresses in CP seem to ignore some of the upper bits (depending on platform)
// This can be observed in CP MMIO registers by setting to 0xffffffff and then reading back.
return SConfig::GetInstance().bWii ? 0x1fffffff : 0x03ffffff;
}
void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
{
constexpr u16 WMASK_NONE = 0x0000;
constexpr u16 WMASK_ALL = 0xffff;
constexpr u16 WMASK_LO_ALIGN_32BIT = 0xffe0;
const u16 WMASK_HI_RESTRICT = GetPhysicalAddressMask() >> 16;
struct
{
u32 addr;
u16* ptr;
bool readonly;
// FIFO mmio regs in the range [cc000020-cc00003e] have certain bits that always read as 0
// For _LO registers in this range, only bits 0xffe0 can be set
// For _HI registers in this range, only bits 0x03ff can be set on GCN and 0x1fff on Wii
u16 wmask;
} directly_mapped_vars[] = {
{FIFO_TOKEN_REGISTER, &m_tokenReg, false, WMASK_ALL},
// Bounding box registers are read only.
{FIFO_BOUNDING_BOX_LEFT, &m_bboxleft, true, WMASK_NONE},
{FIFO_BOUNDING_BOX_RIGHT, &m_bboxright, true, WMASK_NONE},
{FIFO_BOUNDING_BOX_TOP, &m_bboxtop, true, WMASK_NONE},
{FIFO_BOUNDING_BOX_BOTTOM, &m_bboxbottom, true, WMASK_NONE},
{FIFO_BASE_LO, MMIO::Utils::LowPart(&fifo.CPBase), false, WMASK_LO_ALIGN_32BIT},
{FIFO_BASE_HI, MMIO::Utils::HighPart(&fifo.CPBase), false, WMASK_HI_RESTRICT},
{FIFO_END_LO, MMIO::Utils::LowPart(&fifo.CPEnd), false, WMASK_LO_ALIGN_32BIT},
{FIFO_END_HI, MMIO::Utils::HighPart(&fifo.CPEnd), false, WMASK_HI_RESTRICT},
{FIFO_HI_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPHiWatermark), false,
WMASK_LO_ALIGN_32BIT},
{FIFO_HI_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPHiWatermark), false, WMASK_HI_RESTRICT},
{FIFO_LO_WATERMARK_LO, MMIO::Utils::LowPart(&fifo.CPLoWatermark), false,
WMASK_LO_ALIGN_32BIT},
{FIFO_LO_WATERMARK_HI, MMIO::Utils::HighPart(&fifo.CPLoWatermark), false, WMASK_HI_RESTRICT},
// FIFO_RW_DISTANCE has some complex read code different for
// single/dual core.
{FIFO_WRITE_POINTER_LO, MMIO::Utils::LowPart(&fifo.CPWritePointer), false,
WMASK_LO_ALIGN_32BIT},
{FIFO_WRITE_POINTER_HI, MMIO::Utils::HighPart(&fifo.CPWritePointer), false,
WMASK_HI_RESTRICT},
// FIFO_READ_POINTER has different code for single/dual core.
};
for (auto& mapped_var : directly_mapped_vars)
{
mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
mapped_var.readonly ? MMIO::InvalidWrite<u16>() :
MMIO::DirectWrite<u16>(mapped_var.ptr, mapped_var.wmask));
}
mmio->Register(base | FIFO_BP_LO, MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPBreakpoint)),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
WriteLow(fifo.CPBreakpoint, val & WMASK_LO_ALIGN_32BIT);
}));
Add the 'desynced GPU thread' mode. It's a relatively big commit (less big with -w), but it's hard to test any of this separately... The basic problem is that in netplay or movies, the state of the CPU must be deterministic, including when the game receives notification that the GPU has processed FIFO data. Dual core mode notifies the game whenever the GPU thread actually gets around to doing the work, so it isn't deterministic. Single core mode is because it notifies the game 'instantly' (after processing the data synchronously), but it's too slow for many systems and games. My old dc-netplay branch worked as follows: everything worked as normal except the state of the CP registers was a lie, and the CPU thread only delivered results when idle detection triggered (waiting for the GPU if they weren't ready at that point). Usually, a game is idle iff all the work for the frame has been done, except for a small amount of work depending on the GPU result, so neither the CPU or the GPU waiting on the other affected performance much. However, it's possible that the game could be waiting for some earlier interrupt, and any of several games which, for whatever reason, never went into a detectable idle (even when I tried to improve the detection) would never receive results at all. (The current method should have better compatibility, but it also has slightly higher overhead and breaks some other things, so I want to reimplement this, hopefully with less impact on the code, in the future.) With this commit, the basic idea is that the CPU thread acts as if the work has been done instantly, like single core mode, but actually hands it off asynchronously to the GPU thread (after backing up some data that the game might change in memory before it's actually done). Since the work isn't done, any feedback from the GPU to the CPU, such as real XFB/EFB copies (virtual are OK), EFB pokes, performance queries, etc. is broken; but most games work with these options disabled, and there is no need to try to detect what the CPU thread is doing. Technically: when the flag g_use_deterministic_gpu_thread (currently stuck on) is on, the CPU thread calls RunGpu like in single core mode. This function synchronously copies the data from the FIFO to the internal video buffer and updates the CP registers, interrupts, etc. However, instead of the regular ReadDataFromFifo followed by running the opcode decoder, it runs ReadDataFromFifoOnCPU -> OpcodeDecoder_Preprocess, which relatively quickly scans through the FIFO data, detects SetFinish calls etc., which are immediately fired, and saves certain associated data from memory (e.g. display lists) in AuxBuffers (a parallel stream to the main FIFO, which is a bit slow at the moment), before handing the data off to the GPU thread to actually render. That makes up the bulk of this commit. In various circumstances, including the aforementioned EFB pokes and performance queries as well as swap requests (i.e. the end of a frame - we don't want the CPU potentially pumping out frames too quickly and the GPU falling behind*), SyncGPU is called to wait for actual completion. The overhead mainly comes from OpcodeDecoder_Preprocess (which is, again, synchronous), as well as the actual copying. Currently, display lists and such are escrowed from main memory even though they usually won't change over the course of a frame, and textures are not even though they might, resulting in a small chance of graphical glitches. When the texture locking (i.e. fault on write) code lands, I can make this all correct and maybe a little faster. * This suggests an alternate determinism method of just delaying results until a short time before the end of each frame. For all I know this might mostly work - I haven't tried it - but if any significant work hinges on the competion of render to texture etc., the frame will be missed.
2014-08-28 02:56:19 +00:00
mmio->Register(base | FIFO_BP_HI,
MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPBreakpoint)),
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
WriteHigh(fifo.CPBreakpoint, val & WMASK_HI_RESTRICT);
}));
// Timing and metrics MMIOs are stubbed with fixed values.
struct
{
u32 addr;
u16 value;
} metrics_mmios[] = {
{XF_RASBUSY_L, 0},
{XF_RASBUSY_H, 0},
{XF_CLKS_L, 0},
{XF_CLKS_H, 0},
{XF_WAIT_IN_L, 0},
{XF_WAIT_IN_H, 0},
{XF_WAIT_OUT_L, 0},
{XF_WAIT_OUT_H, 0},
{VCACHE_METRIC_CHECK_L, 0},
{VCACHE_METRIC_CHECK_H, 0},
{VCACHE_METRIC_MISS_L, 0},
{VCACHE_METRIC_MISS_H, 0},
{VCACHE_METRIC_STALL_L, 0},
{VCACHE_METRIC_STALL_H, 0},
{CLKS_PER_VTX_OUT, 4},
};
for (auto& metrics_mmio : metrics_mmios)
{
mmio->Register(base | metrics_mmio.addr, MMIO::Constant<u16>(metrics_mmio.value),
MMIO::InvalidWrite<u16>());
}
mmio->Register(base | STATUS_REGISTER, MMIO::ComplexRead<u16>([](u32) {
SetCpStatusRegister();
return m_CPStatusReg.Hex;
}),
MMIO::InvalidWrite<u16>());
mmio->Register(base | CTRL_REGISTER, MMIO::DirectRead<u16>(&m_CPCtrlReg.Hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
UCPCtrlReg tmp(val);
m_CPCtrlReg.Hex = tmp.Hex;
SetCpControlRegister();
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
}));
mmio->Register(base | CLEAR_REGISTER, MMIO::DirectRead<u16>(&m_CPClearReg.Hex),
MMIO::ComplexWrite<u16>([](u32, u16 val) {
UCPClearReg tmp(val);
m_CPClearReg.Hex = tmp.Hex;
SetCpClearRegister();
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
}));
mmio->Register(base | PERF_SELECT, MMIO::InvalidRead<u16>(), MMIO::Nop<u16>());
// Some MMIOs have different handlers for single core vs. dual core mode.
mmio->Register(base | FIFO_RW_DISTANCE_LO,
IsOnThread() ?
MMIO::ComplexRead<u16>([](u32) {
if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
return ReadLow(fifo.CPWritePointer - fifo.SafeCPReadPointer);
else
return ReadLow(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
fifo.CPBase + 32);
}) :
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance)),
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadWriteDistance),
WMASK_LO_ALIGN_32BIT));
mmio->Register(base | FIFO_RW_DISTANCE_HI,
IsOnThread() ?
MMIO::ComplexRead<u16>([](u32) {
if (fifo.CPWritePointer >= fifo.SafeCPReadPointer)
return ReadHigh(fifo.CPWritePointer - fifo.SafeCPReadPointer);
else
return ReadHigh(fifo.CPEnd - fifo.SafeCPReadPointer + fifo.CPWritePointer -
fifo.CPBase + 32);
}) :
MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadWriteDistance)),
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
WriteHigh(fifo.CPReadWriteDistance, val & WMASK_HI_RESTRICT);
2016-08-19 02:35:58 +00:00
Fifo::SyncGPU(Fifo::SyncGPUReason::Other);
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
}));
mmio->Register(
base | FIFO_READ_POINTER_LO,
IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.SafeCPReadPointer)) :
MMIO::DirectRead<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer)),
MMIO::DirectWrite<u16>(MMIO::Utils::LowPart(&fifo.CPReadPointer), WMASK_LO_ALIGN_32BIT));
mmio->Register(
base | FIFO_READ_POINTER_HI,
IsOnThread() ? MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.SafeCPReadPointer)) :
MMIO::DirectRead<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer)),
IsOnThread() ?
MMIO::ComplexWrite<u16>([WMASK_HI_RESTRICT](u32, u16 val) {
WriteHigh(fifo.CPReadPointer, val & WMASK_HI_RESTRICT);
fifo.SafeCPReadPointer = fifo.CPReadPointer;
}) :
MMIO::DirectWrite<u16>(MMIO::Utils::HighPart(&fifo.CPReadPointer), WMASK_HI_RESTRICT));
}
void GatherPipeBursted()
{
SetCPStatusFromCPU();
// if we aren't linked, we don't care about gather pipe data
if (!m_CPCtrlReg.GPLinkEnable)
{
if (IsOnThread() && !Fifo::UseDeterministicGPUThread())
{
// In multibuffer mode is not allowed write in the same FIFO attached to the GPU.
// Fix Pokemon XD in DC mode.
if ((ProcessorInterface::Fifo_CPUEnd == fifo.CPEnd) &&
(ProcessorInterface::Fifo_CPUBase == fifo.CPBase) && fifo.CPReadWriteDistance > 0)
{
2016-01-12 21:44:58 +00:00
Fifo::FlushGpu();
}
}
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
return;
}
// update the fifo pointer
if (fifo.CPWritePointer == fifo.CPEnd)
fifo.CPWritePointer = fifo.CPBase;
else
fifo.CPWritePointer += GATHER_PIPE_SIZE;
if (m_CPCtrlReg.GPReadEnable && m_CPCtrlReg.GPLinkEnable)
{
ProcessorInterface::Fifo_CPUWritePointer = fifo.CPWritePointer;
ProcessorInterface::Fifo_CPUBase = fifo.CPBase;
ProcessorInterface::Fifo_CPUEnd = fifo.CPEnd;
}
// If the game is running close to overflowing, make the exception checking more frequent.
if (fifo.bFF_HiWatermark)
CoreTiming::ForceExceptionCheck(0);
Common::AtomicAdd(fifo.CPReadWriteDistance, GATHER_PIPE_SIZE);
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
ASSERT_MSG(COMMANDPROCESSOR, fifo.CPReadWriteDistance <= fifo.CPEnd - fifo.CPBase,
"FIFO is overflowed by GatherPipe !\nCPU thread is too fast!");
// check if we are in sync
ASSERT_MSG(COMMANDPROCESSOR, fifo.CPWritePointer == ProcessorInterface::Fifo_CPUWritePointer,
"FIFOs linked but out of sync");
ASSERT_MSG(COMMANDPROCESSOR, fifo.CPBase == ProcessorInterface::Fifo_CPUBase,
"FIFOs linked but out of sync");
ASSERT_MSG(COMMANDPROCESSOR, fifo.CPEnd == ProcessorInterface::Fifo_CPUEnd,
"FIFOs linked but out of sync");
}
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
void UpdateInterrupts(u64 userdata)
{
if (userdata)
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
{
s_interrupt_set.Set();
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt set");
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, true);
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
}
else
{
s_interrupt_set.Clear();
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt cleared");
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, false);
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
}
CoreTiming::ForceExceptionCheck(0);
s_interrupt_waiting.Clear();
2016-01-12 21:44:58 +00:00
Fifo::RunGpu();
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
}
void UpdateInterruptsFromVideoBackend(u64 userdata)
{
if (!Fifo::UseDeterministicGPUThread())
CoreTiming::ScheduleEvent(0, et_UpdateInterrupts, userdata, CoreTiming::FromThread::NON_CPU);
}
bool IsInterruptWaiting()
{
return s_interrupt_waiting.IsSet();
}
void SetCPStatusFromGPU()
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
{
// breakpoint
if (fifo.bFF_BPEnable)
{
if (fifo.CPBreakpoint == fifo.CPReadPointer)
{
if (!fifo.bFF_Breakpoint)
{
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Hit breakpoint at {}", fifo.CPReadPointer);
fifo.bFF_Breakpoint = true;
}
}
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
else
{
if (fifo.bFF_Breakpoint)
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Cleared breakpoint at {}", fifo.CPReadPointer);
fifo.bFF_Breakpoint = false;
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
}
}
else
{
if (fifo.bFF_Breakpoint)
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Cleared breakpoint at {}", fifo.CPReadPointer);
fifo.bFF_Breakpoint = false;
}
// overflow & underflow check
fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
{
u64 userdata = interrupt ? 1 : 0;
if (IsOnThread())
{
if (!interrupt || bpInt || undfInt || ovfInt)
{
// Schedule the interrupt asynchronously
s_interrupt_waiting.Set();
CommandProcessor::UpdateInterruptsFromVideoBackend(userdata);
}
}
else
{
CommandProcessor::UpdateInterrupts(userdata);
}
}
}
void SetCPStatusFromCPU()
{
// overflow & underflow check
fifo.bFF_HiWatermark = (fifo.CPReadWriteDistance > fifo.CPHiWatermark);
fifo.bFF_LoWatermark = (fifo.CPReadWriteDistance < fifo.CPLoWatermark);
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
bool bpInt = fifo.bFF_Breakpoint && fifo.bFF_BPInt;
bool ovfInt = fifo.bFF_HiWatermark && fifo.bFF_HiWatermarkInt;
bool undfInt = fifo.bFF_LoWatermark && fifo.bFF_LoWatermarkInt;
bool interrupt = (bpInt || ovfInt || undfInt) && m_CPCtrlReg.GPReadEnable;
if (interrupt != s_interrupt_set.IsSet() && !s_interrupt_waiting.IsSet())
{
u64 userdata = interrupt ? 1 : 0;
if (IsOnThread())
{
if (!interrupt || bpInt || undfInt || ovfInt)
{
s_interrupt_set.Set(interrupt);
DEBUG_LOG_FMT(COMMANDPROCESSOR, "Interrupt set");
ProcessorInterface::SetInterrupt(INT_CAUSE_CP, interrupt);
}
}
else
{
CommandProcessor::UpdateInterrupts(userdata);
}
}
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
}
void SetCpStatusRegister()
{
// Here always there is one fifo attached to the GPU
m_CPStatusReg.Breakpoint = fifo.bFF_Breakpoint;
m_CPStatusReg.ReadIdle = !fifo.CPReadWriteDistance || (fifo.CPReadPointer == fifo.CPWritePointer);
2016-01-12 21:44:58 +00:00
m_CPStatusReg.CommandIdle =
!fifo.CPReadWriteDistance || Fifo::AtBreakpoint() || !fifo.bFF_GPReadEnable;
m_CPStatusReg.UnderflowLoWatermark = fifo.bFF_LoWatermark;
m_CPStatusReg.OverflowHiWatermark = fifo.bFF_HiWatermark;
DEBUG_LOG_FMT(COMMANDPROCESSOR, "\t Read from STATUS_REGISTER : {:04x}", m_CPStatusReg.Hex);
DEBUG_LOG_FMT(
COMMANDPROCESSOR, "(r) status: iBP {} | fReadIdle {} | fCmdIdle {} | iOvF {} | iUndF {}",
m_CPStatusReg.Breakpoint ? "ON" : "OFF", m_CPStatusReg.ReadIdle ? "ON" : "OFF",
m_CPStatusReg.CommandIdle ? "ON" : "OFF", m_CPStatusReg.OverflowHiWatermark ? "ON" : "OFF",
m_CPStatusReg.UnderflowLoWatermark ? "ON" : "OFF");
}
void SetCpControlRegister()
{
fifo.bFF_BPInt = m_CPCtrlReg.BPInt;
fifo.bFF_BPEnable = m_CPCtrlReg.BPEnable;
fifo.bFF_HiWatermarkInt = m_CPCtrlReg.FifoOverflowIntEnable;
fifo.bFF_LoWatermarkInt = m_CPCtrlReg.FifoUnderflowIntEnable;
fifo.bFF_GPLinkEnable = m_CPCtrlReg.GPLinkEnable;
if (fifo.bFF_GPReadEnable && !m_CPCtrlReg.GPReadEnable)
{
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
2016-01-12 21:44:58 +00:00
Fifo::FlushGpu();
}
else
{
fifo.bFF_GPReadEnable = m_CPCtrlReg.GPReadEnable;
}
DEBUG_LOG_FMT(COMMANDPROCESSOR, "\t GPREAD {} | BP {} | Int {} | OvF {} | UndF {} | LINK {}",
fifo.bFF_GPReadEnable ? "ON" : "OFF", fifo.bFF_BPEnable ? "ON" : "OFF",
fifo.bFF_BPInt ? "ON" : "OFF", m_CPCtrlReg.FifoOverflowIntEnable ? "ON" : "OFF",
m_CPCtrlReg.FifoUnderflowIntEnable ? "ON" : "OFF",
m_CPCtrlReg.GPLinkEnable ? "ON" : "OFF");
}
2014-06-01 08:56:09 +00:00
// NOTE: We intentionally don't emulate this function at the moment.
// We don't emulate proper GP timing anyway at the moment, so it would just slow down emulation.
void SetCpClearRegister()
{
}
BIG FIFO Commit PART 1! Sometimes you need to write everything from 0, so 10 days later Ive rewrited some parts of the FIFO in Dual Core mode. Is pending use the same code for SC mode. - Improved the GP Register Status: now this is all the time from the fifo loop. - Improved the Interrupts manage: 1) Removed All UpdateInturrupts from CommandProcessor Writes and Read. 2) now the CP interrupts are schedule from the video thread and the fifo loop waiting until this happens 3) considering Inmediate mode for the CP interrupts 3) Implemented Interrupt CP Cache State 4) Implemented only Overflow interrupt in GatherPipeCheck because this need to be detected quickly. - Implemented Overflow handling like a real HW, when Hiwatermark interrupt happens this write ClearRegister with True en HI and False in LO (FifoIntReset) after that a Control Register is writed and the FIFO is processed to LO Watermark. - Removed all ugly code from LO and HI watermark manage - Removed all ugly code from BP manage - Change >= by == in the BP clauses - Removed speed hack (1024 chunk) for better GP Status Control. - Commented GXSetGPFifo very soon hack - Commented FackWatchDog hack - Commented FIFO_RW_DISTANCE = WritePointer hack This is the beginning and the base for the future., If this broke your favorite game my apologize, only report this and will try solve it. If you have a Overflown don't worry, I've implemented the real solution code using the Overflow Interruption only need continue working for a perfect protection. Why I did it? Because is preferable a accurate and clean fifo instead hack y fifo for improve that. Thanks to DONKO for you awesome Video Plug in and skid for the chatting. PD: I have 7-10 fps more in the star fox video. bye :P git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6554 8ced0084-cf51-0410-be5f-012b33b47a6e
2010-12-11 12:42:55 +00:00
void HandleUnknownOpcode(u8 cmd_byte, void* buffer, bool preprocess)
{
// TODO(Omega): Maybe dump FIFO to file on this error
PanicAlertFmtT("GFX FIFO: Unknown Opcode ({0:#04x} @ {1}, {2}).\n"
"This means one of the following:\n"
"* The emulated GPU got desynced, disabling dual core can help\n"
"* Command stream corrupted by some spurious memory bug\n"
"* This really is an unknown opcode (unlikely)\n"
"* Some other sort of bug\n\n"
"Further errors will be sent to the Video Backend log and\n"
"Dolphin will now likely crash or hang. Enjoy.",
cmd_byte, buffer, preprocess ? "preprocess=true" : "preprocess=false");
{
PanicAlertFmt("Illegal command {:02x}\n"
"CPBase: {:#010x}\n"
"CPEnd: {:#010x}\n"
"CPHiWatermark: {:#010x}\n"
"CPLoWatermark: {:#010x}\n"
"CPReadWriteDistance: {:#010x}\n"
"CPWritePointer: {:#010x}\n"
"CPReadPointer: {:#010x}\n"
"CPBreakpoint: {:#010x}\n"
"bFF_GPReadEnable: {}\n"
"bFF_BPEnable: {}\n"
"bFF_BPInt: {}\n"
"bFF_Breakpoint: {}\n"
"bFF_GPLinkEnable: {}\n"
"bFF_HiWatermarkInt: {}\n"
"bFF_LoWatermarkInt: {}\n",
cmd_byte, fifo.CPBase, fifo.CPEnd, fifo.CPHiWatermark, fifo.CPLoWatermark,
fifo.CPReadWriteDistance, fifo.CPWritePointer, fifo.CPReadPointer,
fifo.CPBreakpoint, fifo.bFF_GPReadEnable ? "true" : "false",
fifo.bFF_BPEnable ? "true" : "false", fifo.bFF_BPInt ? "true" : "false",
fifo.bFF_Breakpoint ? "true" : "false", fifo.bFF_GPLinkEnable ? "true" : "false",
fifo.bFF_HiWatermarkInt ? "true" : "false",
fifo.bFF_LoWatermarkInt ? "true" : "false");
}
}
} // end of namespace CommandProcessor