[maintenance] Add a note explaining why we aren't emulating CP clear register writes.
For further reference, see also r700f5eabc752.
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@ -311,6 +311,7 @@ void Write16(const u16 _Value, const u32 _Address)
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UCPClearReg tmpCtrl(_Value);
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m_CPClearReg.Hex = tmpCtrl.Hex;
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DEBUG_LOG(COMMANDPROCESSOR,"\t write to CLEAR_REGISTER : %04x", _Value);
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SetCpClearRegister();
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}
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break;
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@ -677,13 +678,15 @@ void SetCpControlRegister()
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}
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// NOTE: The implementation of this function should be correct, but we intentionally aren't using it at the moment.
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// We don't emulate proper GP timing anyway at the moment, so this code would just slow down emulation.
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void SetCpClearRegister()
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{
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if (IsOnThread())
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{
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if (!m_CPClearReg.ClearFifoUnderflow && m_CPClearReg.ClearFifoOverflow)
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bProcessFifoToLoWatermark = true;
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}
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// if (IsOnThread())
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// {
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// if (!m_CPClearReg.ClearFifoUnderflow && m_CPClearReg.ClearFifoOverflow)
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// bProcessFifoToLoWatermark = true;
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// }
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}
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} // end of namespace CommandProcessor
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@ -158,6 +158,7 @@ void UpdateInterruptsFromVideoBackend(u64 userdata);
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bool AllowIdleSkipping();
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void SetCpClearRegister();
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void SetCpControlRegister();
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void SetCpStatusRegister();
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void SetOverflowStatusFromGatherPipe();
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