emulate 8bit REG_AUXSPIDATA writes
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@ -2309,7 +2309,11 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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case REG_AUXSPICNT+1:
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case REG_AUXSPICNT+1:
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write_auxspicnt(9,8,1,val);
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write_auxspicnt(9,8,1,val);
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return;
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return;
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case REG_AUXSPIDATA:
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if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF;
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((u8)val,ARMCPU_ARM9));
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return;
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case 0x4000247:
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case 0x4000247:
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/* Update WRAMSTAT at the ARM7 side */
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/* Update WRAMSTAT at the ARM7 side */
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@ -2642,7 +2646,7 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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MMU.AUX_SPI_CMD = val & 0xFF;
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MMU.AUX_SPI_CMD = val & 0xFF;
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//T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val));
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//T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, bm_transfer(&MMU.bupmem, val));
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((u8)val,ARMCPU_ARM9));
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM9][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((u8)val,ARMCPU_ARM9));
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return;
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return;
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case REG_DISPA_BG0CNT :
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case REG_DISPA_BG0CNT :
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@ -3587,6 +3591,10 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
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case REG_AUXSPICNT+1:
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case REG_AUXSPICNT+1:
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write_auxspicnt(9,8,1,val);
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write_auxspicnt(9,8,1,val);
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return;
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return;
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case REG_AUXSPIDATA:
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if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF;
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T1WriteWord(MMU.MMU_MEM[ARMCPU_ARM7][(REG_AUXSPIDATA >> 20) & 0xff], REG_AUXSPIDATA & 0xfff, MMU_new.backupDevice.data_command((u8)val,ARMCPU_ARM7));
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return;
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}
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}
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MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
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MMU.MMU_MEM[ARMCPU_ARM7][adr>>20][adr&MMU.MMU_MASK[ARMCPU_ARM7][adr>>20]]=val;
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return;
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return;
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