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- fix overflow flag in ADCS/SBCS/RSCS;

This commit is contained in:
mtabachenko 2010-04-24 16:47:53 +00:00
parent fc0c459391
commit f535f9ac58
2 changed files with 5 additions and 5 deletions
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6
desmume/src/arm_instructions.cpp
View File

@ -1022,7 +1022,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL(const u32 i)
} \
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
cpu->CPSR.bits.V = ((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)])) != 0;\
cpu->CPSR.bits.V = BIT31((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)]));\
return a; \
}
@ -1182,7 +1182,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL(const u32 i)
} \
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
cpu->CPSR.bits.V = ((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])) != 0; \
cpu->CPSR.bits.V = BIT31((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])); \
return a; \
}
@ -1342,7 +1342,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL(const u32 i)
} \
cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \
cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \
cpu->CPSR.bits.V = ((shift_op ^ shift_op) & (shift_op ^ cpu->R[REG_POS(i, 12)])) != 0; \
cpu->CPSR.bits.V = BIT31((shift_op ^ v) & (shift_op ^ cpu->R[REG_POS(i, 12)])); \
return a; \
}

4
desmume/src/thumb_instructions.cpp
View File

@ -455,7 +455,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i)
}
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
cpu->CPSR.bits.V = (((Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)])) != 0);
cpu->CPSR.bits.V = BIT31((Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)]));
return 1;
}
@ -481,7 +481,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i)
cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]);
cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0);
cpu->CPSR.bits.V = ((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)])) != 0;
cpu->CPSR.bits.V = BIT31((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)]));
return 1;
}