From f535f9ac589c5df5470018e9eb1b33be47e38b5e Mon Sep 17 00:00:00 2001 From: mtabachenko Date: Sat, 24 Apr 2010 16:47:53 +0000 Subject: [PATCH] - fix overflow flag in ADCS/SBCS/RSCS; --- desmume/src/arm_instructions.cpp | 6 +++--- desmume/src/thumb_instructions.cpp | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index bc18fd84d..ed89280e3 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -1022,7 +1022,7 @@ TEMPLATE static u32 FASTCALL OP_ADD_S_IMM_VAL(const u32 i) } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.V = ((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)])) != 0;\ + cpu->CPSR.bits.V = BIT31((v ^ shift_op ^ -1) & (v ^ cpu->R[REG_POS(i, 12)]));\ return a; \ } @@ -1182,7 +1182,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_S_IMM_VAL(const u32 i) } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.V = ((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])) != 0; \ + cpu->CPSR.bits.V = BIT31((v ^ shift_op) & (v ^ cpu->R[REG_POS(i, 12)])); \ return a; \ } @@ -1342,7 +1342,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_S_IMM_VAL(const u32 i) } \ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]); \ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0); \ - cpu->CPSR.bits.V = ((shift_op ^ shift_op) & (shift_op ^ cpu->R[REG_POS(i, 12)])) != 0; \ + cpu->CPSR.bits.V = BIT31((shift_op ^ v) & (shift_op ^ cpu->R[REG_POS(i, 12)])); \ return a; \ } diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp index 7102cc79c..08cb67edd 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/desmume/src/thumb_instructions.cpp @@ -455,7 +455,7 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG(const u32 i) } cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0); - cpu->CPSR.bits.V = (((Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)])) != 0); + cpu->CPSR.bits.V = BIT31((Rd ^ Rm ^ -1) & (Rd ^ cpu->R[REG_NUM(i, 0)])); return 1; } @@ -481,7 +481,7 @@ TEMPLATE static u32 FASTCALL OP_SBC_REG(const u32 i) cpu->CPSR.bits.N = BIT31(cpu->R[REG_NUM(i, 0)]); cpu->CPSR.bits.Z = (cpu->R[REG_NUM(i, 0)] == 0); - cpu->CPSR.bits.V = ((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)])) != 0; + cpu->CPSR.bits.V = BIT31((Rd ^ Rm) & (Rd ^ cpu->R[REG_NUM(i, 0)])); return 1; }