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Added a bunch of crazy templates to the cpu and mmu which speed up a the emu little by optimizing variable accesses

This commit is contained in:
zeromus 2008-09-11 06:02:44 +00:00
parent b1b3a9e3bb
commit f059cc7ae1
14 changed files with 5903 additions and 5812 deletions
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1
desmume/ChangeLog
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@ -50,6 +50,7 @@
- Tweak optimization flags and change entire source code to use fastcall [zeromus] - Tweak optimization flags and change entire source code to use fastcall [zeromus]
- Add opengl state caching. This is of dubious performance assistance, but it is easy to take out so I am leaving it for now. [zeromus] - Add opengl state caching. This is of dubious performance assistance, but it is easy to take out so I am leaving it for now. [zeromus]
- Add MMU->GPU signal for when vram mappings change, which allows it to assume textures are unchanged unless vram has changed [zeromus] - Add MMU->GPU signal for when vram mappings change, which allows it to assume textures are unchanged unless vram has changed [zeromus]
- Added a bunch of crazy templates to the cpu and mmu which speed up a the emu little by optimizing variable accesses [zeromus]
0.7.3 -> 0.8 0.7.3 -> 0.8

1
desmume/src/Disassembler.cpp
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@ -3759,6 +3759,7 @@ static char * OP_BL_THUMB(u32 adr, u32 i, char * txt)
#define CALLTYPE #define CALLTYPE
#define NOM_TAB des_arm_instructions_set #define NOM_TAB des_arm_instructions_set
#define NOM_THUMB_TAB des_thumb_instructions_set #define NOM_THUMB_TAB des_thumb_instructions_set
#define TABDECL(x) x
#include "instruction_tabdef.inc" #include "instruction_tabdef.inc"
#include "thumb_tabdef.inc" #include "thumb_tabdef.inc"

63
desmume/src/MMU.cpp
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@ -584,7 +584,8 @@ void MMU_unsetRom()
} }
char txt[80]; char txt[80];
u8 FASTCALL MMU_read8(u32 proc, u32 adr) template<u32 proc>
u8 FASTCALL _MMU_read8(u32 adr)
{ {
#ifdef INTERNAL_DTCM_READ #ifdef INTERNAL_DTCM_READ
if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion)) if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion))
@ -617,9 +618,8 @@ u8 FASTCALL MMU_read8(u32 proc, u32 adr)
return MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]]; return MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]];
} }
template<u32 proc>
u16 FASTCALL _MMU_read16(u32 adr)
u16 FASTCALL MMU_read16(u32 proc, u32 adr)
{ {
#ifdef INTERNAL_DTCM_READ #ifdef INTERNAL_DTCM_READ
if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@ -695,7 +695,8 @@ u16 FASTCALL MMU_read16(u32 proc, u32 adr)
return T1ReadWord(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]); return T1ReadWord(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]);
} }
u32 FASTCALL MMU_read32(u32 proc, u32 adr) template<u32 proc>
u32 FASTCALL _MMU_read32(u32 adr)
{ {
#ifdef INTERNAL_DTCM_READ #ifdef INTERNAL_DTCM_READ
if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@ -714,7 +715,6 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr)
// CFlash reading, Mic // CFlash reading, Mic
if ((adr>=0x9000000)&&(adr<0x9900000)) if ((adr>=0x9000000)&&(adr<0x9900000))
return (unsigned long)cflash_read(adr); return (unsigned long)cflash_read(adr);
adr &= 0x0FFFFFFF; adr &= 0x0FFFFFFF;
if((adr >> 24) == 4) if((adr >> 24) == 4)
@ -848,13 +848,15 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr)
} }
} }
/* Returns data from memory */ //Returns data from memory
return T1ReadLong(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]); // Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
return T1ReadLong(MMU.MMU_MEM[proc][(adr >> 20)], adr & MMU.MMU_MASK[proc][(adr >> 20)]);
} }
#define OFS(i) ((i>>3)&3) #define OFS(i) ((i>>3)&3)
void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val) template<u32 proc>
void FASTCALL _MMU_write8(u32 adr, u8 val)
{ {
#ifdef INTERNAL_DTCM_WRITE #ifdef INTERNAL_DTCM_WRITE
if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@ -1242,7 +1244,8 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
u16 partie = 1; u16 partie = 1;
void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val) template<u32 proc>
void FASTCALL _MMU_write16(u32 adr, u16 val)
{ {
#ifdef INTERNAL_DTCM_WRITE #ifdef INTERNAL_DTCM_WRITE
if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion)) if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@ -1905,7 +1908,8 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
} }
void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val) template<u32 proc>
void FASTCALL _MMU_write32(u32 adr, u32 val)
{ {
#ifdef INTERNAL_DTCM_WRITE #ifdef INTERNAL_DTCM_WRITE
if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion)) if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion))
@ -3534,3 +3538,40 @@ struct armcpu_memory_iface arm9_direct_memory_iface = {
arm9_write16, arm9_write16,
arm9_write32 arm9_write32
}; };
u32 FASTCALL MMU_read32(u32 proc, u32 adr)
{
if(proc==0) return _MMU_read32<0ul>(adr);
else return _MMU_read32<1ul>(adr);
}
u16 FASTCALL MMU_read16(u32 proc, u32 adr)
{
if(proc==0) return _MMU_read16<0ul>(adr);
else return _MMU_read16<1ul>(adr);
}
u8 FASTCALL MMU_read8(u32 proc, u32 adr)
{
if(proc==0) return _MMU_read8<0ul>(adr);
else return _MMU_read8<1ul>(adr);
}
void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
{
if(proc==0) _MMU_write32<0ul>(adr,val);
else _MMU_write32<1ul>(adr,val);
}
void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
{
if(proc==0) _MMU_write16<0ul>(adr,val);
else _MMU_write16<1ul>(adr,val);
}
void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
{
if(proc==0) _MMU_write8<0ul>(adr,val);
else _MMU_write8<1ul>(adr,val);
}

6
desmume/src/NDSSystem.cpp
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@ -891,7 +891,8 @@ NDS_exec(s32 nb, BOOL force)
nds.ARM9Cycle += 100; nds.ARM9Cycle += 100;
else else
//nds.ARM9Cycle += NDS_ARM9.exec(); //nds.ARM9Cycle += NDS_ARM9.exec();
nds.ARM9Cycle += armcpu_exec(&NDS_ARM9); //nds.ARM9Cycle += armcpu_exec(&NDS_ARM9);
nds.ARM9Cycle += armcpu_exec<0>();
} }
} }
@ -924,7 +925,8 @@ NDS_exec(s32 nb, BOOL force)
nds.ARM7Cycle += 100; nds.ARM7Cycle += 100;
else else
//nds.ARM7Cycle += (NDS_ARM7.exec()<<1); //nds.ARM7Cycle += (NDS_ARM7.exec()<<1);
nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1); //nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1);
nds.ARM7Cycle += (armcpu_exec<1>()<<1);
} }
} }
} }

1117
desmume/src/arm_instructions.cpp
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File diff suppressed because it is too large Load Diff

3
desmume/src/arm_instructions.h
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@ -25,7 +25,8 @@
#include "types.h" #include "types.h"
#include "armcpu.h" #include "armcpu.h"
extern u32 (FASTCALL* arm_instructions_set[4096])(armcpu_t * cpu); extern u32 (FASTCALL* arm_instructions_set_0[4096])();
extern u32 (FASTCALL* arm_instructions_set_1[4096])();
#endif #endif

45
desmume/src/armcpu.cpp
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@ -26,6 +26,13 @@
#include <stdlib.h> #include <stdlib.h>
#include <stdio.h> #include <stdio.h>
template<u32> static u32 armcpu_prefetch();
inline u32 armcpu_prefetch(armcpu_t *armcpu) {
if(armcpu->proc_ID==0) return armcpu_prefetch<0>();
else return armcpu_prefetch<1>();
}
const unsigned char arm_cond_table[16*16] = { const unsigned char arm_cond_table[16*16] = {
/* N=0, Z=0, C=0, V=0 */ /* N=0, Z=0, C=0, V=0 */
0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF, 0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
@ -351,9 +358,11 @@ u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode)
return oldmode; return oldmode;
} }
template<u32 PROCNUM>
static u32 static u32
armcpu_prefetch(armcpu_t *armcpu) armcpu_prefetch()
{ {
armcpu_t* armcpu = &ARMPROC;
u32 temp_instruction; u32 temp_instruction;
if(armcpu->CPSR.bits.T == 0) if(armcpu->CPSR.bits.T == 0)
@ -370,14 +379,14 @@ armcpu_prefetch(armcpu_t *armcpu)
armcpu->R[15] = armcpu->next_instruction + 4; armcpu->R[15] = armcpu->next_instruction + 4;
} }
#else #else
armcpu->instruction = MMU_read32_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE); armcpu->instruction = MMU_read32_acl(PROCNUM, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
armcpu->instruct_adr = armcpu->next_instruction; armcpu->instruct_adr = armcpu->next_instruction;
armcpu->next_instruction += 4; armcpu->next_instruction += 4;
armcpu->R[15] = armcpu->next_instruction + 4; armcpu->R[15] = armcpu->next_instruction + 4;
#endif #endif
return MMU.MMU_WAIT32[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF]; return MMU.MMU_WAIT32[PROCNUM][(armcpu->instruct_adr>>24)&0xF];
} }
#ifdef GDB_STUB #ifdef GDB_STUB
@ -392,17 +401,16 @@ armcpu_prefetch(armcpu_t *armcpu)
armcpu->R[15] = armcpu->next_instruction + 2; armcpu->R[15] = armcpu->next_instruction + 2;
} }
#else #else
armcpu->instruction = MMU_read16_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE); armcpu->instruction = MMU_read16_acl(PROCNUM, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
armcpu->instruct_adr = armcpu->next_instruction; armcpu->instruct_adr = armcpu->next_instruction;
armcpu->next_instruction += 2; armcpu->next_instruction += 2;
armcpu->R[15] = armcpu->next_instruction + 2; armcpu->R[15] = armcpu->next_instruction + 2;
#endif #endif
return MMU.MMU_WAIT16[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF]; return MMU.MMU_WAIT16[PROCNUM][(armcpu->instruct_adr>>24)&0xF];
} }
static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); } static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); } static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
static BOOL FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); } static BOOL FASTCALL test_CS(Status_Reg CPSR) { return ( CPSR.bits.C); }
@ -525,7 +533,8 @@ armcpu_flagIrq( armcpu_t *armcpu) {
} }
u32 armcpu_exec(armcpu_t *armcpu) template<int PROCNUM>
u32 armcpu_exec()
{ {
u32 c = 1; u32 c = 1;
@ -545,12 +554,16 @@ u32 armcpu_exec(armcpu_t *armcpu)
} }
#endif #endif
if(armcpu->CPSR.bits.T == 0) if(ARMPROC.CPSR.bits.T == 0)
{ {
/* if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))*/ /* if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))*/
if((TEST_COND(CONDITION(armcpu->instruction), CODE(armcpu->instruction), armcpu->CPSR))) if((TEST_COND(CONDITION(ARMPROC.instruction), CODE(ARMPROC.instruction), ARMPROC.CPSR)))
{ {
c += arm_instructions_set[INSTRUCTION_INDEX(armcpu->instruction)](armcpu); if(PROCNUM==0)
c += arm_instructions_set_0[INSTRUCTION_INDEX(ARMPROC.instruction)]();
else
c += arm_instructions_set_1[INSTRUCTION_INDEX(ARMPROC.instruction)]();
} }
#ifdef GDB_STUB #ifdef GDB_STUB
if ( armcpu->post_ex_fn != NULL) { if ( armcpu->post_ex_fn != NULL) {
@ -559,12 +572,15 @@ u32 armcpu_exec(armcpu_t *armcpu)
armcpu->instruct_adr, 0); armcpu->instruct_adr, 0);
} }
#else #else
c += armcpu_prefetch(armcpu); c += armcpu_prefetch<PROCNUM>();
#endif #endif
return c; return c;
} }
c += thumb_instructions_set[armcpu->instruction>>6](armcpu); if(PROCNUM==0)
c += thumb_instructions_set_0[ARMPROC.instruction>>6]();
else
c += thumb_instructions_set_1[ARMPROC.instruction>>6]();
#ifdef GDB_STUB #ifdef GDB_STUB
if ( armcpu->post_ex_fn != NULL) { if ( armcpu->post_ex_fn != NULL) {
@ -572,8 +588,11 @@ u32 armcpu_exec(armcpu_t *armcpu)
armcpu->post_ex_fn( armcpu->post_ex_fn_data, armcpu->instruct_adr, 1); armcpu->post_ex_fn( armcpu->post_ex_fn_data, armcpu->instruct_adr, 1);
} }
#else #else
c += armcpu_prefetch(armcpu); c += armcpu_prefetch<PROCNUM>();
#endif #endif
return c; return c;
} }
//these templates needed to be instantiated manually
template u32 armcpu_exec<0>();
template u32 armcpu_exec<1>();

11
desmume/src/armcpu.h
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@ -28,6 +28,7 @@
#define ARMCPU_ARM7 1 #define ARMCPU_ARM7 1
#define ARMCPU_ARM9 0 #define ARMCPU_ARM9 0
#define ARMPROC (PROCNUM?NDS_ARM7:NDS_ARM9)
#define CODE(i) (((i)>>25)&0X7) #define CODE(i) (((i)>>25)&0X7)
#define OPCODE(i) (((i)>>21)&0xF) #define OPCODE(i) (((i)>>21)&0xF)
@ -227,8 +228,10 @@ int armcpu_new( armcpu_t *armcpu, u32 id);
#endif #endif
void armcpu_init(armcpu_t *armcpu, u32 adr); void armcpu_init(armcpu_t *armcpu, u32 adr);
u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode); u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode);
static u32 armcpu_prefetch(armcpu_t *armcpu);
u32 armcpu_exec(armcpu_t *armcpu);
template<int PROCNUM> u32 armcpu_exec();
BOOL armcpu_irqExeption(armcpu_t *armcpu); BOOL armcpu_irqExeption(armcpu_t *armcpu);
//BOOL armcpu_prefetchExeption(armcpu_t *armcpu); //BOOL armcpu_prefetchExeption(armcpu_t *armcpu);
BOOL BOOL
@ -276,4 +279,8 @@ static INLINE void NDS_makeInt(u8 proc_ID,u32 num)
} }
} }
//stores the currently executing arm cpu.
//we poke values in here instead of passing them around constantly.
extern armcpu_t *armcpu_curr;
#endif #endif

8546
desmume/src/instruction_tabdef.inc
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File diff suppressed because it is too large Load Diff

162
desmume/src/thumb_instructions.cpp
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@ -33,6 +33,9 @@
#include "debug.h" #include "debug.h"
#include "MMU.h" #include "MMU.h"
#define cpu (&ARMPROC)
#define TEMPLATE template<int PROCNUM>
#define REG_NUM(i, n) (((i)>>n)&0x7) #define REG_NUM(i, n) (((i)>>n)&0x7)
extern volatile BOOL execute; extern volatile BOOL execute;
@ -54,13 +57,13 @@ extern volatile BOOL execute;
#define WRITE8(a,b,c) MMU_write8(cpu->proc_ID,b,c) #define WRITE8(a,b,c) MMU_write8(cpu->proc_ID,b,c)
#endif #endif
static u32 FASTCALL OP_UND_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_UND_THUMB()
{ {
execute = FALSE; execute = FALSE;
return 1; return 1;
} }
static u32 FASTCALL OP_LSL_0(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSL_0()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)];
@ -70,7 +73,7 @@ static u32 FASTCALL OP_LSL_0(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_LSL(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSL()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = (i>>6) & 0x1F; u32 v = (i>>6) & 0x1F;
@ -82,7 +85,7 @@ static u32 FASTCALL OP_LSL(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_LSR_0(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSR_0()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
// cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]); // cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
@ -94,7 +97,7 @@ static u32 FASTCALL OP_LSR_0(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_LSR(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSR()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = (i>>6) & 0x1F; u32 v = (i>>6) & 0x1F;
@ -106,7 +109,7 @@ static u32 FASTCALL OP_LSR(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_ASR_0(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ASR_0()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]); cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
@ -117,7 +120,7 @@ static u32 FASTCALL OP_ASR_0(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_ASR(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ASR()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = (i>>6) & 0x1F; u32 v = (i>>6) & 0x1F;
@ -129,7 +132,7 @@ static u32 FASTCALL OP_ASR(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_ADD_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 3)]; u32 a = cpu->R[REG_NUM(i, 3)];
@ -143,7 +146,7 @@ static u32 FASTCALL OP_ADD_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_SUB_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_SUB_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 3)]; u32 a = cpu->R[REG_NUM(i, 3)];
@ -157,7 +160,7 @@ static u32 FASTCALL OP_SUB_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_IMM3()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 3)]; u32 a = cpu->R[REG_NUM(i, 3)];
@ -170,7 +173,7 @@ static u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_SUB_IMM3()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 3)]; u32 a = cpu->R[REG_NUM(i, 3)];
@ -183,7 +186,7 @@ static u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_MOV_IMM8()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 8)] = i & 0xFF; cpu->R[REG_NUM(i, 8)] = i & 0xFF;
@ -193,7 +196,7 @@ static u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_CMP_IMM8()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
@ -205,7 +208,7 @@ static u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_IMM8()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF); u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF);
@ -218,7 +221,7 @@ static u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_SUB_IMM8()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF); u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
@ -231,7 +234,7 @@ static u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_AND(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_AND()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)];
@ -241,7 +244,7 @@ static u32 FASTCALL OP_AND(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_EOR(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_EOR()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)];
@ -251,7 +254,7 @@ static u32 FASTCALL OP_EOR(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_LSL_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSL_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@ -281,7 +284,7 @@ static u32 FASTCALL OP_LSL_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_LSR_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LSR_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@ -311,7 +314,7 @@ static u32 FASTCALL OP_LSR_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ASR_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ASR_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@ -339,7 +342,7 @@ static u32 FASTCALL OP_ASR_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ADC_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADC_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 0)]; u32 a = cpu->R[REG_NUM(i, 0)];
@ -358,7 +361,7 @@ static u32 FASTCALL OP_ADC_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_SBC_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_SBC_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 0)]; u32 a = cpu->R[REG_NUM(i, 0)];
@ -376,7 +379,7 @@ static u32 FASTCALL OP_SBC_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ROR_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ROR_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 v = cpu->R[REG_NUM(i, 3)]&0xFF; u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@ -403,7 +406,7 @@ static u32 FASTCALL OP_ROR_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_TST(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_TST()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)]; u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)];
@ -413,7 +416,7 @@ static u32 FASTCALL OP_TST(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_NEG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_NEG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 a = cpu->R[REG_NUM(i, 3)]; u32 a = cpu->R[REG_NUM(i, 3)];
@ -427,7 +430,7 @@ static u32 FASTCALL OP_NEG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_CMP(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_CMP()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)]; u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)];
@ -440,7 +443,7 @@ static u32 FASTCALL OP_CMP(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_CMN(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_CMN()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)]; u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
@ -455,7 +458,7 @@ static u32 FASTCALL OP_CMN(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ORR(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ORR()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)];
@ -465,7 +468,7 @@ static u32 FASTCALL OP_ORR(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_MUL_REG(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_MUL_REG()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)]; cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)];
@ -475,7 +478,7 @@ static u32 FASTCALL OP_MUL_REG(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_BIC(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BIC()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]); cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]);
@ -485,7 +488,7 @@ static u32 FASTCALL OP_BIC(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_MVN(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_MVN()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]); cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]);
@ -495,7 +498,7 @@ static u32 FASTCALL OP_MVN(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_SPE()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 Rd = (i&7) | ((i>>4)&8); u32 Rd = (i&7) | ((i>>4)&8);
@ -507,7 +510,7 @@ static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_CMP_SPE()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 Rn = (i&7) | ((i>>4)&8); u32 Rn = (i&7) | ((i>>4)&8);
@ -521,7 +524,7 @@ static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_MOV_SPE()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 Rd = (i&7) | ((i>>4)&8); u32 Rd = (i&7) | ((i>>4)&8);
@ -533,7 +536,7 @@ static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BX_THUMB()
{ {
u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)]; u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)];
@ -544,7 +547,7 @@ static u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BLX_THUMB()
{ {
u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)]; u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)];
@ -556,7 +559,7 @@ static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDR_PCREL()
{ {
u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2); u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2);
@ -565,7 +568,7 @@ static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STR_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)]; u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)];
@ -574,7 +577,7 @@ static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STRH_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -583,7 +586,7 @@ static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STRB_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -592,7 +595,7 @@ static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRSB_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -601,7 +604,7 @@ static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDR_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]); u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
@ -614,7 +617,7 @@ static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRH_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -623,7 +626,7 @@ static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRB_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -632,7 +635,7 @@ static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRSH_REG_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]; u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@ -641,7 +644,7 @@ static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STR_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
@ -650,7 +653,7 @@ static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDR_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
@ -662,7 +665,7 @@ static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STRB_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
@ -671,7 +674,7 @@ static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRB_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
@ -680,7 +683,7 @@ static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STRH_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
@ -689,7 +692,7 @@ static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDRH_IMM_OFF()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E); u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
@ -698,7 +701,7 @@ static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STR_SPREL()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13] + ((i&0xFF)<<2); u32 adr = cpu->R[13] + ((i&0xFF)<<2);
@ -707,7 +710,7 @@ static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu)
return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF]; return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDR_SPREL()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13] + ((i&0xFF)<<2); u32 adr = cpu->R[13] + ((i&0xFF)<<2);
@ -716,7 +719,7 @@ static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu)
return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]; return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
} }
static u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_2PC()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2); cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
@ -724,7 +727,7 @@ static u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu)
return 5; return 5;
} }
static u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADD_2SP()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2); cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
@ -732,21 +735,21 @@ static u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu)
return 2; return 2;
} }
static u32 FASTCALL OP_ADJUST_P_SP(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADJUST_P_SP()
{ {
cpu->R[13] += ((cpu->instruction&0x7F)<<2); cpu->R[13] += ((cpu->instruction&0x7F)<<2);
return 1; return 1;
} }
static u32 FASTCALL OP_ADJUST_M_SP(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_ADJUST_M_SP()
{ {
cpu->R[13] -= ((cpu->instruction&0x7F)<<2); cpu->R[13] -= ((cpu->instruction&0x7F)<<2);
return 1; return 1;
} }
static u32 FASTCALL OP_PUSH(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_PUSH()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13] - 4; u32 adr = cpu->R[13] - 4;
@ -764,7 +767,7 @@ static u32 FASTCALL OP_PUSH(armcpu_t *cpu)
return c + 3; return c + 3;
} }
static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_PUSH_LR()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13] - 4; u32 adr = cpu->R[13] - 4;
@ -786,7 +789,7 @@ static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu)
return c + 4; return c + 4;
} }
static u32 FASTCALL OP_POP(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_POP()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13]; u32 adr = cpu->R[13];
@ -804,7 +807,7 @@ static u32 FASTCALL OP_POP(armcpu_t *cpu)
return c + 2; return c + 2;
} }
static u32 FASTCALL OP_POP_PC(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_POP_PC()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[13]; u32 adr = cpu->R[13];
@ -831,12 +834,12 @@ static u32 FASTCALL OP_POP_PC(armcpu_t *cpu)
return c + 5; return c + 5;
} }
static u32 FASTCALL OP_BKPT_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BKPT_THUMB()
{ {
return 1; return 1;
} }
static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_STMIA_THUMB()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 8)]; u32 adr = cpu->R[REG_NUM(i, 8)];
@ -853,7 +856,7 @@ static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu)
return c + 2; return c + 2;
} }
static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_LDMIA_THUMB()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
u32 adr = cpu->R[REG_NUM(i, 8)]; u32 adr = cpu->R[REG_NUM(i, 8)];
@ -870,7 +873,7 @@ static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu)
return c + 3; return c + 3;
} }
static u32 FASTCALL OP_B_COND(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_B_COND()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR)) if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
@ -881,7 +884,7 @@ static u32 FASTCALL OP_B_COND(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_SWI_THUMB()
{ {
if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9))) if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
{ {
@ -907,7 +910,7 @@ static u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu)
#define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800)) #define SIGNEEXT_IMM11(i) (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))
static u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_B_UNCOND()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[15] += (SIGNEEXT_IMM11(i)<<1); cpu->R[15] += (SIGNEEXT_IMM11(i)<<1);
@ -915,7 +918,7 @@ static u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_BLX(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BLX()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC; cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC;
@ -925,14 +928,14 @@ static u32 FASTCALL OP_BLX(armcpu_t *cpu)
return 3; return 3;
} }
static u32 FASTCALL OP_BL_10(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BL_10()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12); cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12);
return 1; return 1;
} }
static u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu) TEMPLATE static u32 FASTCALL OP_BL_THUMB()
{ {
u32 i = cpu->instruction; u32 i = cpu->instruction;
cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1)); cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));
@ -943,7 +946,22 @@ static u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu)
#define TYPE_RETOUR u32 #define TYPE_RETOUR u32
#define CALLTYPE FASTCALL #define CALLTYPE FASTCALL
#define PARAMETRES armcpu_t *cpu #define PARAMETRES
#define NOM_THUMB_TAB thumb_instructions_set #define NOM_THUMB_TAB thumb_instructions_set_0
#define TABDECL(x) x<0>
#include "thumb_tabdef.inc"
#undef TYPE_RETOUR
#undef PARAMETRES
#undef CALLTYPE
#undef NOM_THUMB_TAB
#undef TABDECL
#define TYPE_RETOUR u32
#define PARAMETRES
#define CALLTYPE FASTCALL
#define NOM_THUMB_TAB thumb_instructions_set_1
#define TABDECL(x) x<1>
#include "thumb_tabdef.inc" #include "thumb_tabdef.inc"

3
desmume/src/thumb_instructions.h
View File

@ -24,7 +24,8 @@
#include "armcpu.h" #include "armcpu.h"
extern u32 (FASTCALL* thumb_instructions_set[1024])(armcpu_t * cpu); extern u32 (FASTCALL* thumb_instructions_set_0[1024])();
extern u32 (FASTCALL* thumb_instructions_set_1[1024])();
#endif #endif

2048
desmume/src/thumb_tabdef.inc
View File

File diff suppressed because it is too large Load Diff

2
desmume/src/windows/DeSmuME_2005.vcproj
View File

@ -614,7 +614,7 @@
> >
</File> </File>
<File <File
RelativePath="..\gdbstub\gdbstub.c" RelativePath="..\gdbstub\gdbstub.cpp"
> >
</File> </File>
<File <File

59
desmume/src/windows/DeSmuME_2008.vcproj
View File

@ -1,7 +1,7 @@
<?xml version="1.0" encoding="shift_jis"?> <?xml version="1.0" encoding="shift_jis"?>
<VisualStudioProject <VisualStudioProject
ProjectType="Visual C++" ProjectType="Visual C++"
Version="9,00" Version="9.00"
Name="DeSmuME_VS2008" Name="DeSmuME_VS2008"
ProjectGUID="{9F5F72A1-D3A5-4918-B460-E076B16D10A9}" ProjectGUID="{9F5F72A1-D3A5-4918-B460-E076B16D10A9}"
RootNamespace="DeSmuME" RootNamespace="DeSmuME"
@ -197,7 +197,6 @@
IntermediateDirectory="$(SolutionDir)\.VS2008\$(ConfigurationName)\$(PlatformName)" IntermediateDirectory="$(SolutionDir)\.VS2008\$(ConfigurationName)\$(PlatformName)"
ConfigurationType="1" ConfigurationType="1"
InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops" InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
WholeProgramOptimization="1"
> >
<Tool <Tool
Name="VCPreBuildEventTool" Name="VCPreBuildEventTool"
@ -219,23 +218,21 @@
/> />
<Tool <Tool
Name="VCCLCompilerTool" Name="VCCLCompilerTool"
Optimization="2"
InlineFunctionExpansion="2" InlineFunctionExpansion="2"
EnableIntrinsicFunctions="true" EnableIntrinsicFunctions="true"
FavorSizeOrSpeed="1" FavorSizeOrSpeed="1"
OmitFramePointers="true"
EnableFiberSafeOptimizations="true" EnableFiberSafeOptimizations="true"
WholeProgramOptimization="true" WholeProgramOptimization="true"
AdditionalIncludeDirectories="..;.\zlib123;.\zziplib" AdditionalIncludeDirectories="..;.\zlib123;.\zziplib"
PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2\&quot;;WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION" PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2\&quot;;WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION"
StringPooling="true"
ExceptionHandling="0" ExceptionHandling="0"
BufferSecurityCheck="false" BufferSecurityCheck="false"
EnableEnhancedInstructionSet="0" EnableEnhancedInstructionSet="0"
FloatingPointModel="2"
WarningLevel="1" WarningLevel="1"
DebugInformationFormat="3" DebugInformationFormat="3"
CallingConvention="1" CallingConvention="0"
CompileAs="0" CompileAs="1"
/> />
<Tool <Tool
Name="VCManagedResourceCompilerTool" Name="VCManagedResourceCompilerTool"
@ -306,6 +303,7 @@
/> />
<Tool <Tool
Name="VCCLCompilerTool" Name="VCCLCompilerTool"
Optimization="2"
InlineFunctionExpansion="2" InlineFunctionExpansion="2"
EnableIntrinsicFunctions="true" EnableIntrinsicFunctions="true"
FavorSizeOrSpeed="1" FavorSizeOrSpeed="1"
@ -399,7 +397,7 @@
EnableFiberSafeOptimizations="true" EnableFiberSafeOptimizations="true"
WholeProgramOptimization="true" WholeProgramOptimization="true"
AdditionalIncludeDirectories="..;.\zlib123;.\zziplib" AdditionalIncludeDirectories="..;.\zlib123;.\zziplib"
PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2 SSE2\&quot;;WIN32;HAVE_LIBZ;HAVE_LIBZZIP;SSE2;BETA_VERSION" PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2 SSE2\&quot;;WIN32;SSE2;BETA_VERSION"
StringPooling="true" StringPooling="true"
ExceptionHandling="0" ExceptionHandling="0"
BufferSecurityCheck="false" BufferSecurityCheck="false"
@ -421,12 +419,13 @@
/> />
<Tool <Tool
Name="VCLinkerTool" Name="VCLinkerTool"
AdditionalDependencies="opengl32.lib glu32.lib ws2_32.lib user32.lib gdi32.lib dxguid.lib shell32.lib comdlg32.lib dxerr.lib dsound.lib dinput8.lib ddraw.lib zlib-2008-x32.lib zziplib-2008-x32.lib" AdditionalDependencies="opengl32.lib glu32.lib ws2_32.lib user32.lib gdi32.lib dxguid.lib shell32.lib comdlg32.lib dxerr.lib dsound.lib dinput8.lib ddraw.lib"
OutputFile="$(OutDir)\$(ProjectName)_sse2.exe" OutputFile="$(OutDir)\$(ProjectName)_sse2.exe"
AdditionalLibraryDirectories=".\zlib123;.\zziplib" AdditionalLibraryDirectories=".\zlib123;.\zziplib"
GenerateDebugInformation="true" GenerateDebugInformation="true"
RandomizedBaseAddress="1" RandomizedBaseAddress="1"
DataExecutionPrevention="0" DataExecutionPrevention="0"
Profile="true"
/> />
<Tool <Tool
Name="VCALinkTool" Name="VCALinkTool"
@ -479,6 +478,7 @@
/> />
<Tool <Tool
Name="VCCLCompilerTool" Name="VCCLCompilerTool"
Optimization="2"
InlineFunctionExpansion="2" InlineFunctionExpansion="2"
EnableIntrinsicFunctions="true" EnableIntrinsicFunctions="true"
FavorSizeOrSpeed="1" FavorSizeOrSpeed="1"
@ -512,6 +512,7 @@
RandomizedBaseAddress="1" RandomizedBaseAddress="1"
DataExecutionPrevention="0" DataExecutionPrevention="0"
TargetMachine="17" TargetMachine="17"
Profile="true"
/> />
<Tool <Tool
Name="VCALinkTool" Name="VCALinkTool"
@ -610,7 +611,7 @@
> >
</File> </File>
<File <File
RelativePath="..\gdbstub\gdbstub.c" RelativePath="..\gdbstub\gdbstub.cpp"
> >
</File> </File>
<File <File
@ -637,7 +638,7 @@
> >
<Tool <Tool
Name="VCCLCompilerTool" Name="VCCLCompilerTool"
CompileAs="0" CompileAs="1"
/> />
</FileConfiguration> </FileConfiguration>
<FileConfiguration <FileConfiguration
@ -747,14 +748,6 @@
Name="MASM" Name="MASM"
/> />
</FileConfiguration> </FileConfiguration>
<FileConfiguration
Name="Release|Win32"
ExcludedFromBuild="true"
>
<Tool
Name="MASM"
/>
</FileConfiguration>
<FileConfiguration <FileConfiguration
Name="Release|x64" Name="Release|x64"
ExcludedFromBuild="true" ExcludedFromBuild="true"
@ -811,26 +804,10 @@
<File <File
RelativePath="..\ROMReader.cpp" RelativePath="..\ROMReader.cpp"
> >
<FileConfiguration
Name="Release (SSE2)|Win32"
>
<Tool
Name="VCCLCompilerTool"
CallingConvention="1"
/>
</FileConfiguration>
</File> </File>
<File <File
RelativePath="..\saves.cpp" RelativePath="..\saves.cpp"
> >
<FileConfiguration
Name="Release (SSE2)|Win32"
>
<Tool
Name="VCCLCompilerTool"
CallingConvention="1"
/>
</FileConfiguration>
</File> </File>
<File <File
RelativePath=".\snddx.cpp" RelativePath=".\snddx.cpp"
@ -852,10 +829,6 @@
RelativePath="..\wifi.cpp" RelativePath="..\wifi.cpp"
> >
</File> </File>
<Filter
Name="windows"
>
</Filter>
</Filter> </Filter>
<Filter <Filter
Name="Header Files" Name="Header Files"
@ -1010,6 +983,10 @@
RelativePath=".\oamView.h" RelativePath=".\oamView.h"
> >
</File> </File>
<File
RelativePath=".\OGLRender.h"
>
</File>
<File <File
RelativePath=".\palView.h" RelativePath=".\palView.h"
> >
@ -1018,6 +995,10 @@
RelativePath="..\registers.h" RelativePath="..\registers.h"
> >
</File> </File>
<File
RelativePath="..\render3D.h"
>
</File>
<File <File
RelativePath=".\resource.h" RelativePath=".\resource.h"
> >