From f059cc7ae17b13c2584964409bbcd338fabf2ecf Mon Sep 17 00:00:00 2001
From: zeromus <zeromus@users.sf.net>
Date: Thu, 11 Sep 2008 06:02:44 +0000
Subject: [PATCH] Added a bunch of crazy templates to the cpu and mmu which
 speed up a the emu little by optimizing variable accesses

---
 desmume/ChangeLog                       |    1 +
 desmume/src/Disassembler.cpp            |    1 +
 desmume/src/MMU.cpp                     |   65 +-
 desmume/src/NDSSystem.cpp               |    6 +-
 desmume/src/arm_instructions.cpp        | 1117 +--
 desmume/src/arm_instructions.h          |    3 +-
 desmume/src/armcpu.cpp                  |   45 +-
 desmume/src/armcpu.h                    |   11 +-
 desmume/src/instruction_tabdef.inc      | 8192 +++++++++++------------
 desmume/src/thumb_instructions.cpp      |  162 +-
 desmume/src/thumb_instructions.h        |    3 +-
 desmume/src/thumb_tabdef.inc            | 2048 +++---
 desmume/src/windows/DeSmuME_2005.vcproj |    2 +-
 desmume/src/windows/DeSmuME_2008.vcproj |   59 +-
 14 files changed, 5903 insertions(+), 5812 deletions(-)

diff --git a/desmume/ChangeLog b/desmume/ChangeLog
index c168ed37f..3de165149 100644
--- a/desmume/ChangeLog
+++ b/desmume/ChangeLog
@@ -50,6 +50,7 @@
  - Tweak optimization flags and change entire source code to use fastcall [zeromus]
  - Add opengl state caching. This is of dubious performance assistance, but it is easy to take out so I am leaving it for now. [zeromus]
  - Add MMU->GPU signal for when vram mappings change, which allows it to assume textures are unchanged unless vram has changed [zeromus]
+ - Added a bunch of crazy templates to the cpu and mmu which speed up a the emu little by optimizing variable accesses [zeromus]
     
  
 0.7.3 -> 0.8
diff --git a/desmume/src/Disassembler.cpp b/desmume/src/Disassembler.cpp
index d816ac363..3aacbf018 100644
--- a/desmume/src/Disassembler.cpp
+++ b/desmume/src/Disassembler.cpp
@@ -3759,6 +3759,7 @@ static char * OP_BL_THUMB(u32 adr, u32 i, char * txt)
 #define CALLTYPE     
 #define NOM_TAB     des_arm_instructions_set
 #define NOM_THUMB_TAB     des_thumb_instructions_set
+#define TABDECL(x) x
 
 #include "instruction_tabdef.inc"
 #include "thumb_tabdef.inc"
diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp
index 8ba794009..5658198d5 100644
--- a/desmume/src/MMU.cpp
+++ b/desmume/src/MMU.cpp
@@ -584,7 +584,8 @@ void MMU_unsetRom()
 }
 char txt[80];	
 
-u8 FASTCALL MMU_read8(u32 proc, u32 adr)
+template<u32 proc>
+u8 FASTCALL _MMU_read8(u32 adr)
 {
 #ifdef INTERNAL_DTCM_READ
 	if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion))
@@ -617,9 +618,8 @@ u8 FASTCALL MMU_read8(u32 proc, u32 adr)
     return MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]];
 }
 
-
-
-u16 FASTCALL MMU_read16(u32 proc, u32 adr)
+template<u32 proc>
+u16 FASTCALL _MMU_read16(u32 adr)
 {    
 #ifdef INTERNAL_DTCM_READ
 	if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@@ -694,8 +694,9 @@ u16 FASTCALL MMU_read16(u32 proc, u32 adr)
 	/* Returns data from memory */
 	return T1ReadWord(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]); 
 }
-	 
-u32 FASTCALL MMU_read32(u32 proc, u32 adr)
+
+template<u32 proc>
+u32 FASTCALL _MMU_read32(u32 adr)
 {
 #ifdef INTERNAL_DTCM_READ
 	if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@@ -714,7 +715,6 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr)
 	// CFlash reading, Mic
 	if ((adr>=0x9000000)&&(adr<0x9900000))
 	   return (unsigned long)cflash_read(adr);
-		
 	adr &= 0x0FFFFFFF;
 
 	if((adr >> 24) == 4)
@@ -848,13 +848,15 @@ u32 FASTCALL MMU_read32(u32 proc, u32 adr)
 		}
 	}
 	
-	/* Returns data from memory */
-	return T1ReadLong(MMU.MMU_MEM[proc][(adr >> 20) & 0xFF], adr & MMU.MMU_MASK[proc][(adr >> 20) & 0xFF]);
+	//Returns data from memory
+	// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [zeromus, inspired by shash]
+	return T1ReadLong(MMU.MMU_MEM[proc][(adr >> 20)], adr & MMU.MMU_MASK[proc][(adr >> 20)]);
 }
 
 #define OFS(i)	((i>>3)&3)
 	
-void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
+template<u32 proc>
+void FASTCALL _MMU_write8(u32 adr, u8 val)
 {
 #ifdef INTERNAL_DTCM_WRITE
 	if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@@ -1242,7 +1244,8 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
 
 u16 partie = 1;
 
-void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
+template<u32 proc>
+void FASTCALL _MMU_write16(u32 adr, u16 val)
 {
 #ifdef INTERNAL_DTCM_WRITE
 	if((proc == ARMCPU_ARM9) && ((adr & ~0x3FFF) == MMU.DTCMRegion))
@@ -1905,7 +1908,8 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
 } 
 
 
-void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
+template<u32 proc>
+void FASTCALL _MMU_write32(u32 adr, u32 val)
 {
 #ifdef INTERNAL_DTCM_WRITE
 	if((proc==ARMCPU_ARM9)&((adr&(~0x3FFF))==MMU.DTCMRegion))
@@ -3534,3 +3538,40 @@ struct armcpu_memory_iface arm9_direct_memory_iface = {
   arm9_write16,
   arm9_write32
 };
+
+
+u32 FASTCALL MMU_read32(u32 proc, u32 adr) 
+{
+	if(proc==0) return _MMU_read32<0ul>(adr);
+	else return _MMU_read32<1ul>(adr);
+}
+
+u16 FASTCALL MMU_read16(u32 proc, u32 adr) 
+{
+	if(proc==0) return _MMU_read16<0ul>(adr);
+	else return _MMU_read16<1ul>(adr);
+}
+
+u8 FASTCALL MMU_read8(u32 proc, u32 adr) 
+{
+	if(proc==0) return _MMU_read8<0ul>(adr);
+	else return _MMU_read8<1ul>(adr);
+}
+
+void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
+{
+	if(proc==0) _MMU_write32<0ul>(adr,val);
+	else _MMU_write32<1ul>(adr,val);
+}
+
+void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
+{
+	if(proc==0) _MMU_write16<0ul>(adr,val);
+	else _MMU_write16<1ul>(adr,val);
+}
+
+void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
+{
+	if(proc==0) _MMU_write8<0ul>(adr,val);
+	else _MMU_write8<1ul>(adr,val);
+}
diff --git a/desmume/src/NDSSystem.cpp b/desmume/src/NDSSystem.cpp
index 31f350d70..887be2794 100644
--- a/desmume/src/NDSSystem.cpp
+++ b/desmume/src/NDSSystem.cpp
@@ -891,7 +891,8 @@ NDS_exec(s32 nb, BOOL force)
 						nds.ARM9Cycle += 100;
 					else
 						//nds.ARM9Cycle += NDS_ARM9.exec();
-						nds.ARM9Cycle += armcpu_exec(&NDS_ARM9);
+						//nds.ARM9Cycle += armcpu_exec(&NDS_ARM9);
+						nds.ARM9Cycle += armcpu_exec<0>();
 				}
 			}
 
@@ -924,7 +925,8 @@ NDS_exec(s32 nb, BOOL force)
 						nds.ARM7Cycle += 100;
 					else
 						//nds.ARM7Cycle += (NDS_ARM7.exec()<<1);
-						nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1);
+						//nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1);
+						nds.ARM7Cycle += (armcpu_exec<1>()<<1);
 				}
 			}
 		}
diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp
index 85d6e8ccc..4b167904f 100644
--- a/desmume/src/arm_instructions.cpp
+++ b/desmume/src/arm_instructions.cpp
@@ -30,6 +30,10 @@
 #include "cp15.h"
 #include "debug.h"
 #include "MMU.h"
+#include "armcpu.h"
+
+#define cpu (&ARMPROC)
+#define TEMPLATE template<int PROCNUM> 
 
 extern volatile BOOL execute;
 
@@ -42,8 +46,8 @@ extern volatile BOOL execute;
 	#define READ8(a,b)		cpu->mem_if->read8(a,b)
 	#define WRITE8(a,b,c)	cpu->mem_if->write8(a,b,c)
 #else
-	#define READ32(a,b)		MMU_read32(cpu->proc_ID, b)
-	#define WRITE32(a,b,c)	MMU_write32(cpu->proc_ID,b,c)
+	#define READ32(a,b)		MMU_read32(PROCNUM, b)
+	#define WRITE32(a,b,c)	MMU_write32(PROCNUM,b,c)
 	#define READ16(a,b)		MMU_read16(cpu->proc_ID, b)
 	#define WRITE16(a,b,c)	MMU_write16(cpu->proc_ID,b,c)
 	#define READ8(a,b)		MMU_read8(cpu->proc_ID, b)
@@ -241,7 +245,7 @@ extern volatile BOOL execute;
 
 #define IMM_OFF_12 ((i)&0xFFF)
 
-static u32 FASTCALL  OP_UND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_UND()
 {
 	u32 i = cpu->instruction;
 	LOG("Undefined instruction: %08X\n", i);
@@ -278,7 +282,7 @@ static u32 FASTCALL  OP_UND(armcpu_t *cpu)
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
      return a;
  
-static u32 FASTCALL  OP_AND_LSL_IMM(register armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -286,14 +290,14 @@ static u32 FASTCALL  OP_AND_LSL_IMM(register armcpu_t *cpu)
      OP_AND(1, 3);
 }
 
-static u32 FASTCALL  OP_AND_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_AND(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -301,14 +305,14 @@ static u32 FASTCALL  OP_AND_LSR_IMM(armcpu_t *cpu)
      OP_AND(1, 3);
 }
 
-static u32 FASTCALL  OP_AND_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_AND(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -316,14 +320,14 @@ static u32 FASTCALL  OP_AND_ASR_IMM(armcpu_t *cpu)
      OP_AND(1, 3);
 }
 
-static u32 FASTCALL  OP_AND_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_AND(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -331,77 +335,77 @@ static u32 FASTCALL  OP_AND_ROR_IMM(armcpu_t *cpu)
      OP_AND(1, 3);
 }
 
-static u32 FASTCALL  OP_AND_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_AND(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OP_AND(1, 3);
 }
 
-static u32 FASTCALL  OP_AND_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_ANDS(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OP_ANDS(3, 5);
 }
 
-static u32 FASTCALL  OP_AND_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OP_ANDS(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;             
      OP_ANDS(3, 5);
 }
 
-static u32 FASTCALL  OP_AND_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_ANDS(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;                     
      OP_ANDS(3, 5);
 }
 
-static u32 FASTCALL  OP_AND_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_ANDS(2, 4);
 }
 
-static u32 FASTCALL  OP_AND_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_ANDS(3, 5);
 }
 
-static u32 FASTCALL  OP_AND_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_AND_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -433,7 +437,7 @@ static u32 FASTCALL  OP_AND_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
      return a;
 
-static u32 FASTCALL  OP_EOR_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -441,14 +445,14 @@ static u32 FASTCALL  OP_EOR_LSL_IMM(armcpu_t *cpu)
      OP_EOR(1, 3); 
 }
 
-static u32 FASTCALL  OP_EOR_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_EOR(2, 4); 
 }
 
-static u32 FASTCALL  OP_EOR_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -456,14 +460,14 @@ static u32 FASTCALL  OP_EOR_LSR_IMM(armcpu_t *cpu)
      OP_EOR(1, 3); 
 }
 
-static u32 FASTCALL  OP_EOR_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_EOR(2, 4); 
 }
 
-static u32 FASTCALL  OP_EOR_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -471,14 +475,14 @@ static u32 FASTCALL  OP_EOR_ASR_IMM(armcpu_t *cpu)
      OP_EOR(1, 3); 
 }
 
-static u32 FASTCALL  OP_EOR_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_EOR(2, 4); 
 }
 
-static u32 FASTCALL  OP_EOR_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -486,77 +490,77 @@ static u32 FASTCALL  OP_EOR_ROR_IMM(armcpu_t *cpu)
      OP_EOR(1, 3); 
 }
 
-static u32 FASTCALL  OP_EOR_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_EOR(2, 4); 
 }
 
-static u32 FASTCALL  OP_EOR_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OP_EOR(1, 3); 
 }
 
-static u32 FASTCALL  OP_EOR_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_EORS(2, 4);
 }
 
-static u32 FASTCALL  OP_EOR_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OP_EORS(3, 5);
 }
 
-static u32 FASTCALL  OP_EOR_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OP_EORS(2, 4);
 }
 
-static u32 FASTCALL  OP_EOR_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;            
      OP_EORS(3, 5);
 }
 
-static u32 FASTCALL  OP_EOR_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_EORS(2, 4);
 }
 
-static u32 FASTCALL  OP_EOR_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;                     
      OP_EORS(3, 5);
 }
 
-static u32 FASTCALL  OP_EOR_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_EORS(2, 4);
 }
 
-static u32 FASTCALL  OP_EOR_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_EORS(3, 5);
 }
 
-static u32 FASTCALL  OP_EOR_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_EOR_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -589,7 +593,7 @@ static u32 FASTCALL  OP_EOR_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.V = SIGNED_UNDERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
      return a;
 
-static u32 FASTCALL  OP_SUB_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -597,14 +601,14 @@ static u32 FASTCALL  OP_SUB_LSL_IMM(armcpu_t *cpu)
      OP_SUB(1, 3);
 }
 
-static u32 FASTCALL  OP_SUB_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_SUB(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -612,14 +616,14 @@ static u32 FASTCALL  OP_SUB_LSR_IMM(armcpu_t *cpu)
      OP_SUB(1, 3);
 }
 
-static u32 FASTCALL  OP_SUB_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_SUB(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -627,14 +631,14 @@ static u32 FASTCALL  OP_SUB_ASR_IMM(armcpu_t *cpu)
      OP_SUB(1, 3);
 }
 
-static u32 FASTCALL  OP_SUB_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_SUB(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -642,21 +646,21 @@ static u32 FASTCALL  OP_SUB_ROR_IMM(armcpu_t *cpu)
      OP_SUB(1, 3);
 }
 
-static u32 FASTCALL  OP_SUB_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_SUB(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OP_SUB(1, 3);
 }
 
-static u32 FASTCALL  OP_SUB_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -665,7 +669,7 @@ static u32 FASTCALL  OP_SUB_S_LSL_IMM(armcpu_t *cpu)
      OPSUBS(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -673,7 +677,7 @@ static u32 FASTCALL  OP_SUB_S_LSL_REG(armcpu_t *cpu)
      OPSUBS(3, 5);
 }
 
-static u32 FASTCALL  OP_SUB_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -682,7 +686,7 @@ static u32 FASTCALL  OP_SUB_S_LSR_IMM(armcpu_t *cpu)
      OPSUBS(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -690,7 +694,7 @@ static u32 FASTCALL  OP_SUB_S_LSR_REG(armcpu_t *cpu)
      OPSUBS(3, 5);
 }
 
-static u32 FASTCALL  OP_SUB_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -699,7 +703,7 @@ static u32 FASTCALL  OP_SUB_S_ASR_IMM(armcpu_t *cpu)
      OPSUBS(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -707,7 +711,7 @@ static u32 FASTCALL  OP_SUB_S_ASR_REG(armcpu_t *cpu)
      OPSUBS(3, 5);
 }
 
-static u32 FASTCALL  OP_SUB_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -716,7 +720,7 @@ static u32 FASTCALL  OP_SUB_S_ROR_IMM(armcpu_t *cpu)
      OPSUBS(2, 4);
 }
 
-static u32 FASTCALL  OP_SUB_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -724,7 +728,7 @@ static u32 FASTCALL  OP_SUB_S_ROR_REG(armcpu_t *cpu)
      OPSUBS(3, 5);
 }
 
-static u32 FASTCALL  OP_SUB_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SUB_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -758,7 +762,7 @@ static u32 FASTCALL  OP_SUB_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.V = SIGNED_UNDERFLOW(shift_op, v, cpu->R[REG_POS(i,12)]);\
      return a;
      
-static u32 FASTCALL  OP_RSB_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -766,14 +770,14 @@ static u32 FASTCALL  OP_RSB_LSL_IMM(armcpu_t *cpu)
      OP_RSB(1, 3);
 }
 
-static u32 FASTCALL  OP_RSB_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_RSB(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -781,14 +785,14 @@ static u32 FASTCALL  OP_RSB_LSR_IMM(armcpu_t *cpu)
      OP_RSB(1, 3);
 }
 
-static u32 FASTCALL  OP_RSB_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_RSB(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -796,14 +800,14 @@ static u32 FASTCALL  OP_RSB_ASR_IMM(armcpu_t *cpu)
      OP_RSB(1, 3);
 }
 
-static u32 FASTCALL  OP_RSB_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_RSB(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -811,21 +815,21 @@ static u32 FASTCALL  OP_RSB_ROR_IMM(armcpu_t *cpu)
      OP_RSB(1, 3);
 }
 
-static u32 FASTCALL  OP_RSB_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_RSB(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OP_RSB(1, 3);
 }
 
-static u32 FASTCALL  OP_RSB_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -834,7 +838,7 @@ static u32 FASTCALL  OP_RSB_S_LSL_IMM(armcpu_t *cpu)
      OP_RSBS(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -842,7 +846,7 @@ static u32 FASTCALL  OP_RSB_S_LSL_REG(armcpu_t *cpu)
      OP_RSBS(3, 5);
 }
 
-static u32 FASTCALL  OP_RSB_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -851,7 +855,7 @@ static u32 FASTCALL  OP_RSB_S_LSR_IMM(armcpu_t *cpu)
      OP_RSBS(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -859,7 +863,7 @@ static u32 FASTCALL  OP_RSB_S_LSR_REG(armcpu_t *cpu)
      OP_RSBS(3, 5);
 }
 
-static u32 FASTCALL  OP_RSB_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -868,7 +872,7 @@ static u32 FASTCALL  OP_RSB_S_ASR_IMM(armcpu_t *cpu)
      OP_RSBS(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -876,7 +880,7 @@ static u32 FASTCALL  OP_RSB_S_ASR_REG(armcpu_t *cpu)
      OP_RSBS(3, 5);
 }
 
-static u32 FASTCALL  OP_RSB_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -885,7 +889,7 @@ static u32 FASTCALL  OP_RSB_S_ROR_IMM(armcpu_t *cpu)
      OP_RSBS(2, 4);
 }
 
-static u32 FASTCALL  OP_RSB_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -893,7 +897,7 @@ static u32 FASTCALL  OP_RSB_S_ROR_REG(armcpu_t *cpu)
      OP_RSBS(3, 5);
 }
 
-static u32 FASTCALL  OP_RSB_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSB_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -911,7 +915,7 @@ static u32 FASTCALL  OP_RSB_S_IMM_VAL(armcpu_t *cpu)
      }\
      return a;
 
-static u32 FASTCALL  OP_ADD_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -919,14 +923,14 @@ static u32 FASTCALL  OP_ADD_LSL_IMM(armcpu_t *cpu)
      OP_ADD(1, 3);
 }
 
-static u32 FASTCALL  OP_ADD_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_ADD(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -934,14 +938,14 @@ static u32 FASTCALL  OP_ADD_LSR_IMM(armcpu_t *cpu)
      OP_ADD(1, 3);
 }
 
-static u32 FASTCALL  OP_ADD_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_ADD(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -949,14 +953,14 @@ static u32 FASTCALL  OP_ADD_ASR_IMM(armcpu_t *cpu)
      OP_ADD(1, 3);
 }
 
-static u32 FASTCALL  OP_ADD_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_ADD(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -964,14 +968,14 @@ static u32 FASTCALL  OP_ADD_ROR_IMM(armcpu_t *cpu)
      OP_ADD(1, 3);
 }
 
-static u32 FASTCALL  OP_ADD_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_ADD(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -994,7 +998,7 @@ static u32 FASTCALL  OP_ADD_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.V = SIGNED_OVERFLOW(v, shift_op, cpu->R[REG_POS(i,12)]);\
      return a;
      
-static u32 FASTCALL  OP_ADD_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1003,7 +1007,7 @@ static u32 FASTCALL  OP_ADD_S_LSL_IMM(armcpu_t *cpu)
      OP_ADDS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1011,7 +1015,7 @@ static u32 FASTCALL  OP_ADD_S_LSL_REG(armcpu_t *cpu)
      OP_ADDS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADD_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1020,7 +1024,7 @@ static u32 FASTCALL  OP_ADD_S_LSR_IMM(armcpu_t *cpu)
      OP_ADDS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1028,7 +1032,7 @@ static u32 FASTCALL  OP_ADD_S_LSR_REG(armcpu_t *cpu)
      OP_ADDS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADD_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1037,7 +1041,7 @@ static u32 FASTCALL  OP_ADD_S_ASR_IMM(armcpu_t *cpu)
      OP_ADDS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1045,7 +1049,7 @@ static u32 FASTCALL  OP_ADD_S_ASR_REG(armcpu_t *cpu)
      OP_ADDS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADD_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1054,7 +1058,7 @@ static u32 FASTCALL  OP_ADD_S_ROR_IMM(armcpu_t *cpu)
      OP_ADDS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADD_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1062,7 +1066,7 @@ static u32 FASTCALL  OP_ADD_S_ROR_REG(armcpu_t *cpu)
      OP_ADDS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADD_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADD_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1080,7 +1084,7 @@ static u32 FASTCALL  OP_ADD_S_IMM_VAL(armcpu_t *cpu)
      }\
      return a;
      
-static u32 FASTCALL  OP_ADC_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1088,14 +1092,14 @@ static u32 FASTCALL  OP_ADC_LSL_IMM(armcpu_t *cpu)
      OP_ADC(1, 3);
 }
 
-static u32 FASTCALL  OP_ADC_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_ADC(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1103,14 +1107,14 @@ static u32 FASTCALL  OP_ADC_LSR_IMM(armcpu_t *cpu)
      OP_ADC(1, 3);
 }
 
-static u32 FASTCALL  OP_ADC_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_ADC(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1118,14 +1122,14 @@ static u32 FASTCALL  OP_ADC_ASR_IMM(armcpu_t *cpu)
      OP_ADC(1, 3);
 }
 
-static u32 FASTCALL  OP_ADC_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_ADC(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1133,14 +1137,14 @@ static u32 FASTCALL  OP_ADC_ROR_IMM(armcpu_t *cpu)
      OP_ADC(1, 3);
 }
 
-static u32 FASTCALL  OP_ADC_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_ADC(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1167,7 +1171,7 @@ static u32 FASTCALL  OP_ADC_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
      
-static u32 FASTCALL  OP_ADC_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1176,7 +1180,7 @@ static u32 FASTCALL  OP_ADC_S_LSL_IMM(armcpu_t *cpu)
      OP_ADCS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1184,7 +1188,7 @@ static u32 FASTCALL  OP_ADC_S_LSL_REG(armcpu_t *cpu)
      OP_ADCS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADC_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1193,7 +1197,7 @@ static u32 FASTCALL  OP_ADC_S_LSR_IMM(armcpu_t *cpu)
      OP_ADCS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1201,7 +1205,7 @@ static u32 FASTCALL  OP_ADC_S_LSR_REG(armcpu_t *cpu)
      OP_ADCS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADC_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1210,7 +1214,7 @@ static u32 FASTCALL  OP_ADC_S_ASR_IMM(armcpu_t *cpu)
      OP_ADCS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1218,7 +1222,7 @@ static u32 FASTCALL  OP_ADC_S_ASR_REG(armcpu_t *cpu)
      OP_ADCS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADC_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1227,7 +1231,7 @@ static u32 FASTCALL  OP_ADC_S_ROR_IMM(armcpu_t *cpu)
      OP_ADCS(2, 4);
 }
 
-static u32 FASTCALL  OP_ADC_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1235,7 +1239,7 @@ static u32 FASTCALL  OP_ADC_S_ROR_REG(armcpu_t *cpu)
      OP_ADCS(3, 5);
 }
 
-static u32 FASTCALL  OP_ADC_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ADC_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1253,7 +1257,7 @@ static u32 FASTCALL  OP_ADC_S_IMM_VAL(armcpu_t *cpu)
      }\
      return a;
      
-static u32 FASTCALL  OP_SBC_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1261,14 +1265,14 @@ static u32 FASTCALL  OP_SBC_LSL_IMM(armcpu_t *cpu)
      OP_SBC(1, 3);
 }
 
-static u32 FASTCALL  OP_SBC_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_SBC(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1276,14 +1280,14 @@ static u32 FASTCALL  OP_SBC_LSR_IMM(armcpu_t *cpu)
      OP_SBC(1, 3);
 }
 
-static u32 FASTCALL  OP_SBC_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_SBC(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1291,14 +1295,14 @@ static u32 FASTCALL  OP_SBC_ASR_IMM(armcpu_t *cpu)
      OP_SBC(1, 3);
 }
 
-static u32 FASTCALL  OP_SBC_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_SBC(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1306,14 +1310,14 @@ static u32 FASTCALL  OP_SBC_ROR_IMM(armcpu_t *cpu)
      OP_SBC(1, 3);
 }
 
-static u32 FASTCALL  OP_SBC_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_SBC(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1340,7 +1344,7 @@ static u32 FASTCALL  OP_SBC_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
 
-static u32 FASTCALL  OP_SBC_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1349,7 +1353,7 @@ static u32 FASTCALL  OP_SBC_S_LSL_IMM(armcpu_t *cpu)
      OP_SBCS(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1357,7 +1361,7 @@ static u32 FASTCALL  OP_SBC_S_LSL_REG(armcpu_t *cpu)
      OP_SBCS(3, 5);
 }
 
-static u32 FASTCALL  OP_SBC_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1366,7 +1370,7 @@ static u32 FASTCALL  OP_SBC_S_LSR_IMM(armcpu_t *cpu)
      OP_SBCS(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1374,7 +1378,7 @@ static u32 FASTCALL  OP_SBC_S_LSR_REG(armcpu_t *cpu)
      OP_SBCS(3, 5);
 }
 
-static u32 FASTCALL  OP_SBC_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1383,7 +1387,7 @@ static u32 FASTCALL  OP_SBC_S_ASR_IMM(armcpu_t *cpu)
      OP_SBCS(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1391,7 +1395,7 @@ static u32 FASTCALL  OP_SBC_S_ASR_REG(armcpu_t *cpu)
      OP_SBCS(3, 5);
 }
 
-static u32 FASTCALL  OP_SBC_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1400,7 +1404,7 @@ static u32 FASTCALL  OP_SBC_S_ROR_IMM(armcpu_t *cpu)
      OP_SBCS(2, 4);
 }
 
-static u32 FASTCALL  OP_SBC_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1408,7 +1412,7 @@ static u32 FASTCALL  OP_SBC_S_ROR_REG(armcpu_t *cpu)
      OP_SBCS(3, 5);
 }
 
-static u32 FASTCALL  OP_SBC_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SBC_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1426,7 +1430,7 @@ static u32 FASTCALL  OP_SBC_S_IMM_VAL(armcpu_t *cpu)
      }\
      return a;
      
-static u32 FASTCALL  OP_RSC_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1434,14 +1438,14 @@ static u32 FASTCALL  OP_RSC_LSL_IMM(armcpu_t *cpu)
      OP_RSC(1, 3);
 }
 
-static u32 FASTCALL  OP_RSC_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_RSC(2, 4);
 }
 
-static u32 FASTCALL  OP_RSC_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1449,14 +1453,14 @@ static u32 FASTCALL  OP_RSC_LSR_IMM(armcpu_t *cpu)
      OP_RSC(1, 3);
 }
 
-static u32 FASTCALL  OP_RSC_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_RSC(2, 4);
 }
 
-static u32 FASTCALL  OP_RSC_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1464,14 +1468,14 @@ static u32 FASTCALL  OP_RSC_ASR_IMM(armcpu_t *cpu)
      OP_RSC(1, 3);
 }
 
-static u32 FASTCALL  OP_RSC_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_RSC(2, 4);
 }
 
-static u32 FASTCALL  OP_RSC_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1479,14 +1483,14 @@ static u32 FASTCALL  OP_RSC_ROR_IMM(armcpu_t *cpu)
      OP_RSC(1, 3);
 }
 
-static u32 FASTCALL  OP_RSC_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_RSC(2, 4);
 }
 
-static u32 FASTCALL  OP_RSC_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1513,7 +1517,7 @@ static u32 FASTCALL  OP_RSC_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
 
-static u32 FASTCALL  OP_RSC_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1522,7 +1526,7 @@ static u32 FASTCALL  OP_RSC_S_LSL_IMM(armcpu_t *cpu)
      OP_RSCS(2,4);
 }
 
-static u32 FASTCALL  OP_RSC_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1530,7 +1534,7 @@ static u32 FASTCALL  OP_RSC_S_LSL_REG(armcpu_t *cpu)
      OP_RSCS(3,5);
 }
 
-static u32 FASTCALL  OP_RSC_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1539,7 +1543,7 @@ static u32 FASTCALL  OP_RSC_S_LSR_IMM(armcpu_t *cpu)
      OP_RSCS(2,4);
 }
 
-static u32 FASTCALL  OP_RSC_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1547,7 +1551,7 @@ static u32 FASTCALL  OP_RSC_S_LSR_REG(armcpu_t *cpu)
      OP_RSCS(3,5);
 }
 
-static u32 FASTCALL  OP_RSC_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1556,7 +1560,7 @@ static u32 FASTCALL  OP_RSC_S_ASR_IMM(armcpu_t *cpu)
      OP_RSCS(2,4);
 }
 
-static u32 FASTCALL  OP_RSC_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1564,7 +1568,7 @@ static u32 FASTCALL  OP_RSC_S_ASR_REG(armcpu_t *cpu)
      OP_RSCS(3,5);
 }
 
-static u32 FASTCALL  OP_RSC_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1573,7 +1577,7 @@ static u32 FASTCALL  OP_RSC_S_ROR_IMM(armcpu_t *cpu)
      OP_RSCS(2,4);
 }
 
-static u32 FASTCALL  OP_RSC_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1581,7 +1585,7 @@ static u32 FASTCALL  OP_RSC_S_ROR_REG(armcpu_t *cpu)
      OP_RSCS(3,5);
 }
 
-static u32 FASTCALL  OP_RSC_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_RSC_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,16)];
@@ -1600,63 +1604,63 @@ static u32 FASTCALL  OP_RSC_S_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
      
-static u32 FASTCALL  OP_TST_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_TST(1);
 }
 
-static u32 FASTCALL  OP_TST_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OP_TST(2);
 }
 
-static u32 FASTCALL  OP_TST_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OP_TST(1);
 }
 
-static u32 FASTCALL  OP_TST_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;             
      OP_TST(2);
 }
 
-static u32 FASTCALL  OP_TST_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_TST(1);
 }
 
-static u32 FASTCALL  OP_TST_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;                     
      OP_TST(2);
 }
 
-static u32 FASTCALL  OP_TST_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_TST(1);
 }
 
-static u32 FASTCALL  OP_TST_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_TST(2);
 }
 
-static u32 FASTCALL  OP_TST_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TST_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -1674,63 +1678,63 @@ static u32 FASTCALL  OP_TST_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
      
-static u32 FASTCALL  OP_TEQ_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_TEQ(1);
 }
 
-static u32 FASTCALL  OP_TEQ_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OP_TEQ(2);
 }
 
-static u32 FASTCALL  OP_TEQ_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OP_TEQ(1);
 }
 
-static u32 FASTCALL  OP_TEQ_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;             
      OP_TEQ(2);
 }
 
-static u32 FASTCALL  OP_TEQ_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_TEQ(1);
 }
 
-static u32 FASTCALL  OP_TEQ_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;                     
      OP_TEQ(2);
 }
 
-static u32 FASTCALL  OP_TEQ_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_TEQ(1);
 }
 
-static u32 FASTCALL  OP_TEQ_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_TEQ(2);
 }
 
-static u32 FASTCALL  OP_TEQ_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_TEQ_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -1749,7 +1753,7 @@ static u32 FASTCALL  OP_TEQ_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
      
-static u32 FASTCALL  OP_CMP_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1757,14 +1761,14 @@ static u32 FASTCALL  OP_CMP_LSL_IMM(armcpu_t *cpu)
      OP_CMP(1);
 }
 
-static u32 FASTCALL  OP_CMP_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_CMP(2);
 }
 
-static u32 FASTCALL  OP_CMP_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1772,14 +1776,14 @@ static u32 FASTCALL  OP_CMP_LSR_IMM(armcpu_t *cpu)
      OP_CMP(1);
 }
 
-static u32 FASTCALL  OP_CMP_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_CMP(2);
 }
 
-static u32 FASTCALL  OP_CMP_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1787,14 +1791,14 @@ static u32 FASTCALL  OP_CMP_ASR_IMM(armcpu_t *cpu)
      OP_CMP(1);
 }
 
-static u32 FASTCALL  OP_CMP_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_CMP(2);
 }
 
-static u32 FASTCALL  OP_CMP_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1802,14 +1806,14 @@ static u32 FASTCALL  OP_CMP_ROR_IMM(armcpu_t *cpu)
      OP_CMP(1);
 }
 
-static u32 FASTCALL  OP_CMP_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_CMP(2);
 }
 
-static u32 FASTCALL  OP_CMP_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMP_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1828,7 +1832,7 @@ static u32 FASTCALL  OP_CMP_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
 
-static u32 FASTCALL  OP_CMN_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1836,14 +1840,14 @@ static u32 FASTCALL  OP_CMN_LSL_IMM(armcpu_t *cpu)
      OP_CMN(1);
 }
 
-static u32 FASTCALL  OP_CMN_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_CMN(2);
 }
 
-static u32 FASTCALL  OP_CMN_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1851,14 +1855,14 @@ static u32 FASTCALL  OP_CMN_LSR_IMM(armcpu_t *cpu)
      OP_CMN(1);
 }
 
-static u32 FASTCALL  OP_CMN_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_CMN(2);
 }
 
-static u32 FASTCALL  OP_CMN_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1866,14 +1870,14 @@ static u32 FASTCALL  OP_CMN_ASR_IMM(armcpu_t *cpu)
      OP_CMN(1);
 }
 
-static u32 FASTCALL  OP_CMN_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_CMN(2);
 }
 
-static u32 FASTCALL  OP_CMN_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1881,14 +1885,14 @@ static u32 FASTCALL  OP_CMN_ROR_IMM(armcpu_t *cpu)
      OP_CMN(1);
 }
 
-static u32 FASTCALL  OP_CMN_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_CMN(2);
 }
 
-static u32 FASTCALL  OP_CMN_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CMN_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1905,7 +1909,7 @@ static u32 FASTCALL  OP_CMN_IMM_VAL(armcpu_t *cpu)
      }\
      return a;
 
-static u32 FASTCALL  OP_ORR_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1913,14 +1917,14 @@ static u32 FASTCALL  OP_ORR_LSL_IMM(armcpu_t *cpu)
      OP_ORR(1, 3);
 }
 
-static u32 FASTCALL  OP_ORR_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OP_ORR(2, 4);
 }
 
-static u32 FASTCALL  OP_ORR_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1928,14 +1932,14 @@ static u32 FASTCALL  OP_ORR_LSR_IMM(armcpu_t *cpu)
      OP_ORR(1, 3);
 }
 
-static u32 FASTCALL  OP_ORR_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OP_ORR(2, 4);
 }
 
-static u32 FASTCALL  OP_ORR_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1943,14 +1947,14 @@ static u32 FASTCALL  OP_ORR_ASR_IMM(armcpu_t *cpu)
      OP_ORR(1, 3);
 }
 
-static u32 FASTCALL  OP_ORR_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_ORR(2, 4);
 }
 
-static u32 FASTCALL  OP_ORR_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -1958,14 +1962,14 @@ static u32 FASTCALL  OP_ORR_ROR_IMM(armcpu_t *cpu)
      OP_ORR(1, 3);
 }
 
-static u32 FASTCALL  OP_ORR_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_ORR(2, 4);
 }
 
-static u32 FASTCALL  OP_ORR_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -1990,63 +1994,63 @@ static u32 FASTCALL  OP_ORR_IMM_VAL(armcpu_t *cpu)
      return a; \
      }
 
-static u32 FASTCALL  OP_ORR_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_ORRS(2,4);
 }
 
-static u32 FASTCALL  OP_ORR_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OP_ORRS(3,5);
 }
 
-static u32 FASTCALL  OP_ORR_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OP_ORRS(2,4);
 }
 
-static u32 FASTCALL  OP_ORR_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;             
      OP_ORRS(3,5);
 }
 
-static u32 FASTCALL  OP_ORR_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_ORRS(2,4);
 }
 
-static u32 FASTCALL  OP_ORR_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;                     
      OP_ORRS(3,5);
 }
 
-static u32 FASTCALL  OP_ORR_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_ORRS(2,4);
 }
 
-static u32 FASTCALL  OP_ORR_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_ORRS(3,5);
 }
 
-static u32 FASTCALL  OP_ORR_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_ORR_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -2078,7 +2082,7 @@ static u32 FASTCALL  OP_ORR_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
      return a;\
 
-static u32 FASTCALL  OP_MOV_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2086,7 +2090,7 @@ static u32 FASTCALL  OP_MOV_LSL_IMM(armcpu_t *cpu)
      OP_MOV(1,3);
 }
 
-static u32 FASTCALL  OP_MOV_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
@@ -2094,7 +2098,7 @@ static u32 FASTCALL  OP_MOV_LSL_REG(armcpu_t *cpu)
      OP_MOV(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2102,7 +2106,7 @@ static u32 FASTCALL  OP_MOV_LSR_IMM(armcpu_t *cpu)
      OP_MOV(1,3);
 }
 
-static u32 FASTCALL  OP_MOV_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;  
@@ -2110,7 +2114,7 @@ static u32 FASTCALL  OP_MOV_LSR_REG(armcpu_t *cpu)
      OP_MOV(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2118,14 +2122,14 @@ static u32 FASTCALL  OP_MOV_ASR_IMM(armcpu_t *cpu)
      OP_MOV(1,3);
 }
 
-static u32 FASTCALL  OP_MOV_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OP_MOV(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2133,28 +2137,28 @@ static u32 FASTCALL  OP_MOV_ROR_IMM(armcpu_t *cpu)
      OP_MOV(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OP_MOV(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OP_MOV(1,3);
 }
 
-static u32 FASTCALL  OP_MOV_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OP_MOV_S(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
@@ -2162,14 +2166,14 @@ static u32 FASTCALL  OP_MOV_S_LSL_REG(armcpu_t *cpu)
      OP_MOV_S(3,5);
 }
 
-static u32 FASTCALL  OP_MOV_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;   
      OP_MOV_S(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;  
@@ -2177,35 +2181,35 @@ static u32 FASTCALL  OP_MOV_S_LSR_REG(armcpu_t *cpu)
      OP_MOV_S(3,5);           
 }
 
-static u32 FASTCALL  OP_MOV_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OP_MOV_S(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;  
      OP_MOV_S(3,5);                   
 }
 
-static u32 FASTCALL  OP_MOV_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OP_MOV_S(2,4);
 }
 
-static u32 FASTCALL  OP_MOV_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OP_MOV_S(3,5);
 }
 
-static u32 FASTCALL  OP_MOV_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MOV_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -2236,7 +2240,7 @@ static u32 FASTCALL  OP_MOV_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
      return a;
      
-static u32 FASTCALL  OP_BIC_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2244,14 +2248,14 @@ static u32 FASTCALL  OP_BIC_LSL_IMM(armcpu_t *cpu)
      OPP_BIC(1,3);
 }
 
-static u32 FASTCALL  OP_BIC_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OPP_BIC(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2259,14 +2263,14 @@ static u32 FASTCALL  OP_BIC_LSR_IMM(armcpu_t *cpu)
      OPP_BIC(1,3);
 }
 
-static u32 FASTCALL  OP_BIC_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;             
      OPP_BIC(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2274,14 +2278,14 @@ static u32 FASTCALL  OP_BIC_ASR_IMM(armcpu_t *cpu)
      OPP_BIC(1,3);
 }
 
-static u32 FASTCALL  OP_BIC_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;                     
      OPP_BIC(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2289,77 +2293,77 @@ static u32 FASTCALL  OP_BIC_ROR_IMM(armcpu_t *cpu)
      OPP_BIC(1,3);
 }
 
-static u32 FASTCALL  OP_BIC_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OPP_BIC(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OPP_BIC(1,3);
 }
 
-static u32 FASTCALL  OP_BIC_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OPP_BIC_S(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OPP_BIC_S(3,5);
 }
 
-static u32 FASTCALL  OP_BIC_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OPP_BIC_S(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;
      OPP_BIC_S(3,5);
 }
 
-static u32 FASTCALL  OP_BIC_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OPP_BIC_S(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;
      OPP_BIC_S(3,5);
 }
 
-static u32 FASTCALL  OP_BIC_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OPP_BIC_S(2,4);
 }
 
-static u32 FASTCALL  OP_BIC_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OPP_BIC_S(3,5);
 }
 
-static u32 FASTCALL  OP_BIC_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BIC_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -2390,7 +2394,7 @@ static u32 FASTCALL  OP_BIC_S_IMM_VAL(armcpu_t *cpu)
      cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
      return a;
      
-static u32 FASTCALL  OP_MVN_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_LSL_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2398,14 +2402,14 @@ static u32 FASTCALL  OP_MVN_LSL_IMM(armcpu_t *cpu)
      OPP_MVN(1,3);
 }
 
-static u32 FASTCALL  OP_MVN_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_LSL_REG()
 {
      u32 i = cpu->instruction;
      LSL_REG;
      OPP_MVN(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_LSR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2413,14 +2417,14 @@ static u32 FASTCALL  OP_MVN_LSR_IMM(armcpu_t *cpu)
      OPP_MVN(1,3);
 }
 
-static u32 FASTCALL  OP_MVN_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_LSR_REG()
 {
      u32 i = cpu->instruction;
      LSR_REG;
      OPP_MVN(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_ASR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2428,14 +2432,14 @@ static u32 FASTCALL  OP_MVN_ASR_IMM(armcpu_t *cpu)
      OPP_MVN(1,3);
 }
 
-static u32 FASTCALL  OP_MVN_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_ASR_REG()
 {
      u32 i = cpu->instruction;
      ASR_REG;
      OPP_MVN(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_ROR_IMM()
 {
      u32 i = cpu->instruction;
      u32 shift_op;
@@ -2443,77 +2447,77 @@ static u32 FASTCALL  OP_MVN_ROR_IMM(armcpu_t *cpu)
      OPP_MVN(1,3);
 }
 
-static u32 FASTCALL  OP_MVN_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_ROR_REG()
 {
      u32 i = cpu->instruction;
      ROR_REG;
      OPP_MVN(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
      OPP_MVN(1,3);
 }
 
-static u32 FASTCALL  OP_MVN_S_LSL_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_LSL_IMM()
 {
      u32 i = cpu->instruction;
      S_LSL_IMM;
      OPP_MVN_S(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_S_LSL_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_LSL_REG()
 {
      u32 i = cpu->instruction;
      S_LSL_REG;
      OPP_MVN_S(3,5);
 }
 
-static u32 FASTCALL  OP_MVN_S_LSR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_LSR_IMM()
 {
      u32 i = cpu->instruction;
      S_LSR_IMM;            
      OPP_MVN_S(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_S_LSR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_LSR_REG()
 {
      u32 i = cpu->instruction;
      S_LSR_REG;
      OPP_MVN_S(3,5);
 }
 
-static u32 FASTCALL  OP_MVN_S_ASR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_ASR_IMM()
 {
      u32 i = cpu->instruction;
      S_ASR_IMM;
      OPP_MVN_S(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_S_ASR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_ASR_REG()
 {
      u32 i = cpu->instruction;
      S_ASR_REG;
      OPP_MVN_S(3,5);
 }
 
-static u32 FASTCALL  OP_MVN_S_ROR_IMM(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_ROR_IMM()
 {
      u32 i = cpu->instruction;
      S_ROR_IMM;
      OPP_MVN_S(2,4);
 }
 
-static u32 FASTCALL  OP_MVN_S_ROR_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_ROR_REG()
 {
      u32 i = cpu->instruction;
      S_ROR_REG;
      OPP_MVN_S(3,5);
 }
 
-static u32 FASTCALL  OP_MVN_S_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MVN_S_IMM_VAL()
 {
      u32 i = cpu->instruction;
      S_IMM_VALUE;
@@ -2532,7 +2536,7 @@ static u32 FASTCALL  OP_MVN_S_IMM_VAL(armcpu_t *cpu)
           return b+2;\
      return a;\
 
-static u32 FASTCALL  OP_MUL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MUL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2540,7 +2544,7 @@ static u32 FASTCALL  OP_MUL(armcpu_t *cpu)
      OPP_M(5,2);
 }
 
-static u32 FASTCALL  OP_MLA(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MLA()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2551,7 +2555,7 @@ static u32 FASTCALL  OP_MLA(armcpu_t *cpu)
      OPP_M(6,3);
 }
 
-static u32 FASTCALL  OP_MUL_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MUL_S()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2563,7 +2567,7 @@ static u32 FASTCALL  OP_MUL_S(armcpu_t *cpu)
      OPP_M(6,3);
 }
 
-static u32 FASTCALL  OP_MLA_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MLA_S()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2575,7 +2579,7 @@ static u32 FASTCALL  OP_MLA_S(armcpu_t *cpu)
 
 //----------UMUL--------------------------
 
-static u32 FASTCALL  OP_UMULL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_UMULL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2587,7 +2591,7 @@ static u32 FASTCALL  OP_UMULL(armcpu_t *cpu)
      OPP_M(6,3);
 }
 
-static u32 FASTCALL  OP_UMLAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_UMLAL()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2599,7 +2603,7 @@ static u32 FASTCALL  OP_UMLAL(armcpu_t *cpu)
      OPP_M(7,4);
 }
 
-static u32 FASTCALL  OP_UMULL_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_UMULL_S()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2614,7 +2618,7 @@ static u32 FASTCALL  OP_UMULL_S(armcpu_t *cpu)
      OPP_M(7,4);
 }
 
-static u32 FASTCALL  OP_UMLAL_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_UMLAL_S()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_POS(i,0)];
@@ -2631,7 +2635,7 @@ static u32 FASTCALL  OP_UMLAL_S(armcpu_t *cpu)
 
 //----------SMUL--------------------------
 
-static u32 FASTCALL  OP_SMULL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMULL()
 {
      u32 i = cpu->instruction;
      s64 v = (s32)cpu->R[REG_POS(i,0)];
@@ -2646,7 +2650,7 @@ static u32 FASTCALL  OP_SMULL(armcpu_t *cpu)
      OPP_M(6,3);
 }
 
-static u32 FASTCALL  OP_SMLAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL()
 {
      u32 i = cpu->instruction;
      
@@ -2666,7 +2670,7 @@ static u32 FASTCALL  OP_SMLAL(armcpu_t *cpu)
      OPP_M(7,4);
 }
 
-static u32 FASTCALL  OP_SMULL_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMULL_S()
 {
      u32 i = cpu->instruction;
      s64 v = (s32)cpu->R[REG_POS(i,0)];
@@ -2684,7 +2688,7 @@ static u32 FASTCALL  OP_SMULL_S(armcpu_t *cpu)
      OPP_M(7,4);
 }
 
-static u32 FASTCALL  OP_SMLAL_S(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL_S()
 {
      u32 i = cpu->instruction;
      s64 v = (s32)cpu->R[REG_POS(i,0)];
@@ -2704,7 +2708,7 @@ static u32 FASTCALL  OP_SMLAL_S(armcpu_t *cpu)
 
 //---------------SWP------------------------------
 
-static u32 FASTCALL  OP_SWP(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SWP()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2716,7 +2720,7 @@ static u32 FASTCALL  OP_SWP(armcpu_t *cpu)
      return 4 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF]*2;
 }
 
-static u32 FASTCALL  OP_SWPB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SWPB()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2729,7 +2733,7 @@ static u32 FASTCALL  OP_SWPB(armcpu_t *cpu)
 
 //------------LDRH-----------------------------
 
-static u32 FASTCALL  OP_LDRH_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -2738,7 +2742,7 @@ static u32 FASTCALL  OP_LDRH_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -2747,7 +2751,7 @@ static u32 FASTCALL  OP_LDRH_M_IMM_OFF(armcpu_t *cpu)
     return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -2756,7 +2760,7 @@ static u32 FASTCALL  OP_LDRH_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -2765,7 +2769,7 @@ static u32 FASTCALL  OP_LDRH_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_PRE_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -2775,7 +2779,7 @@ static u32 FASTCALL  OP_LDRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_PRE_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -2786,7 +2790,7 @@ static u32 FASTCALL  OP_LDRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_PRE_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -2796,7 +2800,7 @@ static u32 FASTCALL  OP_LDRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_PRE_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -2806,7 +2810,7 @@ static u32 FASTCALL  OP_LDRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_POS_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2816,7 +2820,7 @@ static u32 FASTCALL  OP_LDRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_POS_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2826,7 +2830,7 @@ static u32 FASTCALL  OP_LDRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_POS_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2836,7 +2840,7 @@ static u32 FASTCALL  OP_LDRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRH_POS_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2848,7 +2852,7 @@ static u32 FASTCALL  OP_LDRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
 
 //------------STRH-----------------------------
 
-static u32 FASTCALL  OP_STRH_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -2857,7 +2861,7 @@ static u32 FASTCALL  OP_STRH_P_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -2866,7 +2870,7 @@ static u32 FASTCALL  OP_STRH_M_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -2875,7 +2879,7 @@ static u32 FASTCALL  OP_STRH_P_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -2884,7 +2888,7 @@ static u32 FASTCALL  OP_STRH_M_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_PRE_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -2894,7 +2898,7 @@ static u32 FASTCALL  OP_STRH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_PRE_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -2904,7 +2908,7 @@ static u32 FASTCALL  OP_STRH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_PRE_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -2914,7 +2918,7 @@ static u32 FASTCALL  OP_STRH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_PRE_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -2924,7 +2928,7 @@ static u32 FASTCALL  OP_STRH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_POS_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2934,7 +2938,7 @@ static u32 FASTCALL  OP_STRH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_POS_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2944,7 +2948,7 @@ static u32 FASTCALL  OP_STRH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_POS_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2954,7 +2958,7 @@ static u32 FASTCALL  OP_STRH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRH_POS_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -2966,7 +2970,7 @@ static u32 FASTCALL  OP_STRH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
 
 //----------------LDRSH--------------------------
 
-static u32 FASTCALL  OP_LDRSH_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -2975,7 +2979,7 @@ static u32 FASTCALL  OP_LDRSH_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -2984,7 +2988,7 @@ static u32 FASTCALL  OP_LDRSH_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -2993,7 +2997,7 @@ static u32 FASTCALL  OP_LDRSH_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -3002,7 +3006,7 @@ static u32 FASTCALL  OP_LDRSH_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -3012,7 +3016,7 @@ static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -3022,7 +3026,7 @@ static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -3032,7 +3036,7 @@ static u32 FASTCALL  OP_LDRSH_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -3042,7 +3046,7 @@ static u32 FASTCALL  OP_LDRSH_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_POS_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3052,7 +3056,7 @@ static u32 FASTCALL  OP_LDRSH_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_POS_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3062,7 +3066,7 @@ static u32 FASTCALL  OP_LDRSH_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_POS_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3072,7 +3076,7 @@ static u32 FASTCALL  OP_LDRSH_POS_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSH_POS_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3084,7 +3088,7 @@ static u32 FASTCALL  OP_LDRSH_POS_INDE_M_REG_OFF(armcpu_t *cpu)
 
 //----------------------LDRSB----------------------
 
-static u32 FASTCALL  OP_LDRSB_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -3093,7 +3097,7 @@ static u32 FASTCALL  OP_LDRSB_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -3102,7 +3106,7 @@ static u32 FASTCALL  OP_LDRSB_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -3111,7 +3115,7 @@ static u32 FASTCALL  OP_LDRSB_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -3120,7 +3124,7 @@ static u32 FASTCALL  OP_LDRSB_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF;
@@ -3130,7 +3134,7 @@ static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF;
@@ -3140,7 +3144,7 @@ static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + cpu->R[REG_POS(i,0)];
@@ -3150,7 +3154,7 @@ static u32 FASTCALL  OP_LDRSB_PRE_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - cpu->R[REG_POS(i,0)];
@@ -3160,7 +3164,7 @@ static u32 FASTCALL  OP_LDRSB_PRE_INDE_M_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_POS_INDE_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3170,7 +3174,7 @@ static u32 FASTCALL  OP_LDRSB_POS_INDE_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_POS_INDE_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3180,7 +3184,7 @@ static u32 FASTCALL  OP_LDRSB_POS_INDE_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_POS_INDE_P_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3190,7 +3194,7 @@ static u32 FASTCALL  OP_LDRSB_POS_INDE_P_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRSB_POS_INDE_M_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -3202,14 +3206,14 @@ static u32 FASTCALL  OP_LDRSB_POS_INDE_M_REG_OFF(armcpu_t *cpu)
 
 //--------------MRS--------------------------------
 
-static u32 FASTCALL  OP_MRS_CPSR(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MRS_CPSR()
 {
      cpu->R[REG_POS(cpu->instruction,12)] = cpu->CPSR.val;
      
      return 1;
 }
 
-static u32 FASTCALL  OP_MRS_SPSR(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MRS_SPSR()
 {
      cpu->R[REG_POS(cpu->instruction,12)] = cpu->SPSR.val;
      
@@ -3218,7 +3222,7 @@ static u32 FASTCALL  OP_MRS_SPSR(armcpu_t *cpu)
 
 //--------------MSR--------------------------------
 
-static u32 FASTCALL  OP_MSR_CPSR(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MSR_CPSR()
 {
      u32 i = cpu->instruction;
      u32 operand = cpu->R[REG_POS(i,0)];
@@ -3241,7 +3245,7 @@ static u32 FASTCALL  OP_MSR_CPSR(armcpu_t *cpu)
      return 1;
 }
 
-static u32 FASTCALL  OP_MSR_SPSR(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MSR_SPSR()
 {
      u32 i = cpu->instruction;
      u32 operand = cpu->R[REG_POS(i,0)];
@@ -3263,7 +3267,7 @@ static u32 FASTCALL  OP_MSR_SPSR(armcpu_t *cpu)
      return 1;
 }
 
-static u32 FASTCALL  OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MSR_CPSR_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -3289,7 +3293,7 @@ static u32 FASTCALL  OP_MSR_CPSR_IMM_VAL(armcpu_t *cpu)
      return 1;
 }
 
-static u32 FASTCALL  OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MSR_SPSR_IMM_VAL()
 {
      u32 i = cpu->instruction;
      IMM_VALUE;
@@ -3313,7 +3317,7 @@ static u32 FASTCALL  OP_MSR_SPSR_IMM_VAL(armcpu_t *cpu)
 
 //-----------------BRANCH--------------------------
 
-static u32 FASTCALL  OP_BX(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BX()
 {
      u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)];
      
@@ -3323,7 +3327,7 @@ static u32 FASTCALL  OP_BX(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL  OP_BLX_REG(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BLX_REG()
 {
      u32 tmp = cpu->R[REG_POS(cpu->instruction, 0)];
      
@@ -3336,7 +3340,7 @@ static u32 FASTCALL  OP_BLX_REG(armcpu_t *cpu)
 
 #define SIGNEXTEND_24(i) (((s32)((i)<<8))>>8)
 
-static u32 FASTCALL  OP_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_B()
 {
 	u32 off = SIGNEXTEND_24(cpu->instruction);
 	if(CONDITION(cpu->instruction)==0xF)
@@ -3350,7 +3354,7 @@ static u32 FASTCALL  OP_B(armcpu_t *cpu)
     return 3;
 }
 
-static u32 FASTCALL  OP_BL(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_BL()
 {
 	u32 off = SIGNEXTEND_24(cpu->instruction);
 	if(CONDITION(cpu->instruction)==0xF)
@@ -3376,7 +3380,7 @@ u8 CLZ_TAB[16]=
      4, 4, 4, 4, 4, 4, 4, 4 // 1XXX
 };
      
-static u32 FASTCALL  OP_CLZ(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CLZ()
 {
      u32 i = cpu->instruction;
      u32 Rm = cpu->R[REG_POS(i,0)];
@@ -3411,7 +3415,7 @@ static u32 FASTCALL  OP_CLZ(armcpu_t *cpu)
 
 //--------------------QADD--QSUB------------------------------
 
-static u32 FASTCALL  OP_QADD(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_QADD()
 {
      u32 i = cpu->instruction;
         u32 res = cpu->R[REG_POS(i,16)]+cpu->R[REG_POS(i,0)];
@@ -3433,7 +3437,7 @@ static u32 FASTCALL  OP_QADD(armcpu_t *cpu)
     return 2;
 }
 
-static u32 FASTCALL  OP_QSUB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_QSUB()
 {
      u32 i = cpu->instruction;
         u32 res = cpu->R[REG_POS(i,0)]-cpu->R[REG_POS(i,16)];
@@ -3455,7 +3459,7 @@ static u32 FASTCALL  OP_QSUB(armcpu_t *cpu)
     return 2;
 }
 
-static u32 FASTCALL  OP_QDADD(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_QDADD()
 {
      u32 i = cpu->instruction;
         u32 mul = cpu->R[REG_POS(i,16)]<<1;
@@ -3486,7 +3490,7 @@ static u32 FASTCALL  OP_QDADD(armcpu_t *cpu)
     return 2;
 }
 
-static u32 FASTCALL  OP_QDSUB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_QDSUB()
 {
     u32 i = cpu->instruction;
         u32 mul = cpu->R[REG_POS(i,16)]<<1;
@@ -3522,7 +3526,7 @@ static u32 FASTCALL  OP_QDSUB(armcpu_t *cpu)
 #define HWORD(i)   ((s32)(((s32)(i))>>16))
 #define LWORD(i)   (s32)(((s32)((i)<<16))>>16)
 
-static u32 FASTCALL  OP_SMUL_B_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMUL_B_B()
 {
      u32 i = cpu->instruction;
      
@@ -3531,7 +3535,7 @@ static u32 FASTCALL  OP_SMUL_B_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMUL_B_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMUL_B_T()
 {
      u32 i = cpu->instruction;
 
@@ -3540,7 +3544,7 @@ static u32 FASTCALL  OP_SMUL_B_T(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMUL_T_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMUL_T_B()
 {
      u32 i = cpu->instruction;
 
@@ -3549,7 +3553,7 @@ static u32 FASTCALL  OP_SMUL_T_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMUL_T_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMUL_T_T()
 {
      u32 i = cpu->instruction;
 
@@ -3560,7 +3564,7 @@ static u32 FASTCALL  OP_SMUL_T_T(armcpu_t *cpu)
 
 //-----------SMLA----------------------------
 
-static u32 FASTCALL  OP_SMLA_B_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLA_B_B()
 {
      u32 i = cpu->instruction;
      u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
@@ -3575,7 +3579,7 @@ static u32 FASTCALL  OP_SMLA_B_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLA_B_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLA_B_T()
 {
      u32 i = cpu->instruction;
      u32 tmp = (u32)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
@@ -3590,7 +3594,7 @@ static u32 FASTCALL  OP_SMLA_B_T(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLA_T_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLA_T_B()
 {
      u32 i = cpu->instruction;
      u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
@@ -3605,7 +3609,7 @@ static u32 FASTCALL  OP_SMLA_T_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLA_T_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLA_T_T()
 {
      u32 i = cpu->instruction;
      u32 tmp = (u32)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
@@ -3622,7 +3626,7 @@ static u32 FASTCALL  OP_SMLA_T_T(armcpu_t *cpu)
 
 //--------------SMLAL---------------------------------------
 
-static u32 FASTCALL  OP_SMLAL_B_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL_B_B()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* LWORD(cpu->R[REG_POS(i,8)]));
@@ -3636,7 +3640,7 @@ static u32 FASTCALL  OP_SMLAL_B_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLAL_B_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL_B_T()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)(LWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
@@ -3650,7 +3654,7 @@ static u32 FASTCALL  OP_SMLAL_B_T(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLAL_T_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL_T_B()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* (s64)LWORD(cpu->R[REG_POS(i,8)]));
@@ -3664,7 +3668,7 @@ static u32 FASTCALL  OP_SMLAL_T_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLAL_T_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAL_T_T()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)(HWORD(cpu->R[REG_POS(i,0)])* HWORD(cpu->R[REG_POS(i,8)]));
@@ -3680,7 +3684,7 @@ static u32 FASTCALL  OP_SMLAL_T_T(armcpu_t *cpu)
 
 //--------------SMULW--------------------
 
-static u32 FASTCALL  OP_SMULW_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMULW_B()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
@@ -3692,7 +3696,7 @@ static u32 FASTCALL  OP_SMULW_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMULW_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMULW_T()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
@@ -3705,7 +3709,7 @@ static u32 FASTCALL  OP_SMULW_T(armcpu_t *cpu)
 }
 
 //--------------SMLAW-------------------
-static u32 FASTCALL  OP_SMLAW_B(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAW_B()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)LWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
@@ -3723,7 +3727,7 @@ static u32 FASTCALL  OP_SMLAW_B(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL  OP_SMLAW_T(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SMLAW_T()
 {
      u32 i = cpu->instruction;
      s64 tmp = (s64)HWORD(cpu->R[REG_POS(i,8)]) * (s64)((s32)cpu->R[REG_POS(i,0)]);
@@ -3742,7 +3746,7 @@ static u32 FASTCALL  OP_SMLAW_T(armcpu_t *cpu)
 
 //------------LDR---------------------------
 
-static u32 FASTCALL  OP_LDR_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -3763,7 +3767,7 @@ static u32 FASTCALL  OP_LDR_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -3785,7 +3789,7 @@ static u32 FASTCALL  OP_LDR_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3811,7 +3815,7 @@ static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3837,7 +3841,7 @@ static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3863,7 +3867,7 @@ static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3889,7 +3893,7 @@ static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3915,7 +3919,7 @@ static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3941,7 +3945,7 @@ static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3967,7 +3971,7 @@ static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -3994,7 +3998,7 @@ static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -4018,7 +4022,7 @@ static u32 FASTCALL  OP_LDR_P_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -4043,7 +4047,7 @@ static u32 FASTCALL  OP_LDR_M_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4072,7 +4076,7 @@ static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4101,7 +4105,7 @@ static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4130,7 +4134,7 @@ static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4159,7 +4163,7 @@ static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4188,7 +4192,7 @@ static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4217,7 +4221,7 @@ static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4246,7 +4250,7 @@ static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4274,7 +4278,7 @@ static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -4299,7 +4303,7 @@ static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
 }
 
 //------------------------------------------------------------
-static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND2()
 {
      u32 i = cpu->instruction;
      
@@ -4329,7 +4333,7 @@ static u32 FASTCALL  OP_LDR_P_IMM_OFF_POSTIND2(armcpu_t *cpu)
 
 //------------------------------------------------------------
 
-static u32 FASTCALL  OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -4353,7 +4357,7 @@ static u32 FASTCALL  OP_LDR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4381,7 +4385,7 @@ static u32 FASTCALL  OP_LDR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4409,7 +4413,7 @@ static u32 FASTCALL  OP_LDR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4437,7 +4441,7 @@ static u32 FASTCALL  OP_LDR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4465,7 +4469,7 @@ static u32 FASTCALL  OP_LDR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4493,7 +4497,7 @@ static u32 FASTCALL  OP_LDR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4521,7 +4525,7 @@ static u32 FASTCALL  OP_LDR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4549,7 +4553,7 @@ static u32 FASTCALL  OP_LDR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4579,7 +4583,7 @@ static u32 FASTCALL  OP_LDR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
 
 //-----------------LDRB-------------------------------------------
 
-static u32 FASTCALL  OP_LDRB_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -4589,7 +4593,7 @@ static u32 FASTCALL  OP_LDRB_P_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -4599,7 +4603,7 @@ static u32 FASTCALL  OP_LDRB_M_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4613,7 +4617,7 @@ static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4627,7 +4631,7 @@ static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4641,7 +4645,7 @@ static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4655,7 +4659,7 @@ static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4669,7 +4673,7 @@ static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4683,7 +4687,7 @@ static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4697,7 +4701,7 @@ static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4712,7 +4716,7 @@ static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -4725,7 +4729,7 @@ static u32 FASTCALL  OP_LDRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -4737,7 +4741,7 @@ static u32 FASTCALL  OP_LDRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4754,7 +4758,7 @@ static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4770,7 +4774,7 @@ static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4785,7 +4789,7 @@ static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4800,7 +4804,7 @@ static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4815,7 +4819,7 @@ static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4830,7 +4834,7 @@ static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4845,7 +4849,7 @@ static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4860,7 +4864,7 @@ static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -4871,7 +4875,7 @@ static u32 FASTCALL  OP_LDRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -4882,7 +4886,7 @@ static u32 FASTCALL  OP_LDRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4897,7 +4901,7 @@ static u32 FASTCALL  OP_LDRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4912,7 +4916,7 @@ static u32 FASTCALL  OP_LDRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4927,7 +4931,7 @@ static u32 FASTCALL  OP_LDRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4942,7 +4946,7 @@ static u32 FASTCALL  OP_LDRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4957,7 +4961,7 @@ static u32 FASTCALL  OP_LDRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4972,7 +4976,7 @@ static u32 FASTCALL  OP_LDRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -4987,7 +4991,7 @@ static u32 FASTCALL  OP_LDRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5004,7 +5008,7 @@ static u32 FASTCALL  OP_LDRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
 
 //----------------------STR--------------------------------
 
-static u32 FASTCALL  OP_STR_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -5015,7 +5019,7 @@ static u32 FASTCALL  OP_STR_P_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -5024,7 +5028,7 @@ static u32 FASTCALL  OP_STR_M_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5036,7 +5040,7 @@ static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5048,7 +5052,7 @@ static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5060,7 +5064,7 @@ static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5072,7 +5076,7 @@ static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5084,7 +5088,7 @@ static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5096,7 +5100,7 @@ static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5108,7 +5112,7 @@ static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5121,7 +5125,7 @@ static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -5131,7 +5135,7 @@ static u32 FASTCALL  OP_STR_P_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -5141,7 +5145,7 @@ static u32 FASTCALL  OP_STR_M_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5154,7 +5158,7 @@ static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5167,7 +5171,7 @@ static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5180,7 +5184,7 @@ static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5193,7 +5197,7 @@ static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5206,7 +5210,7 @@ static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5219,7 +5223,7 @@ static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5232,7 +5236,7 @@ static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5245,7 +5249,7 @@ static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -5255,7 +5259,7 @@ static u32 FASTCALL  OP_STR_P_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -5265,7 +5269,7 @@ static u32 FASTCALL  OP_STR_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5278,7 +5282,7 @@ static u32 FASTCALL  OP_STR_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5291,7 +5295,7 @@ static u32 FASTCALL  OP_STR_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5304,7 +5308,7 @@ static u32 FASTCALL  OP_STR_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5317,7 +5321,7 @@ static u32 FASTCALL  OP_STR_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5330,7 +5334,7 @@ static u32 FASTCALL  OP_STR_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5343,7 +5347,7 @@ static u32 FASTCALL  OP_STR_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5356,7 +5360,7 @@ static u32 FASTCALL  OP_STR_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5371,7 +5375,7 @@ static u32 FASTCALL  OP_STR_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
 
 //-----------------------STRB-------------------------------------
 
-static u32 FASTCALL  OP_STRB_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -5380,7 +5384,7 @@ static u32 FASTCALL  OP_STRB_P_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -5389,7 +5393,7 @@ static u32 FASTCALL  OP_STRB_M_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5401,7 +5405,7 @@ static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5413,7 +5417,7 @@ static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5425,7 +5429,7 @@ static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5437,7 +5441,7 @@ static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5449,7 +5453,7 @@ static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5461,7 +5465,7 @@ static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5473,7 +5477,7 @@ static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5485,7 +5489,7 @@ static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] + IMM_OFF_12;
@@ -5495,7 +5499,7 @@ static u32 FASTCALL  OP_STRB_P_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)] - IMM_OFF_12;
@@ -5505,7 +5509,7 @@ static u32 FASTCALL  OP_STRB_M_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5518,7 +5522,7 @@ static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5531,7 +5535,7 @@ static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5544,7 +5548,7 @@ static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5557,7 +5561,7 @@ static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5570,7 +5574,7 @@ static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5583,7 +5587,7 @@ static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5596,7 +5600,7 @@ static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_PREIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5609,7 +5613,7 @@ static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_PREIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -5619,7 +5623,7 @@ static u32 FASTCALL  OP_STRB_P_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_POS(i,16)];
@@ -5629,7 +5633,7 @@ static u32 FASTCALL  OP_STRB_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5642,7 +5646,7 @@ static u32 FASTCALL  OP_STRB_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5655,7 +5659,7 @@ static u32 FASTCALL  OP_STRB_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5668,7 +5672,7 @@ static u32 FASTCALL  OP_STRB_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5681,7 +5685,7 @@ static u32 FASTCALL  OP_STRB_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5694,7 +5698,7 @@ static u32 FASTCALL  OP_STRB_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5707,7 +5711,7 @@ static u32 FASTCALL  OP_STRB_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5720,7 +5724,7 @@ static u32 FASTCALL  OP_STRB_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_POSTIND()
 {
      u32 i = cpu->instruction;
      u32 adr;
@@ -5735,7 +5739,7 @@ static u32 FASTCALL  OP_STRB_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
 
 //-----------------------LDRBT-------------------------------------
 
-static u32 FASTCALL  OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_IMM_OFF_POSTIND()
 {
      u32 oldmode;     
      u32 i;
@@ -5757,7 +5761,7 @@ static u32 FASTCALL  OP_LDRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_M_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5783,7 +5787,7 @@ static u32 FASTCALL  OP_LDRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_REG_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5809,7 +5813,7 @@ static u32 FASTCALL  OP_LDRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_LSL_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5836,7 +5840,7 @@ static u32 FASTCALL  OP_LDRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_M_LSL_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5864,7 +5868,7 @@ static u32 FASTCALL  OP_LDRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_LSR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5892,7 +5896,7 @@ static u32 FASTCALL  OP_LDRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_M_LSR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5920,7 +5924,7 @@ static u32 FASTCALL  OP_LDRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_ASR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5948,7 +5952,7 @@ static u32 FASTCALL  OP_LDRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_M_ASR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -5976,7 +5980,7 @@ static u32 FASTCALL  OP_LDRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_P_ROR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6004,7 +6008,7 @@ static u32 FASTCALL  OP_LDRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDRBT_M_ROR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6034,7 +6038,7 @@ static u32 FASTCALL  OP_LDRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
 
 //----------------------STRBT----------------------------
 
-static u32 FASTCALL  OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6056,7 +6060,7 @@ static u32 FASTCALL  OP_STRBT_P_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6078,7 +6082,7 @@ static u32 FASTCALL  OP_STRBT_M_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_REG_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6100,7 +6104,7 @@ static u32 FASTCALL  OP_STRBT_P_REG_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_REG_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6122,7 +6126,7 @@ static u32 FASTCALL  OP_STRBT_M_REG_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_LSL_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6146,7 +6150,7 @@ static u32 FASTCALL  OP_STRBT_P_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_LSL_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6170,7 +6174,7 @@ static u32 FASTCALL  OP_STRBT_M_LSL_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_LSR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6194,7 +6198,7 @@ static u32 FASTCALL  OP_STRBT_P_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_LSR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6218,7 +6222,7 @@ static u32 FASTCALL  OP_STRBT_M_LSR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_ASR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6242,7 +6246,7 @@ static u32 FASTCALL  OP_STRBT_P_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_ASR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6266,7 +6270,7 @@ static u32 FASTCALL  OP_STRBT_M_ASR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_P_ROR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6290,7 +6294,7 @@ static u32 FASTCALL  OP_STRBT_P_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL  OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STRBT_M_ROR_IMM_OFF_POSTIND()
 {
      u32 oldmode;
      u32 i;
@@ -6344,7 +6348,7 @@ static u32 FASTCALL  OP_STRBT_M_ROR_IMM_OFF_POSTIND(armcpu_t *cpu)
           c += waitState[(start>>24)&0xF];\
      }
 
-static u32 FASTCALL  OP_LDMIA(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIA()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -6382,7 +6386,7 @@ static u32 FASTCALL  OP_LDMIA(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIB()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -6422,7 +6426,7 @@ static u32 FASTCALL  OP_LDMIB(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDA(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDA()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -6460,7 +6464,7 @@ static u32 FASTCALL  OP_LDMDA(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDB()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -6499,7 +6503,7 @@ static u32 FASTCALL  OP_LDMDB(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIA_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIA_W()
 {
      u32 i = cpu->instruction, c = 0, count;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -6544,7 +6548,7 @@ static u32 FASTCALL  OP_LDMIA_W(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIB_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIB_W()
 {
      u32 i = cpu->instruction, c = 0, count;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -6591,7 +6595,7 @@ static u32 FASTCALL  OP_LDMIB_W(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDA_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDA_W()
 {
 	u32 i = cpu->instruction, c = 0, count;
 	u32 start = cpu->R[REG_POS(i,16)];
@@ -6636,7 +6640,7 @@ static u32 FASTCALL  OP_LDMDA_W(armcpu_t *cpu)
 	return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDB_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDB_W()
 {
 	u32 i = cpu->instruction, c = 0, count;
 	u32 start = cpu->R[REG_POS(i,16)];
@@ -6681,7 +6685,7 @@ static u32 FASTCALL  OP_LDMDB_W(armcpu_t *cpu)
 	return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIA2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIA2()
 {
      u32 i = cpu->instruction;
      u32 oldmode;
@@ -6737,7 +6741,7 @@ static u32 FASTCALL  OP_LDMIA2(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIB2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIB2()
 {
      u32 i = cpu->instruction;
      u32 oldmode;
@@ -6795,7 +6799,7 @@ static u32 FASTCALL  OP_LDMIB2(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDA2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDA2()
 {
      u32 i = cpu->instruction;
           
@@ -6858,7 +6862,7 @@ static u32 FASTCALL  OP_LDMDA2(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDB2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDB2()
 {
      u32 i = cpu->instruction;
           
@@ -6919,7 +6923,7 @@ static u32 FASTCALL  OP_LDMDB2(armcpu_t *cpu)
      return 2 + c;
 }
 
-static u32 FASTCALL  OP_LDMIA2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIA2_W()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -6976,7 +6980,7 @@ static u32 FASTCALL  OP_LDMIA2_W(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMIB2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMIB2_W()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -7035,7 +7039,7 @@ static u32 FASTCALL  OP_LDMIB2_W(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDA2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDA2_W()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -7095,7 +7099,7 @@ static u32 FASTCALL  OP_LDMDA2_W(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL  OP_LDMDB2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDMDB2_W()
 {
      u32 i = cpu->instruction;
      u32 c = 0;
@@ -7159,7 +7163,7 @@ static u32 FASTCALL  OP_LDMDB2_W(armcpu_t *cpu)
 
 //------------------------------STM----------------------------------
 
-static u32 FASTCALL  OP_STMIA(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIA()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7176,7 +7180,7 @@ static u32 FASTCALL  OP_STMIA(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIB()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7193,7 +7197,7 @@ static u32 FASTCALL  OP_STMIB(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDA(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDA()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7210,7 +7214,7 @@ static u32 FASTCALL  OP_STMDA(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDB(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDB()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7227,7 +7231,7 @@ static u32 FASTCALL  OP_STMDB(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIA_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIA_W()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7246,7 +7250,7 @@ static u32 FASTCALL  OP_STMIA_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIB_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIB_W()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7264,7 +7268,7 @@ static u32 FASTCALL  OP_STMIB_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDA_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDA_W()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7283,7 +7287,7 @@ static u32 FASTCALL  OP_STMDA_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDB_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDB_W()
 {
      u32 i = cpu->instruction, c = 0, b;
      u32 start = cpu->R[REG_POS(i,16)];
@@ -7302,7 +7306,7 @@ static u32 FASTCALL  OP_STMDB_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIA2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIA2()
 {
      u32 i, c, b;
      u32 start;
@@ -7333,7 +7337,7 @@ static u32 FASTCALL  OP_STMIA2(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIB2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIB2()
 {
      u32 i, c, b;
      u32 start;
@@ -7364,7 +7368,7 @@ static u32 FASTCALL  OP_STMIB2(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDA2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDA2()
 {
      u32 i, c, b;
      u32 start;
@@ -7395,7 +7399,7 @@ static u32 FASTCALL  OP_STMDA2(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDB2(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDB2()
 {
      u32 i, c, b;
      u32 start;
@@ -7422,7 +7426,7 @@ static u32 FASTCALL  OP_STMDB2(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIA2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIA2_W()
 {
      u32 i, c, b;
      u32 start;
@@ -7455,7 +7459,7 @@ static u32 FASTCALL  OP_STMIA2_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMIB2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMIB2_W()
 {
      u32 i, c, b;
      u32 start;
@@ -7483,7 +7487,7 @@ static u32 FASTCALL  OP_STMIB2_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDA2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDA2_W()
 {
      u32 i, c, b;
      u32 start;
@@ -7515,7 +7519,7 @@ static u32 FASTCALL  OP_STMDA2_W(armcpu_t *cpu)
      return c + 1;
 }
 
-static u32 FASTCALL  OP_STMDB2_W(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STMDB2_W()
 {
      u32 i, c, b;     
      u32 start;
@@ -7554,8 +7558,8 @@ static u32 FASTCALL  OP_STMDB2_W(armcpu_t *cpu)
  * The Enhanced DSP Extension LDRD and STRD instructions.
  *
  */
-static u32 FASTCALL
-OP_LDRD_STRD_POST_INDEX( armcpu_t *cpu) {
+TEMPLATE static u32 FASTCALL
+OP_LDRD_STRD_POST_INDEX( ) {
   u32 i = cpu->instruction;
   u32 Rd_num = REG_POS( i, 12);
   u32 addr = cpu->R[REG_POS(i,16)];
@@ -7588,8 +7592,8 @@ OP_LDRD_STRD_POST_INDEX( armcpu_t *cpu) {
   return 3 + (MMU.MMU_WAIT32[cpu->proc_ID][(addr>>24)&0xF] * 2);
 }
 
-static u32 FASTCALL
-OP_LDRD_STRD_OFFSET_PRE_INDEX( armcpu_t *cpu) {
+TEMPLATE static u32 FASTCALL
+OP_LDRD_STRD_OFFSET_PRE_INDEX( ) {
   u32 i = cpu->instruction;
   u32 Rd_num = REG_POS( i, 12);
   u32 addr = cpu->R[REG_POS(i,16)];
@@ -7636,7 +7640,7 @@ OP_LDRD_STRD_OFFSET_PRE_INDEX( armcpu_t *cpu) {
 
 //---------------------STC----------------------------------
 
-static u32 FASTCALL  OP_STC_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_P_IMM_OFF()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7644,7 +7648,7 @@ static u32 FASTCALL  OP_STC_P_IMM_OFF(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_M_IMM_OFF()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7652,7 +7656,7 @@ static u32 FASTCALL  OP_STC_M_IMM_OFF(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_P_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_P_PREIND()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7660,7 +7664,7 @@ static u32 FASTCALL  OP_STC_P_PREIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_M_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_M_PREIND()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7668,7 +7672,7 @@ static u32 FASTCALL  OP_STC_M_PREIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_P_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_P_POSTIND()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7676,7 +7680,7 @@ static u32 FASTCALL  OP_STC_P_POSTIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_M_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_M_POSTIND()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7684,7 +7688,7 @@ static u32 FASTCALL  OP_STC_M_POSTIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_STC_OPTION(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_STC_OPTION()
 {
      {
 		/* the NDS has no coproc that responses to a STC, no feedback is given to the arm */
@@ -7694,7 +7698,7 @@ static u32 FASTCALL  OP_STC_OPTION(armcpu_t *cpu)
 
 //---------------------LDC----------------------------------
 
-static u32 FASTCALL  OP_LDC_P_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_P_IMM_OFF()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7702,7 +7706,7 @@ static u32 FASTCALL  OP_LDC_P_IMM_OFF(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_M_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_M_IMM_OFF()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7710,7 +7714,7 @@ static u32 FASTCALL  OP_LDC_M_IMM_OFF(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_P_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_P_PREIND()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7718,7 +7722,7 @@ static u32 FASTCALL  OP_LDC_P_PREIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_M_PREIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_M_PREIND()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7726,7 +7730,7 @@ static u32 FASTCALL  OP_LDC_M_PREIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_P_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_P_POSTIND()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7734,7 +7738,7 @@ static u32 FASTCALL  OP_LDC_P_POSTIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_M_POSTIND(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_M_POSTIND()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7742,7 +7746,7 @@ static u32 FASTCALL  OP_LDC_M_POSTIND(armcpu_t *cpu)
      }
 }
 
-static u32 FASTCALL  OP_LDC_OPTION(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_LDC_OPTION()
 {
      {
 		/* the NDS has no coproc that responses to a LDC, no feedback is given to the arm */
@@ -7752,7 +7756,7 @@ static u32 FASTCALL  OP_LDC_OPTION(armcpu_t *cpu)
 
 //----------------MCR-----------------------
 
-static u32 FASTCALL  OP_MCR(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MCR()
 {
      u32 i = cpu->instruction;
      u32 cpnum = REG_POS(i, 8);
@@ -7771,7 +7775,7 @@ static u32 FASTCALL  OP_MCR(armcpu_t *cpu)
 
 //----------------MRC-----------------------
 
-static u32 FASTCALL  OP_MRC(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_MRC()
 {
      u32 i = cpu->instruction;
      u32 cpnum = REG_POS(i, 8);
@@ -7789,7 +7793,7 @@ static u32 FASTCALL  OP_MRC(armcpu_t *cpu)
 }
 
 //--------------SWI-------------------------------
-static u32 FASTCALL  OP_SWI(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_SWI()
 {
      if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
      {
@@ -7814,7 +7818,7 @@ static u32 FASTCALL  OP_SWI(armcpu_t *cpu)
 }
 
 //----------------BKPT-------------------------
-static u32 FASTCALL OP_BKPT(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL OP_BKPT()
 {
      execute = FALSE;
 	 LOG("Stopped (OP_BKPT)\n");
@@ -7823,7 +7827,7 @@ static u32 FASTCALL OP_BKPT(armcpu_t *cpu)
 
 //----------------CDP-----------------------
 
-static u32 FASTCALL  OP_CDP(armcpu_t *cpu)
+TEMPLATE static u32 FASTCALL  OP_CDP()
 {
      execute = FALSE;
 	 LOG("Stopped (OP_CDP)\n");
@@ -7831,8 +7835,23 @@ static u32 FASTCALL  OP_CDP(armcpu_t *cpu)
 }
 
 #define TYPE_RETOUR u32
-#define PARAMETRES  armcpu_t *cpu
+#define PARAMETRES  
 #define CALLTYPE    FASTCALL 
-#define NOM_TAB     arm_instructions_set
+#define NOM_TAB     arm_instructions_set_0
+#define TABDECL(x)		x<0>
+
+#include "instruction_tabdef.inc"
+
+#undef TYPE_RETOUR
+#undef PARAMETRES  
+#undef CALLTYPE
+#undef NOM_TAB
+#undef TABDECL
+
+#define TYPE_RETOUR u32
+#define PARAMETRES  
+#define CALLTYPE    FASTCALL 
+#define NOM_TAB     arm_instructions_set_1
+#define TABDECL(x)		x<1>
 
 #include "instruction_tabdef.inc"
diff --git a/desmume/src/arm_instructions.h b/desmume/src/arm_instructions.h
index 350680aaf..fab719263 100644
--- a/desmume/src/arm_instructions.h
+++ b/desmume/src/arm_instructions.h
@@ -25,7 +25,8 @@
 #include "types.h"
 #include "armcpu.h"
 
-extern u32 (FASTCALL* arm_instructions_set[4096])(armcpu_t * cpu);
+extern u32 (FASTCALL* arm_instructions_set_0[4096])();
+extern u32 (FASTCALL* arm_instructions_set_1[4096])();
  
 #endif
 
diff --git a/desmume/src/armcpu.cpp b/desmume/src/armcpu.cpp
index a3071857e..648b0709f 100644
--- a/desmume/src/armcpu.cpp
+++ b/desmume/src/armcpu.cpp
@@ -26,6 +26,13 @@
 #include <stdlib.h>
 #include <stdio.h>
 
+template<u32> static u32 armcpu_prefetch();
+
+inline u32 armcpu_prefetch(armcpu_t *armcpu) { 
+	if(armcpu->proc_ID==0) return armcpu_prefetch<0>();
+	else return armcpu_prefetch<1>();
+}
+
 const unsigned char arm_cond_table[16*16] = {
     /* N=0, Z=0, C=0, V=0 */
     0x00,0xFF,0x00,0xFF,0x00,0xFF,0x00,0xFF,
@@ -351,9 +358,11 @@ u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode)
 	return oldmode;
 }
 
+template<u32 PROCNUM>
 static u32
-armcpu_prefetch(armcpu_t *armcpu)
+armcpu_prefetch()
 {
+	armcpu_t* armcpu = &ARMPROC;
 	u32 temp_instruction;
 
 	if(armcpu->CPSR.bits.T == 0)
@@ -370,14 +379,14 @@ armcpu_prefetch(armcpu_t *armcpu)
 			armcpu->R[15] = armcpu->next_instruction + 4;
 		}
 #else
-		armcpu->instruction = MMU_read32_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
+		armcpu->instruction = MMU_read32_acl(PROCNUM, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
 
 		armcpu->instruct_adr = armcpu->next_instruction;
 		armcpu->next_instruction += 4;
 		armcpu->R[15] = armcpu->next_instruction + 4;
 #endif
           
-        return MMU.MMU_WAIT32[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF];
+        return MMU.MMU_WAIT32[PROCNUM][(armcpu->instruct_adr>>24)&0xF];
 	}
 
 #ifdef GDB_STUB
@@ -392,16 +401,15 @@ armcpu_prefetch(armcpu_t *armcpu)
 		armcpu->R[15] = armcpu->next_instruction + 2;
 	}
 #else
-	armcpu->instruction = MMU_read16_acl(armcpu->proc_ID, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
+	armcpu->instruction = MMU_read16_acl(PROCNUM, armcpu->next_instruction,CP15_ACCESS_EXECUTE);
 
 	armcpu->instruct_adr = armcpu->next_instruction;
 	armcpu->next_instruction += 2;
 	armcpu->R[15] = armcpu->next_instruction + 2;
 #endif
 
-	return MMU.MMU_WAIT16[armcpu->proc_ID][(armcpu->instruct_adr>>24)&0xF];
+	return MMU.MMU_WAIT16[PROCNUM][(armcpu->instruct_adr>>24)&0xF];
 }
- 
 
 static BOOL FASTCALL test_EQ(Status_Reg CPSR) { return ( CPSR.bits.Z); }
 static BOOL FASTCALL test_NE(Status_Reg CPSR) { return (!CPSR.bits.Z); }
@@ -525,7 +533,8 @@ armcpu_flagIrq( armcpu_t *armcpu) {
 }
 
 
-u32 armcpu_exec(armcpu_t *armcpu)
+template<int PROCNUM>
+u32 armcpu_exec()
 {
         u32 c = 1;
 
@@ -545,12 +554,16 @@ u32 armcpu_exec(armcpu_t *armcpu)
         }
 #endif
 
-	if(armcpu->CPSR.bits.T == 0)
+	if(ARMPROC.CPSR.bits.T == 0)
 	{
 /*        if((TEST_COND(CONDITION(armcpu->instruction), armcpu->CPSR)) || ((CONDITION(armcpu->instruction)==0xF)&&(CODE(armcpu->instruction)==0x5)))*/
-        if((TEST_COND(CONDITION(armcpu->instruction), CODE(armcpu->instruction), armcpu->CPSR)))
+        if((TEST_COND(CONDITION(ARMPROC.instruction), CODE(ARMPROC.instruction), ARMPROC.CPSR)))
 		{
-			c += arm_instructions_set[INSTRUCTION_INDEX(armcpu->instruction)](armcpu);
+			if(PROCNUM==0)
+				c += arm_instructions_set_0[INSTRUCTION_INDEX(ARMPROC.instruction)]();
+			else
+				c += arm_instructions_set_1[INSTRUCTION_INDEX(ARMPROC.instruction)]();
+			
 		}
 #ifdef GDB_STUB
         if ( armcpu->post_ex_fn != NULL) {
@@ -559,12 +572,15 @@ u32 armcpu_exec(armcpu_t *armcpu)
                                 armcpu->instruct_adr, 0);
         }
 #else
-		c += armcpu_prefetch(armcpu);
+		c += armcpu_prefetch<PROCNUM>();
 #endif
 		return c;
 	}
 
-	c += thumb_instructions_set[armcpu->instruction>>6](armcpu);
+	if(PROCNUM==0)
+		c += thumb_instructions_set_0[ARMPROC.instruction>>6]();
+	else
+		c += thumb_instructions_set_1[ARMPROC.instruction>>6]();
 
 #ifdef GDB_STUB
     if ( armcpu->post_ex_fn != NULL) {
@@ -572,8 +588,11 @@ u32 armcpu_exec(armcpu_t *armcpu)
         armcpu->post_ex_fn( armcpu->post_ex_fn_data, armcpu->instruct_adr, 1);
     }
 #else
-	c += armcpu_prefetch(armcpu);
+	c += armcpu_prefetch<PROCNUM>();
 #endif
 	return c;
 }
 
+//these templates needed to be instantiated manually
+template u32 armcpu_exec<0>();
+template u32 armcpu_exec<1>();
diff --git a/desmume/src/armcpu.h b/desmume/src/armcpu.h
index bc8a42f63..bbd89ffdf 100644
--- a/desmume/src/armcpu.h
+++ b/desmume/src/armcpu.h
@@ -28,6 +28,7 @@
 
 #define ARMCPU_ARM7 1
 #define ARMCPU_ARM9 0
+#define ARMPROC (PROCNUM?NDS_ARM7:NDS_ARM9)
 
 #define CODE(i)     (((i)>>25)&0X7)
 #define OPCODE(i)   (((i)>>21)&0xF)
@@ -227,8 +228,10 @@ int armcpu_new( armcpu_t *armcpu, u32 id);
 #endif
 void armcpu_init(armcpu_t *armcpu, u32 adr);
 u32 armcpu_switchMode(armcpu_t *armcpu, u8 mode);
-static u32 armcpu_prefetch(armcpu_t *armcpu);
-u32 armcpu_exec(armcpu_t *armcpu);
+
+
+template<int PROCNUM> u32 armcpu_exec();
+
 BOOL armcpu_irqExeption(armcpu_t *armcpu);
 //BOOL armcpu_prefetchExeption(armcpu_t *armcpu);
 BOOL
@@ -276,4 +279,8 @@ static INLINE void NDS_makeInt(u8 proc_ID,u32 num)
 	}
 }
 
+//stores the currently executing arm cpu.
+//we poke values in here instead of passing them around constantly.
+extern armcpu_t *armcpu_curr;
+
 #endif
diff --git a/desmume/src/instruction_tabdef.inc b/desmume/src/instruction_tabdef.inc
index a06ca2ec8..45eac2813 100644
--- a/desmume/src/instruction_tabdef.inc
+++ b/desmume/src/instruction_tabdef.inc
@@ -20,4381 +20,4381 @@
 */
 
 TYPE_RETOUR (*CALLTYPE NOM_TAB[4096])(PARAMETRES)={
-     OP_AND_LSL_IMM,    // 000 0000 0 0000
-     OP_AND_LSL_REG,    // 000 0000 0 0001
-     OP_AND_LSR_IMM,    // 000 0000 0 0010
-     OP_AND_LSR_REG,    // 000 0000 0 0011
-     OP_AND_ASR_IMM,    // 000 0000 0 0100
-     OP_AND_ASR_REG,    // 000 0000 0 0101
-     OP_AND_ROR_IMM,    // 000 0000 0 0110
-     OP_AND_ROR_REG,    // 000 0000 0 0111
+TABDECL(     OP_AND_LSL_IMM),    // 000 0000 0 0000
+TABDECL(     OP_AND_LSL_REG),    // 000 0000 0 0001
+TABDECL(     OP_AND_LSR_IMM),    // 000 0000 0 0010
+TABDECL(     OP_AND_LSR_REG),    // 000 0000 0 0011
+TABDECL(     OP_AND_ASR_IMM),    // 000 0000 0 0100
+TABDECL(     OP_AND_ASR_REG),    // 000 0000 0 0101
+TABDECL(     OP_AND_ROR_IMM),    // 000 0000 0 0110
+TABDECL(     OP_AND_ROR_REG),    // 000 0000 0 0111
      
-     OP_AND_LSL_IMM,    // 000 0000 0 1000
-     OP_MUL,            // 000 0000 0 1001
-     OP_AND_LSR_IMM,    // 000 0000 0 1010
-     OP_STRH_POS_INDE_M_REG_OFF, // 000 0000 0 1011
-     OP_AND_ASR_IMM,    // 000 0000 0 1100
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_AND_LSL_IMM),    // 000 0000 0 1000
+TABDECL(     OP_MUL),            // 000 0000 0 1001
+TABDECL(     OP_AND_LSR_IMM),    // 000 0000 0 1010
+TABDECL(     OP_STRH_POS_INDE_M_REG_OFF), // 000 0000 0 1011
+TABDECL(     OP_AND_ASR_IMM),    // 000 0000 0 1100
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0000 0 1101
-     OP_AND_ROR_IMM,    // 000 0000 0 1110
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_AND_ROR_IMM),    // 000 0000 0 1110
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0000 0 1111
      
-     OP_AND_S_LSL_IMM,  // 000 0000 1 0000
-     OP_AND_S_LSL_REG,  // 000 0000 1 0001
-     OP_AND_S_LSR_IMM,  // 000 0000 1 0010
-     OP_AND_S_LSR_REG,  // 000 0000 1 0011
-     OP_AND_S_ASR_IMM,  // 000 0000 1 0100
-     OP_AND_S_ASR_REG,  // 000 0000 1 0101
-     OP_AND_S_ROR_IMM,  // 000 0000 1 0110
-     OP_AND_S_ROR_REG,  // 000 0000 1 0111
+TABDECL(     OP_AND_S_LSL_IMM),  // 000 0000 1 0000
+TABDECL(     OP_AND_S_LSL_REG),  // 000 0000 1 0001
+TABDECL(     OP_AND_S_LSR_IMM),  // 000 0000 1 0010
+TABDECL(     OP_AND_S_LSR_REG),  // 000 0000 1 0011
+TABDECL(     OP_AND_S_ASR_IMM),  // 000 0000 1 0100
+TABDECL(     OP_AND_S_ASR_REG),  // 000 0000 1 0101
+TABDECL(     OP_AND_S_ROR_IMM),  // 000 0000 1 0110
+TABDECL(     OP_AND_S_ROR_REG),  // 000 0000 1 0111
      
-     OP_AND_S_LSL_IMM,  // 000 0000 1 1000
-     OP_MUL_S,          // 000 0000 1 1001
-     OP_AND_S_LSR_IMM,  // 000 0000 1 1010
-     OP_LDRH_POS_INDE_M_REG_OFF, // 000 0000 1 1011
-     OP_AND_S_ASR_IMM,  // 000 0000 1 1100
-     OP_LDRSB_POS_INDE_M_REG_OFF,// 000 0000 1 1101
-     OP_AND_S_ROR_IMM,  // 000 0000 1 1110
-     OP_LDRSH_POS_INDE_M_REG_OFF,// 000 0000 1 1111
+TABDECL(     OP_AND_S_LSL_IMM),  // 000 0000 1 1000
+TABDECL(     OP_MUL_S),          // 000 0000 1 1001
+TABDECL(     OP_AND_S_LSR_IMM),  // 000 0000 1 1010
+TABDECL(     OP_LDRH_POS_INDE_M_REG_OFF), // 000 0000 1 1011
+TABDECL(     OP_AND_S_ASR_IMM),  // 000 0000 1 1100
+TABDECL(     OP_LDRSB_POS_INDE_M_REG_OFF),// 000 0000 1 1101
+TABDECL(     OP_AND_S_ROR_IMM),  // 000 0000 1 1110
+TABDECL(     OP_LDRSH_POS_INDE_M_REG_OFF),// 000 0000 1 1111
      
-     OP_EOR_LSL_IMM,    // 000 0001 0 0000
-     OP_EOR_LSL_REG,    // 000 0001 0 0001
-     OP_EOR_LSR_IMM,    // 000 0001 0 0010
-     OP_EOR_LSR_REG,    // 000 0001 0 0011
-     OP_EOR_ASR_IMM,    // 000 0001 0 0100
-     OP_EOR_ASR_REG,    // 000 0001 0 0101
-     OP_EOR_ROR_IMM,    // 000 0001 0 0110
-     OP_EOR_ROR_REG,    // 000 0001 0 0111
+TABDECL(     OP_EOR_LSL_IMM),    // 000 0001 0 0000
+TABDECL(     OP_EOR_LSL_REG),    // 000 0001 0 0001
+TABDECL(     OP_EOR_LSR_IMM),    // 000 0001 0 0010
+TABDECL(     OP_EOR_LSR_REG),    // 000 0001 0 0011
+TABDECL(     OP_EOR_ASR_IMM),    // 000 0001 0 0100
+TABDECL(     OP_EOR_ASR_REG),    // 000 0001 0 0101
+TABDECL(     OP_EOR_ROR_IMM),    // 000 0001 0 0110
+TABDECL(     OP_EOR_ROR_REG),    // 000 0001 0 0111
      
-     OP_EOR_LSL_IMM,    // 000 0001 0 1000
-     OP_MLA,            // 000 0001 0 1001
-     OP_EOR_LSR_IMM,    // OOO OOO1 O 1010
-     OP_UND,            // 000 0001 0 1011
-     OP_EOR_ASR_IMM,    // 000 0001 0 1100
-     OP_UND,            // 000 0001 0 1101
-     OP_EOR_ROR_IMM,    // 000 0001 0 1110
-     OP_UND,            // 000 0001 0 1111
+TABDECL(     OP_EOR_LSL_IMM),    // 000 0001 0 1000
+TABDECL(     OP_MLA),            // 000 0001 0 1001
+TABDECL(     OP_EOR_LSR_IMM),    // OOO OOO1 O 1010
+TABDECL(     OP_UND),            // 000 0001 0 1011
+TABDECL(     OP_EOR_ASR_IMM),    // 000 0001 0 1100
+TABDECL(     OP_UND),            // 000 0001 0 1101
+TABDECL(     OP_EOR_ROR_IMM),    // 000 0001 0 1110
+TABDECL(     OP_UND),            // 000 0001 0 1111
      
-     OP_EOR_S_LSL_IMM,  // 000 0001 1 0000
-     OP_EOR_S_LSL_REG,  // 000 0001 1 0001
-     OP_EOR_S_LSR_IMM,  // 000 0001 1 0010
-     OP_EOR_S_LSR_REG,  // 000 0001 1 0011
-     OP_EOR_S_ASR_IMM,  // 000 0001 1 0100
-     OP_EOR_S_ASR_REG,  // 000 0001 1 0101
-     OP_EOR_S_ROR_IMM,  // 000 0001 1 0110
-     OP_EOR_S_ROR_REG,  // 000 0001 1 0111
+TABDECL(     OP_EOR_S_LSL_IMM),  // 000 0001 1 0000
+TABDECL(     OP_EOR_S_LSL_REG),  // 000 0001 1 0001
+TABDECL(     OP_EOR_S_LSR_IMM),  // 000 0001 1 0010
+TABDECL(     OP_EOR_S_LSR_REG),  // 000 0001 1 0011
+TABDECL(     OP_EOR_S_ASR_IMM),  // 000 0001 1 0100
+TABDECL(     OP_EOR_S_ASR_REG),  // 000 0001 1 0101
+TABDECL(     OP_EOR_S_ROR_IMM),  // 000 0001 1 0110
+TABDECL(     OP_EOR_S_ROR_REG),  // 000 0001 1 0111
      
-     OP_EOR_S_LSL_IMM,  // 000 0001 1 1000
-     OP_MLA_S,          // 000 0001 1 1001
-     OP_EOR_S_LSR_IMM,  // 000 0001 1 1010
-     OP_UND,            // 000 0001 1 1011
-     OP_EOR_S_ASR_IMM,  // 000 0001 1 1100
-     OP_UND,            // 000 0001 1 1101
-     OP_EOR_S_ROR_IMM,  // 000 0001 1 1110
-     OP_UND,            // 000 0001 1 1111
+TABDECL(     OP_EOR_S_LSL_IMM),  // 000 0001 1 1000
+TABDECL(     OP_MLA_S),          // 000 0001 1 1001
+TABDECL(     OP_EOR_S_LSR_IMM),  // 000 0001 1 1010
+TABDECL(     OP_UND),            // 000 0001 1 1011
+TABDECL(     OP_EOR_S_ASR_IMM),  // 000 0001 1 1100
+TABDECL(     OP_UND),            // 000 0001 1 1101
+TABDECL(     OP_EOR_S_ROR_IMM),  // 000 0001 1 1110
+TABDECL(     OP_UND),            // 000 0001 1 1111
 
-     OP_SUB_LSL_IMM,    // 000 0010 0 0000
-     OP_SUB_LSL_REG,    // 000 0010 0 0001
-     OP_SUB_LSR_IMM,    // 000 0010 0 0010
-     OP_SUB_LSR_REG,    // 000 0010 0 0011
-     OP_SUB_ASR_IMM,    // 000 0010 0 0100
-     OP_SUB_ASR_REG,    // 000 0010 0 0101
-     OP_SUB_ROR_IMM,    // 000 0010 0 0110
-     OP_SUB_ROR_REG,    // 000 0010 0 0111
+TABDECL(     OP_SUB_LSL_IMM),    // 000 0010 0 0000
+TABDECL(     OP_SUB_LSL_REG),    // 000 0010 0 0001
+TABDECL(     OP_SUB_LSR_IMM),    // 000 0010 0 0010
+TABDECL(     OP_SUB_LSR_REG),    // 000 0010 0 0011
+TABDECL(     OP_SUB_ASR_IMM),    // 000 0010 0 0100
+TABDECL(     OP_SUB_ASR_REG),    // 000 0010 0 0101
+TABDECL(     OP_SUB_ROR_IMM),    // 000 0010 0 0110
+TABDECL(     OP_SUB_ROR_REG),    // 000 0010 0 0111
      
-     OP_SUB_LSL_IMM,    // 000 0010 0 1000
-     OP_UND,            // 000 0010 0 1001
-     OP_SUB_LSR_IMM,    // OOO OO1O O 1010
-     OP_STRH_POS_INDE_M_IMM_OFF, // 000 0010 0 1011
-     OP_SUB_ASR_IMM,    // 000 0010 0 1100
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_SUB_LSL_IMM),    // 000 0010 0 1000
+TABDECL(     OP_UND),            // 000 0010 0 1001
+TABDECL(     OP_SUB_LSR_IMM),    // OOO OO1O O 1010
+TABDECL(     OP_STRH_POS_INDE_M_IMM_OFF), // 000 0010 0 1011
+TABDECL(     OP_SUB_ASR_IMM),    // 000 0010 0 1100
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0010 0 1101
-     OP_SUB_ROR_IMM,    // 000 0010 0 1110
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_SUB_ROR_IMM),    // 000 0010 0 1110
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0010 0 1111
      
-     OP_SUB_S_LSL_IMM,  // 000 0010 1 0000
-     OP_SUB_S_LSL_REG,  // 000 0010 1 0001
-     OP_SUB_S_LSR_IMM,  // 000 0010 1 0010
-     OP_SUB_S_LSR_REG,  // 000 0010 1 0011
-     OP_SUB_S_ASR_IMM,  // 000 0010 1 0100
-     OP_SUB_S_ASR_REG,  // 000 0010 1 0101
-     OP_SUB_S_ROR_IMM,  // 000 0010 1 0110
-     OP_SUB_S_ROR_REG,  // 000 0010 1 0111
+TABDECL(     OP_SUB_S_LSL_IMM),  // 000 0010 1 0000
+TABDECL(     OP_SUB_S_LSL_REG),  // 000 0010 1 0001
+TABDECL(     OP_SUB_S_LSR_IMM),  // 000 0010 1 0010
+TABDECL(     OP_SUB_S_LSR_REG),  // 000 0010 1 0011
+TABDECL(     OP_SUB_S_ASR_IMM),  // 000 0010 1 0100
+TABDECL(     OP_SUB_S_ASR_REG),  // 000 0010 1 0101
+TABDECL(     OP_SUB_S_ROR_IMM),  // 000 0010 1 0110
+TABDECL(     OP_SUB_S_ROR_REG),  // 000 0010 1 0111
      
-     OP_SUB_S_LSL_IMM,  // 000 0010 1 1000
-     OP_UND,            // 000 0010 1 1001
-     OP_SUB_S_LSR_IMM,  // 000 0010 1 1010
-     OP_LDRH_POS_INDE_M_IMM_OFF, // 000 0010 1 1011
-     OP_SUB_S_ASR_IMM,  // 000 0010 1 1100
-     OP_LDRSB_POS_INDE_M_IMM_OFF,// 000 0010 1 1101
-     OP_SUB_S_ROR_IMM,  // 000 0010 1 1110
-     OP_LDRSH_POS_INDE_M_IMM_OFF,// 000 0010 1 1111
+TABDECL(     OP_SUB_S_LSL_IMM),  // 000 0010 1 1000
+TABDECL(     OP_UND),            // 000 0010 1 1001
+TABDECL(     OP_SUB_S_LSR_IMM),  // 000 0010 1 1010
+TABDECL(     OP_LDRH_POS_INDE_M_IMM_OFF), // 000 0010 1 1011
+TABDECL(     OP_SUB_S_ASR_IMM),  // 000 0010 1 1100
+TABDECL(     OP_LDRSB_POS_INDE_M_IMM_OFF),// 000 0010 1 1101
+TABDECL(     OP_SUB_S_ROR_IMM),  // 000 0010 1 1110
+TABDECL(     OP_LDRSH_POS_INDE_M_IMM_OFF),// 000 0010 1 1111
 //--------------------     
-     OP_RSB_LSL_IMM,    // 000 0011 0 0000
-     OP_RSB_LSL_REG,    // 000 0011 0 0001
-     OP_RSB_LSR_IMM,    // 000 0011 0 0010
-     OP_RSB_LSR_REG,    // 000 0011 0 0011
-     OP_RSB_ASR_IMM,    // 000 0011 0 0100
-     OP_RSB_ASR_REG,    // 000 0011 0 0101
-     OP_RSB_ROR_IMM,    // 000 0011 0 0110
-     OP_RSB_ROR_REG,    // 000 0011 0 0111
+TABDECL(     OP_RSB_LSL_IMM),    // 000 0011 0 0000
+TABDECL(     OP_RSB_LSL_REG),    // 000 0011 0 0001
+TABDECL(     OP_RSB_LSR_IMM),    // 000 0011 0 0010
+TABDECL(     OP_RSB_LSR_REG),    // 000 0011 0 0011
+TABDECL(     OP_RSB_ASR_IMM),    // 000 0011 0 0100
+TABDECL(     OP_RSB_ASR_REG),    // 000 0011 0 0101
+TABDECL(     OP_RSB_ROR_IMM),    // 000 0011 0 0110
+TABDECL(     OP_RSB_ROR_REG),    // 000 0011 0 0111
      
-     OP_RSB_LSL_IMM,    // 000 0011 0 1000
-     OP_UND,            // 000 0011 0 1001
-     OP_RSB_LSR_IMM,    // OOO OO11 O 1010
-     OP_UND,            // 000 0011 0 1011
-     OP_RSB_ASR_IMM,    // 000 0011 0 1100
-     OP_UND,            // 000 0011 0 1101
-     OP_RSB_ROR_IMM,    // 000 0011 0 1110
-     OP_UND,            // 000 0011 0 1111
+TABDECL(     OP_RSB_LSL_IMM),    // 000 0011 0 1000
+TABDECL(     OP_UND),            // 000 0011 0 1001
+TABDECL(     OP_RSB_LSR_IMM),    // OOO OO11 O 1010
+TABDECL(     OP_UND),            // 000 0011 0 1011
+TABDECL(     OP_RSB_ASR_IMM),    // 000 0011 0 1100
+TABDECL(     OP_UND),            // 000 0011 0 1101
+TABDECL(     OP_RSB_ROR_IMM),    // 000 0011 0 1110
+TABDECL(     OP_UND),            // 000 0011 0 1111
      
-     OP_RSB_S_LSL_IMM,  // 000 0011 1 0000
-     OP_RSB_S_LSL_REG,  // 000 0011 1 0001
-     OP_RSB_S_LSR_IMM,  // 000 0011 1 0010
-     OP_RSB_S_LSR_REG,  // 000 0011 1 0011
-     OP_RSB_S_ASR_IMM,  // 000 0011 1 0100
-     OP_RSB_S_ASR_REG,  // 000 0011 1 0101
-     OP_RSB_S_ROR_IMM,  // 000 0011 1 0110
-     OP_RSB_S_ROR_REG,  // 000 0011 1 0111
+TABDECL(     OP_RSB_S_LSL_IMM),  // 000 0011 1 0000
+TABDECL(     OP_RSB_S_LSL_REG),  // 000 0011 1 0001
+TABDECL(     OP_RSB_S_LSR_IMM),  // 000 0011 1 0010
+TABDECL(     OP_RSB_S_LSR_REG),  // 000 0011 1 0011
+TABDECL(     OP_RSB_S_ASR_IMM),  // 000 0011 1 0100
+TABDECL(     OP_RSB_S_ASR_REG),  // 000 0011 1 0101
+TABDECL(     OP_RSB_S_ROR_IMM),  // 000 0011 1 0110
+TABDECL(     OP_RSB_S_ROR_REG),  // 000 0011 1 0111
      
-     OP_RSB_S_LSL_IMM,  // 000 0011 1 1000
-     OP_UND,            // 000 0011 1 1001
-     OP_RSB_S_LSR_IMM,  // 000 0011 1 1010
-     OP_UND,            // 000 0011 1 1011
-     OP_RSB_S_ASR_IMM,  // 000 0011 1 1100
-     OP_UND,            // 000 0011 1 1101
-     OP_RSB_S_ROR_IMM,  // 000 0011 1 1110
-     OP_UND,            // 000 0011 1 1111
+TABDECL(     OP_RSB_S_LSL_IMM),  // 000 0011 1 1000
+TABDECL(     OP_UND),            // 000 0011 1 1001
+TABDECL(     OP_RSB_S_LSR_IMM),  // 000 0011 1 1010
+TABDECL(     OP_UND),            // 000 0011 1 1011
+TABDECL(     OP_RSB_S_ASR_IMM),  // 000 0011 1 1100
+TABDECL(     OP_UND),            // 000 0011 1 1101
+TABDECL(     OP_RSB_S_ROR_IMM),  // 000 0011 1 1110
+TABDECL(     OP_UND),            // 000 0011 1 1111
 //--------------------------
-     OP_ADD_LSL_IMM,    // 000 0100 0 0000
-     OP_ADD_LSL_REG,    // 000 0100 0 0001
-     OP_ADD_LSR_IMM,    // 000 0100 0 0010
-     OP_ADD_LSR_REG,    // 000 0100 0 0011
-     OP_ADD_ASR_IMM,    // 000 0100 0 0100
-     OP_ADD_ASR_REG,    // 000 0100 0 0101
-     OP_ADD_ROR_IMM,    // 000 0100 0 0110
-     OP_ADD_ROR_REG,    // 000 0100 0 0111
+TABDECL(     OP_ADD_LSL_IMM),    // 000 0100 0 0000
+TABDECL(     OP_ADD_LSL_REG),    // 000 0100 0 0001
+TABDECL(     OP_ADD_LSR_IMM),    // 000 0100 0 0010
+TABDECL(     OP_ADD_LSR_REG),    // 000 0100 0 0011
+TABDECL(     OP_ADD_ASR_IMM),    // 000 0100 0 0100
+TABDECL(     OP_ADD_ASR_REG),    // 000 0100 0 0101
+TABDECL(     OP_ADD_ROR_IMM),    // 000 0100 0 0110
+TABDECL(     OP_ADD_ROR_REG),    // 000 0100 0 0111
      
-     OP_ADD_LSL_IMM,    // 000 0100 0 1000
-     OP_UMULL,          // 000 0100 0 1001
-     OP_ADD_LSR_IMM,    // OOO O10O O 1010
-     OP_STRH_POS_INDE_P_REG_OFF, // 000 0100 0 1011
-     OP_ADD_ASR_IMM,    // 000 0100 0 1100
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_ADD_LSL_IMM),    // 000 0100 0 1000
+TABDECL(     OP_UMULL),          // 000 0100 0 1001
+TABDECL(     OP_ADD_LSR_IMM),    // OOO O10O O 1010
+TABDECL(     OP_STRH_POS_INDE_P_REG_OFF), // 000 0100 0 1011
+TABDECL(     OP_ADD_ASR_IMM),    // 000 0100 0 1100
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0100 0 1101
-     OP_ADD_ROR_IMM,    // 000 0100 0 1110
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_ADD_ROR_IMM),    // 000 0100 0 1110
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0100 0 1111
      
-     OP_ADD_S_LSL_IMM,  // 000 0100 1 0000
-     OP_ADD_S_LSL_REG,  // 000 0100 1 0001
-     OP_ADD_S_LSR_IMM,  // 000 0100 1 0010
-     OP_ADD_S_LSR_REG,  // 000 0100 1 0011
-     OP_ADD_S_ASR_IMM,  // 000 0100 1 0100
-     OP_ADD_S_ASR_REG,  // 000 0100 1 0101
-     OP_ADD_S_ROR_IMM,  // 000 0100 1 0110
-     OP_ADD_S_ROR_REG,  // 000 0100 1 0111
+TABDECL(     OP_ADD_S_LSL_IMM),  // 000 0100 1 0000
+TABDECL(     OP_ADD_S_LSL_REG),  // 000 0100 1 0001
+TABDECL(     OP_ADD_S_LSR_IMM),  // 000 0100 1 0010
+TABDECL(     OP_ADD_S_LSR_REG),  // 000 0100 1 0011
+TABDECL(     OP_ADD_S_ASR_IMM),  // 000 0100 1 0100
+TABDECL(     OP_ADD_S_ASR_REG),  // 000 0100 1 0101
+TABDECL(     OP_ADD_S_ROR_IMM),  // 000 0100 1 0110
+TABDECL(     OP_ADD_S_ROR_REG),  // 000 0100 1 0111
      
-     OP_ADD_S_LSL_IMM,  // 000 0100 1 1000
-     OP_UMULL_S,        // 000 0100 1 1001
-     OP_ADD_S_LSR_IMM,  // 000 0100 1 1010
-     OP_LDRH_POS_INDE_P_REG_OFF, // 000 0100 1 1011
-     OP_ADD_S_ASR_IMM,  // 000 0100 1 1100
-     OP_LDRSB_POS_INDE_P_REG_OFF,// 000 0100 1 1101
-     OP_ADD_S_ROR_IMM,  // 000 0100 1 1110
-     OP_LDRSH_POS_INDE_P_REG_OFF,// 000 0100 1 1111
+TABDECL(     OP_ADD_S_LSL_IMM),  // 000 0100 1 1000
+TABDECL(     OP_UMULL_S),        // 000 0100 1 1001
+TABDECL(     OP_ADD_S_LSR_IMM),  // 000 0100 1 1010
+TABDECL(     OP_LDRH_POS_INDE_P_REG_OFF), // 000 0100 1 1011
+TABDECL(     OP_ADD_S_ASR_IMM),  // 000 0100 1 1100
+TABDECL(     OP_LDRSB_POS_INDE_P_REG_OFF),// 000 0100 1 1101
+TABDECL(     OP_ADD_S_ROR_IMM),  // 000 0100 1 1110
+TABDECL(     OP_LDRSH_POS_INDE_P_REG_OFF),// 000 0100 1 1111
 //-----------------------------------------
-     OP_ADC_LSL_IMM,    // 000 0101 0 0000
-     OP_ADC_LSL_REG,    // 000 0101 0 0001
-     OP_ADC_LSR_IMM,    // 000 0101 0 0010
-     OP_ADC_LSR_REG,    // 000 0101 0 0011
-     OP_ADC_ASR_IMM,    // 000 0101 0 0100
-     OP_ADC_ASR_REG,    // 000 0101 0 0101
-     OP_ADC_ROR_IMM,    // 000 0101 0 0110
-     OP_ADC_ROR_REG,    // 000 0101 0 0111
+TABDECL(     OP_ADC_LSL_IMM),    // 000 0101 0 0000
+TABDECL(     OP_ADC_LSL_REG),    // 000 0101 0 0001
+TABDECL(     OP_ADC_LSR_IMM),    // 000 0101 0 0010
+TABDECL(     OP_ADC_LSR_REG),    // 000 0101 0 0011
+TABDECL(     OP_ADC_ASR_IMM),    // 000 0101 0 0100
+TABDECL(     OP_ADC_ASR_REG),    // 000 0101 0 0101
+TABDECL(     OP_ADC_ROR_IMM),    // 000 0101 0 0110
+TABDECL(     OP_ADC_ROR_REG),    // 000 0101 0 0111
      
-     OP_ADC_LSL_IMM,    // 000 0101 0 1000
-     OP_UMLAL,          // 000 0101 0 1001
-     OP_ADC_LSR_IMM,    // OOO O101 O 1010
-     OP_UND,            // 000 0101 0 1011
-     OP_ADC_ASR_IMM,    // 000 0101 0 1100
-     OP_UND,            // 000 0101 0 1101
-     OP_ADC_ROR_IMM,    // 000 0101 0 1110
-     OP_UND,            // 000 0101 0 1111
+TABDECL(     OP_ADC_LSL_IMM),    // 000 0101 0 1000
+TABDECL(     OP_UMLAL),          // 000 0101 0 1001
+TABDECL(     OP_ADC_LSR_IMM),    // OOO O101 O 1010
+TABDECL(     OP_UND),            // 000 0101 0 1011
+TABDECL(     OP_ADC_ASR_IMM),    // 000 0101 0 1100
+TABDECL(     OP_UND),            // 000 0101 0 1101
+TABDECL(     OP_ADC_ROR_IMM),    // 000 0101 0 1110
+TABDECL(     OP_UND),            // 000 0101 0 1111
      
-     OP_ADC_S_LSL_IMM,  // 000 0101 1 0000
-     OP_ADC_S_LSL_REG,  // 000 0101 1 0001
-     OP_ADC_S_LSR_IMM,  // 000 0101 1 0010
-     OP_ADC_S_LSR_REG,  // 000 0101 1 0011
-     OP_ADC_S_ASR_IMM,  // 000 0101 1 0100
-     OP_ADC_S_ASR_REG,  // 000 0101 1 0101
-     OP_ADC_S_ROR_IMM,  // 000 0101 1 0110
-     OP_ADC_S_ROR_REG,  // 000 0101 1 0111
+TABDECL(     OP_ADC_S_LSL_IMM),  // 000 0101 1 0000
+TABDECL(     OP_ADC_S_LSL_REG),  // 000 0101 1 0001
+TABDECL(     OP_ADC_S_LSR_IMM),  // 000 0101 1 0010
+TABDECL(     OP_ADC_S_LSR_REG),  // 000 0101 1 0011
+TABDECL(     OP_ADC_S_ASR_IMM),  // 000 0101 1 0100
+TABDECL(     OP_ADC_S_ASR_REG),  // 000 0101 1 0101
+TABDECL(     OP_ADC_S_ROR_IMM),  // 000 0101 1 0110
+TABDECL(     OP_ADC_S_ROR_REG),  // 000 0101 1 0111
      
-     OP_ADC_S_LSL_IMM,  // 000 0101 1 1000
-     OP_UMLAL_S,        // 000 0101 1 1001
-     OP_ADC_S_LSR_IMM,  // 000 0101 1 1010
-     OP_UND,            // 000 0101 1 1011
-     OP_ADC_S_ASR_IMM,  // 000 0101 1 1100
-     OP_UND,            // 000 0101 1 1101
-     OP_ADC_S_ROR_IMM,  // 000 0101 1 1110
-     OP_UND,            // 000 0101 1 1111
+TABDECL(     OP_ADC_S_LSL_IMM),  // 000 0101 1 1000
+TABDECL(     OP_UMLAL_S),        // 000 0101 1 1001
+TABDECL(     OP_ADC_S_LSR_IMM),  // 000 0101 1 1010
+TABDECL(     OP_UND),            // 000 0101 1 1011
+TABDECL(     OP_ADC_S_ASR_IMM),  // 000 0101 1 1100
+TABDECL(     OP_UND),            // 000 0101 1 1101
+TABDECL(     OP_ADC_S_ROR_IMM),  // 000 0101 1 1110
+TABDECL(     OP_UND),            // 000 0101 1 1111
 //------------------------------------------
-     OP_SBC_LSL_IMM,    // 000 0110 0 0000
-     OP_SBC_LSL_REG,    // 000 0110 0 0001
-     OP_SBC_LSR_IMM,    // 000 0110 0 0010
-     OP_SBC_LSR_REG,    // 000 0110 0 0011
-     OP_SBC_ASR_IMM,    // 000 0110 0 0100
-     OP_SBC_ASR_REG,    // 000 0110 0 0101
-     OP_SBC_ROR_IMM,    // 000 0110 0 0110
-     OP_SBC_ROR_REG,    // 000 0110 0 0111
+TABDECL(     OP_SBC_LSL_IMM),    // 000 0110 0 0000
+TABDECL(     OP_SBC_LSL_REG),    // 000 0110 0 0001
+TABDECL(     OP_SBC_LSR_IMM),    // 000 0110 0 0010
+TABDECL(     OP_SBC_LSR_REG),    // 000 0110 0 0011
+TABDECL(     OP_SBC_ASR_IMM),    // 000 0110 0 0100
+TABDECL(     OP_SBC_ASR_REG),    // 000 0110 0 0101
+TABDECL(     OP_SBC_ROR_IMM),    // 000 0110 0 0110
+TABDECL(     OP_SBC_ROR_REG),    // 000 0110 0 0111
      
-     OP_SBC_LSL_IMM,    // 000 0110 0 1000
-     OP_SMULL,          // 000 0110 0 1001
-     OP_SBC_LSR_IMM,    // OOO O11O O 1010
-     OP_STRH_POS_INDE_P_IMM_OFF, // 000 0110 0 1011
-     OP_SBC_ASR_IMM,    // 000 0110 0 1100
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_SBC_LSL_IMM),    // 000 0110 0 1000
+TABDECL(     OP_SMULL),          // 000 0110 0 1001
+TABDECL(     OP_SBC_LSR_IMM),    // OOO O11O O 1010
+TABDECL(     OP_STRH_POS_INDE_P_IMM_OFF), // 000 0110 0 1011
+TABDECL(     OP_SBC_ASR_IMM),    // 000 0110 0 1100
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0110 0 1101
-     OP_SBC_ROR_IMM,    // 000 0110 0 1110
-     OP_LDRD_STRD_POST_INDEX,
+TABDECL(     OP_SBC_ROR_IMM),    // 000 0110 0 1110
+TABDECL(     OP_LDRD_STRD_POST_INDEX),
                         // 000 0110 0 1111
      
-     OP_SBC_S_LSL_IMM,  // 000 0110 1 0000
-     OP_SBC_S_LSL_REG,  // 000 0110 1 0001
-     OP_SBC_S_LSR_IMM,  // 000 0110 1 0010
-     OP_SBC_S_LSR_REG,  // 000 0110 1 0011
-     OP_SBC_S_ASR_IMM,  // 000 0110 1 0100
-     OP_SBC_S_ASR_REG,  // 000 0110 1 0101
-     OP_SBC_S_ROR_IMM,  // 000 0110 1 0110
-     OP_SBC_S_ROR_REG,  // 000 0110 1 0111
+TABDECL(     OP_SBC_S_LSL_IMM),  // 000 0110 1 0000
+TABDECL(     OP_SBC_S_LSL_REG),  // 000 0110 1 0001
+TABDECL(     OP_SBC_S_LSR_IMM),  // 000 0110 1 0010
+TABDECL(     OP_SBC_S_LSR_REG),  // 000 0110 1 0011
+TABDECL(     OP_SBC_S_ASR_IMM),  // 000 0110 1 0100
+TABDECL(     OP_SBC_S_ASR_REG),  // 000 0110 1 0101
+TABDECL(     OP_SBC_S_ROR_IMM),  // 000 0110 1 0110
+TABDECL(     OP_SBC_S_ROR_REG),  // 000 0110 1 0111
      
-     OP_SBC_S_LSL_IMM,  // 000 0110 1 1000
-     OP_SMULL_S,        // 000 0110 1 1001
-     OP_SBC_S_LSR_IMM,  // 000 0110 1 1010
-     OP_LDRH_POS_INDE_P_IMM_OFF, // 000 0110 1 1011
-     OP_SBC_S_ASR_IMM,  // 000 0110 1 1100
-     OP_LDRSB_POS_INDE_P_IMM_OFF,// 000 0110 1 1101
-     OP_SBC_S_ROR_IMM,  // 000 0110 1 1110
-     OP_LDRSH_POS_INDE_P_IMM_OFF,// 000 0110 1 1111
+TABDECL(     OP_SBC_S_LSL_IMM),  // 000 0110 1 1000
+TABDECL(     OP_SMULL_S),        // 000 0110 1 1001
+TABDECL(     OP_SBC_S_LSR_IMM),  // 000 0110 1 1010
+TABDECL(     OP_LDRH_POS_INDE_P_IMM_OFF), // 000 0110 1 1011
+TABDECL(     OP_SBC_S_ASR_IMM),  // 000 0110 1 1100
+TABDECL(     OP_LDRSB_POS_INDE_P_IMM_OFF),// 000 0110 1 1101
+TABDECL(     OP_SBC_S_ROR_IMM),  // 000 0110 1 1110
+TABDECL(     OP_LDRSH_POS_INDE_P_IMM_OFF),// 000 0110 1 1111
 //------------------------------------------
-     OP_RSC_LSL_IMM,    // 000 0111 0 0000
-     OP_RSC_LSL_REG,    // 000 0111 0 0001
-     OP_RSC_LSR_IMM,    // 000 0111 0 0010
-     OP_RSC_LSR_REG,    // 000 0111 0 0011
-     OP_RSC_ASR_IMM,    // 000 0111 0 0100
-     OP_RSC_ASR_REG,    // 000 0111 0 0101
-     OP_RSC_ROR_IMM,    // 000 0111 0 0110
-     OP_RSC_ROR_REG,    // 000 0111 0 0111
+TABDECL(     OP_RSC_LSL_IMM),    // 000 0111 0 0000
+TABDECL(     OP_RSC_LSL_REG),    // 000 0111 0 0001
+TABDECL(     OP_RSC_LSR_IMM),    // 000 0111 0 0010
+TABDECL(     OP_RSC_LSR_REG),    // 000 0111 0 0011
+TABDECL(     OP_RSC_ASR_IMM),    // 000 0111 0 0100
+TABDECL(     OP_RSC_ASR_REG),    // 000 0111 0 0101
+TABDECL(     OP_RSC_ROR_IMM),    // 000 0111 0 0110
+TABDECL(     OP_RSC_ROR_REG),    // 000 0111 0 0111
      
-     OP_RSC_LSL_IMM,    // 000 0111 0 1000
-     OP_SMLAL,          // 000 0111 0 1001
-     OP_RSC_LSR_IMM,    // OOO O111 O 1010
-     OP_UND,            // 000 0111 0 1011
-     OP_RSC_ASR_IMM,    // 000 0111 0 1100
-     OP_UND,            // 000 0111 0 1101
-     OP_RSC_ROR_IMM,    // 000 0111 0 1110
-     OP_UND,            // 000 0111 0 1111
+TABDECL(     OP_RSC_LSL_IMM),    // 000 0111 0 1000
+TABDECL(     OP_SMLAL),          // 000 0111 0 1001
+TABDECL(     OP_RSC_LSR_IMM),    // OOO O111 O 1010
+TABDECL(     OP_UND),            // 000 0111 0 1011
+TABDECL(     OP_RSC_ASR_IMM),    // 000 0111 0 1100
+TABDECL(     OP_UND),            // 000 0111 0 1101
+TABDECL(     OP_RSC_ROR_IMM),    // 000 0111 0 1110
+TABDECL(     OP_UND),            // 000 0111 0 1111
      
-     OP_RSC_S_LSL_IMM,  // 000 0111 1 0000
-     OP_RSC_S_LSL_REG,  // 000 0111 1 0001
-     OP_RSC_S_LSR_IMM,  // 000 0111 1 0010
-     OP_RSC_S_LSR_REG,  // 000 0111 1 0011
-     OP_RSC_S_ASR_IMM,  // 000 0111 1 0100
-     OP_RSC_S_ASR_REG,  // 000 0111 1 0101
-     OP_RSC_S_ROR_IMM,  // 000 0111 1 0110
-     OP_RSC_S_ROR_REG,  // 000 0111 1 0111
+TABDECL(     OP_RSC_S_LSL_IMM),  // 000 0111 1 0000
+TABDECL(     OP_RSC_S_LSL_REG),  // 000 0111 1 0001
+TABDECL(     OP_RSC_S_LSR_IMM),  // 000 0111 1 0010
+TABDECL(     OP_RSC_S_LSR_REG),  // 000 0111 1 0011
+TABDECL(     OP_RSC_S_ASR_IMM),  // 000 0111 1 0100
+TABDECL(     OP_RSC_S_ASR_REG),  // 000 0111 1 0101
+TABDECL(     OP_RSC_S_ROR_IMM),  // 000 0111 1 0110
+TABDECL(     OP_RSC_S_ROR_REG),  // 000 0111 1 0111
      
-     OP_RSC_S_LSL_IMM,  // 000 0111 1 1000
-     OP_SMLAL_S,        // 000 0111 1 1001
-     OP_RSC_S_LSR_IMM,  // 000 0111 1 1010
-     OP_UND,            // 000 0111 1 1011
-     OP_RSC_S_ASR_IMM,  // 000 0111 1 1100
-     OP_UND,            // 000 0111 1 1101
-     OP_RSC_S_ROR_IMM,  // 000 0111 1 1110
-     OP_UND,            // 000 0111 1 1111
+TABDECL(     OP_RSC_S_LSL_IMM),  // 000 0111 1 1000
+TABDECL(     OP_SMLAL_S),        // 000 0111 1 1001
+TABDECL(     OP_RSC_S_LSR_IMM),  // 000 0111 1 1010
+TABDECL(     OP_UND),            // 000 0111 1 1011
+TABDECL(     OP_RSC_S_ASR_IMM),  // 000 0111 1 1100
+TABDECL(     OP_UND),            // 000 0111 1 1101
+TABDECL(     OP_RSC_S_ROR_IMM),  // 000 0111 1 1110
+TABDECL(     OP_UND),            // 000 0111 1 1111
 //------------------------------------------
-     OP_MRS_CPSR,       // 000 1000 0 0000
-     OP_UND,            // 000 1000 0 0001
-     OP_UND,            // 000 1000 0 0010
-     OP_UND,            // 000 1000 0 0011
-     OP_UND,            // 000 1000 0 0100
-     OP_QADD,           // 000 1000 0 0101
-     OP_UND,            // 000 1000 0 0110
-     OP_UND,            // 000 1000 0 0111         
+TABDECL(     OP_MRS_CPSR),       // 000 1000 0 0000
+TABDECL(     OP_UND),            // 000 1000 0 0001
+TABDECL(     OP_UND),            // 000 1000 0 0010
+TABDECL(     OP_UND),            // 000 1000 0 0011
+TABDECL(     OP_UND),            // 000 1000 0 0100
+TABDECL(     OP_QADD),           // 000 1000 0 0101
+TABDECL(     OP_UND),            // 000 1000 0 0110
+TABDECL(     OP_UND),            // 000 1000 0 0111         
      
-     OP_SMLA_B_B,       // 000 1000 0 1000
-     OP_SWP,            // 000 1000 0 1001
-     OP_SMLA_T_B,       // 000 1000 0 1010
-     OP_STRH_M_REG_OFF, // 000 1000 0 1011
-     OP_SMLA_B_T,       // 000 1000 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMLA_B_B),       // 000 1000 0 1000
+TABDECL(     OP_SWP),            // 000 1000 0 1001
+TABDECL(     OP_SMLA_T_B),       // 000 1000 0 1010
+TABDECL(     OP_STRH_M_REG_OFF), // 000 1000 0 1011
+TABDECL(     OP_SMLA_B_T),       // 000 1000 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1000 0 1101
-     OP_SMLA_T_T,       // 000 1000 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMLA_T_T),       // 000 1000 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1000 0 1111
 
-     OP_TST_LSL_IMM,    // 000 1000 1 0000
-     OP_TST_LSL_REG,    // 000 1000 1 0001
-     OP_TST_LSR_IMM,    // 000 1000 1 0010
-     OP_TST_LSR_REG,    // 000 1000 1 0011
-     OP_TST_ASR_IMM,    // 000 1000 1 0100
-     OP_TST_ASR_REG,    // 000 1000 1 0101
-     OP_TST_ROR_IMM,    // 000 1000 1 0110
-     OP_TST_ROR_REG,    // 000 1000 1 0111
+TABDECL(     OP_TST_LSL_IMM),    // 000 1000 1 0000
+TABDECL(     OP_TST_LSL_REG),    // 000 1000 1 0001
+TABDECL(     OP_TST_LSR_IMM),    // 000 1000 1 0010
+TABDECL(     OP_TST_LSR_REG),    // 000 1000 1 0011
+TABDECL(     OP_TST_ASR_IMM),    // 000 1000 1 0100
+TABDECL(     OP_TST_ASR_REG),    // 000 1000 1 0101
+TABDECL(     OP_TST_ROR_IMM),    // 000 1000 1 0110
+TABDECL(     OP_TST_ROR_REG),    // 000 1000 1 0111
      
-     OP_TST_LSL_IMM,    // 000 1000 1 1000
-     OP_UND,            // 000 1000 1 1001
-     OP_TST_LSR_IMM,    // OOO 100O 1 1010
-     OP_LDRH_M_REG_OFF, // 000 1000 1 1011
-     OP_TST_ASR_IMM,    // 000 1000 1 1100
-     OP_LDRSB_M_REG_OFF,// 000 1000 1 1101
-     OP_TST_ROR_IMM,    // 000 1000 1 1110
-     OP_LDRSH_M_REG_OFF,// 000 1000 1 1111
+TABDECL(     OP_TST_LSL_IMM),    // 000 1000 1 1000
+TABDECL(     OP_UND),            // 000 1000 1 1001
+TABDECL(     OP_TST_LSR_IMM),    // OOO 100O 1 1010
+TABDECL(     OP_LDRH_M_REG_OFF), // 000 1000 1 1011
+TABDECL(     OP_TST_ASR_IMM),    // 000 1000 1 1100
+TABDECL(     OP_LDRSB_M_REG_OFF),// 000 1000 1 1101
+TABDECL(     OP_TST_ROR_IMM),    // 000 1000 1 1110
+TABDECL(     OP_LDRSH_M_REG_OFF),// 000 1000 1 1111
 //------------------------------------------
-     OP_MSR_CPSR,       // 000 1001 0 0000
-     OP_BX,             // 000 1001 0 0001
-     OP_UND,            // 000 1001 0 0010
-     OP_BLX_REG,        // 000 1001 0 0011
-     OP_UND,            // 000 1001 0 0100
-     OP_QSUB,           // 000 1001 0 0101
-     OP_UND,            // 000 1001 0 0110
-     OP_BKPT,            // 000 1001 0 0111  
+TABDECL(     OP_MSR_CPSR),       // 000 1001 0 0000
+TABDECL(     OP_BX),             // 000 1001 0 0001
+TABDECL(     OP_UND),            // 000 1001 0 0010
+TABDECL(     OP_BLX_REG),        // 000 1001 0 0011
+TABDECL(     OP_UND),            // 000 1001 0 0100
+TABDECL(     OP_QSUB),           // 000 1001 0 0101
+TABDECL(     OP_UND),            // 000 1001 0 0110
+TABDECL(     OP_BKPT),            // 000 1001 0 0111  
      
-     OP_SMLAW_B,      // 000 1001 0 1000
-     OP_UND,          // 000 1001 0 1001
-     OP_SMULW_B,          // 000 1001 0 1010
-     OP_STRH_PRE_INDE_M_REG_OFF,  // 000 1001 0 1011
-     OP_SMLAW_T,      // 000 1001 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMLAW_B),      // 000 1001 0 1000
+TABDECL(     OP_UND),          // 000 1001 0 1001
+TABDECL(     OP_SMULW_B),          // 000 1001 0 1010
+TABDECL(     OP_STRH_PRE_INDE_M_REG_OFF),  // 000 1001 0 1011
+TABDECL(     OP_SMLAW_T),      // 000 1001 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1001 0 1101
-     OP_SMULW_T,  // 000 1001 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMULW_T),  // 000 1001 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1001 0 1111
      
-     OP_TEQ_LSL_IMM,    // 000 1001 1 0000
-     OP_TEQ_LSL_REG,    // 000 1001 1 0001
-     OP_TEQ_LSR_IMM,    // 000 1001 1 0010
-     OP_TEQ_LSR_REG,    // 000 1001 1 0011
-     OP_TEQ_ASR_IMM,    // 000 1001 1 0100
-     OP_TEQ_ASR_REG,    // 000 1001 1 0101
-     OP_TEQ_ROR_IMM,    // 000 1001 1 0110
-     OP_TEQ_ROR_REG,    // 000 1001 1 0111
+TABDECL(     OP_TEQ_LSL_IMM),    // 000 1001 1 0000
+TABDECL(     OP_TEQ_LSL_REG),    // 000 1001 1 0001
+TABDECL(     OP_TEQ_LSR_IMM),    // 000 1001 1 0010
+TABDECL(     OP_TEQ_LSR_REG),    // 000 1001 1 0011
+TABDECL(     OP_TEQ_ASR_IMM),    // 000 1001 1 0100
+TABDECL(     OP_TEQ_ASR_REG),    // 000 1001 1 0101
+TABDECL(     OP_TEQ_ROR_IMM),    // 000 1001 1 0110
+TABDECL(     OP_TEQ_ROR_REG),    // 000 1001 1 0111
      
-     OP_TEQ_LSL_IMM,    // 000 1001 1 1000
-     OP_UND,            // 000 1001 1 1001
-     OP_TEQ_LSR_IMM,    // OOO 1001 1 1010
-     OP_LDRH_PRE_INDE_M_REG_OFF,  // 000 1001 1 1011
-     OP_TEQ_ASR_IMM,    // 000 1001 1 1100
-     OP_LDRSB_PRE_INDE_M_REG_OFF, // 000 1001 1 1101
-     OP_TEQ_ROR_IMM,    // 000 1001 1 1110
-     OP_LDRSH_PRE_INDE_M_REG_OFF, // 000 1001 1 1111     
+TABDECL(     OP_TEQ_LSL_IMM),    // 000 1001 1 1000
+TABDECL(     OP_UND),            // 000 1001 1 1001
+TABDECL(     OP_TEQ_LSR_IMM),    // OOO 1001 1 1010
+TABDECL(     OP_LDRH_PRE_INDE_M_REG_OFF),  // 000 1001 1 1011
+TABDECL(     OP_TEQ_ASR_IMM),    // 000 1001 1 1100
+TABDECL(     OP_LDRSB_PRE_INDE_M_REG_OFF), // 000 1001 1 1101
+TABDECL(     OP_TEQ_ROR_IMM),    // 000 1001 1 1110
+TABDECL(     OP_LDRSH_PRE_INDE_M_REG_OFF), // 000 1001 1 1111     
 //------------------------------------------
-     OP_MRS_SPSR,       // 000 1010 0 0000
-     OP_UND,            // 000 1010 0 0001
-     OP_UND,            // 000 1010 0 0010
-     OP_UND,            // 000 1010 0 0011
-     OP_UND,            // 000 1010 0 0100
-     OP_QDADD,          // 000 1010 0 0101
-     OP_UND,            // 000 1010 0 0110
-     OP_UND,            // 000 1010 0 0111
+TABDECL(     OP_MRS_SPSR),       // 000 1010 0 0000
+TABDECL(     OP_UND),            // 000 1010 0 0001
+TABDECL(     OP_UND),            // 000 1010 0 0010
+TABDECL(     OP_UND),            // 000 1010 0 0011
+TABDECL(     OP_UND),            // 000 1010 0 0100
+TABDECL(     OP_QDADD),          // 000 1010 0 0101
+TABDECL(     OP_UND),            // 000 1010 0 0110
+TABDECL(     OP_UND),            // 000 1010 0 0111
      
-     OP_SMLAL_B_B,      // 000 1010 0 1000
-     OP_SWPB,           // 000 1010 0 1001
-     OP_SMLAL_T_B,      // 000 1010 0 1010
-     OP_STRH_M_IMM_OFF, // 000 1010 0 1011
-     OP_SMLAL_B_T,      // 000 1010 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMLAL_B_B),      // 000 1010 0 1000
+TABDECL(     OP_SWPB),           // 000 1010 0 1001
+TABDECL(     OP_SMLAL_T_B),      // 000 1010 0 1010
+TABDECL(     OP_STRH_M_IMM_OFF), // 000 1010 0 1011
+TABDECL(     OP_SMLAL_B_T),      // 000 1010 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1010 0 1101
-     OP_SMLAL_T_T,      // 000 1010 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMLAL_T_T),      // 000 1010 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1010 0 1111
      
-     OP_CMP_LSL_IMM,    // 000 1010 1 0000
-     OP_CMP_LSL_REG,    // 000 1010 1 0001
-     OP_CMP_LSR_IMM,    // 000 1010 1 0010
-     OP_CMP_LSR_REG,    // 000 1010 1 0011
-     OP_CMP_ASR_IMM,    // 000 1010 1 0100
-     OP_CMP_ASR_REG,    // 000 1010 1 0101
-     OP_CMP_ROR_IMM,    // 000 1010 1 0110
-     OP_CMP_ROR_REG,    // 000 1010 1 0111
+TABDECL(     OP_CMP_LSL_IMM),    // 000 1010 1 0000
+TABDECL(     OP_CMP_LSL_REG),    // 000 1010 1 0001
+TABDECL(     OP_CMP_LSR_IMM),    // 000 1010 1 0010
+TABDECL(     OP_CMP_LSR_REG),    // 000 1010 1 0011
+TABDECL(     OP_CMP_ASR_IMM),    // 000 1010 1 0100
+TABDECL(     OP_CMP_ASR_REG),    // 000 1010 1 0101
+TABDECL(     OP_CMP_ROR_IMM),    // 000 1010 1 0110
+TABDECL(     OP_CMP_ROR_REG),    // 000 1010 1 0111
      
-     OP_CMP_LSL_IMM,    // 000 1010 1 1000
-     OP_UND,            // 000 1010 1 1001
-     OP_CMP_LSR_IMM,    // OOO 1O1O 1 1010
-     OP_LDRH_M_IMM_OFF, // 000 1010 1 1011
-     OP_CMP_ASR_IMM,    // 000 1010 1 1100
-     OP_LDRSB_M_IMM_OFF,// 000 1010 1 1101
-     OP_CMP_ROR_IMM,    // 000 1010 1 1110
-     OP_LDRSH_M_IMM_OFF,// 000 1010 1 1111
+TABDECL(     OP_CMP_LSL_IMM),    // 000 1010 1 1000
+TABDECL(     OP_UND),            // 000 1010 1 1001
+TABDECL(     OP_CMP_LSR_IMM),    // OOO 1O1O 1 1010
+TABDECL(     OP_LDRH_M_IMM_OFF), // 000 1010 1 1011
+TABDECL(     OP_CMP_ASR_IMM),    // 000 1010 1 1100
+TABDECL(     OP_LDRSB_M_IMM_OFF),// 000 1010 1 1101
+TABDECL(     OP_CMP_ROR_IMM),    // 000 1010 1 1110
+TABDECL(     OP_LDRSH_M_IMM_OFF),// 000 1010 1 1111
 //------------------------------------------
-     OP_MSR_SPSR,       // 000 1011 0 0000
-     OP_CLZ,            // 000 1011 0 0001
-     OP_UND,            // 000 1011 0 0010
-     OP_UND,            // 000 1011 0 0011
-     OP_UND,            // 000 1011 0 0100
-     OP_QDSUB,          // 000 1011 0 0101
-     OP_UND,            // 000 1011 0 0110
-     OP_UND,            // 000 1011 0 0111
+TABDECL(     OP_MSR_SPSR),       // 000 1011 0 0000
+TABDECL(     OP_CLZ),            // 000 1011 0 0001
+TABDECL(     OP_UND),            // 000 1011 0 0010
+TABDECL(     OP_UND),            // 000 1011 0 0011
+TABDECL(     OP_UND),            // 000 1011 0 0100
+TABDECL(     OP_QDSUB),          // 000 1011 0 0101
+TABDECL(     OP_UND),            // 000 1011 0 0110
+TABDECL(     OP_UND),            // 000 1011 0 0111
      
-     OP_SMUL_B_B,       // 000 1011 0 1000
-     OP_UND,            // 000 1011 0 1001
-     OP_SMUL_T_B,       // 000 1011 0 1010
-     OP_STRH_PRE_INDE_M_IMM_OFF,  // 000 1011 0 1011
-     OP_SMUL_B_T,       // 000 1011 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMUL_B_B),       // 000 1011 0 1000
+TABDECL(     OP_UND),            // 000 1011 0 1001
+TABDECL(     OP_SMUL_T_B),       // 000 1011 0 1010
+TABDECL(     OP_STRH_PRE_INDE_M_IMM_OFF),  // 000 1011 0 1011
+TABDECL(     OP_SMUL_B_T),       // 000 1011 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1011 0 1101
-     OP_SMUL_T_T,       // 000 1011 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_SMUL_T_T),       // 000 1011 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1011 0 1111
 
-     OP_CMN_LSL_IMM,    // 000 1011 1 0000
-     OP_CMN_LSL_REG,    // 000 1011 1 0001
-     OP_CMN_LSR_IMM,    // 000 1011 1 0010
-     OP_CMN_LSR_REG,    // 000 1011 1 0011
-     OP_CMN_ASR_IMM,    // 000 1011 1 0100
-     OP_CMN_ASR_REG,    // 000 1011 1 0101
-     OP_CMN_ROR_IMM,    // 000 1011 1 0110
-     OP_CMN_ROR_REG,    // 000 1011 1 0111
+TABDECL(     OP_CMN_LSL_IMM),    // 000 1011 1 0000
+TABDECL(     OP_CMN_LSL_REG),    // 000 1011 1 0001
+TABDECL(     OP_CMN_LSR_IMM),    // 000 1011 1 0010
+TABDECL(     OP_CMN_LSR_REG),    // 000 1011 1 0011
+TABDECL(     OP_CMN_ASR_IMM),    // 000 1011 1 0100
+TABDECL(     OP_CMN_ASR_REG),    // 000 1011 1 0101
+TABDECL(     OP_CMN_ROR_IMM),    // 000 1011 1 0110
+TABDECL(     OP_CMN_ROR_REG),    // 000 1011 1 0111
      
-     OP_CMN_LSL_IMM,    // 000 1011 1 1000
-     OP_UND,            // 000 1011 1 1001
-     OP_CMN_LSR_IMM,    // OOO 1O11 1 1010
-     OP_LDRH_PRE_INDE_M_IMM_OFF,  // 000 1011 1 1011
-     OP_CMN_ASR_IMM,    // 000 1011 1 1100
-     OP_LDRSB_PRE_INDE_M_IMM_OFF, // 000 1011 1 1101
-     OP_CMN_ROR_IMM,    // 000 1011 1 1110
-     OP_LDRSH_PRE_INDE_M_IMM_OFF, // 000 1011 1 1111
+TABDECL(     OP_CMN_LSL_IMM),    // 000 1011 1 1000
+TABDECL(     OP_UND),            // 000 1011 1 1001
+TABDECL(     OP_CMN_LSR_IMM),    // OOO 1O11 1 1010
+TABDECL(     OP_LDRH_PRE_INDE_M_IMM_OFF),  // 000 1011 1 1011
+TABDECL(     OP_CMN_ASR_IMM),    // 000 1011 1 1100
+TABDECL(     OP_LDRSB_PRE_INDE_M_IMM_OFF), // 000 1011 1 1101
+TABDECL(     OP_CMN_ROR_IMM),    // 000 1011 1 1110
+TABDECL(     OP_LDRSH_PRE_INDE_M_IMM_OFF), // 000 1011 1 1111
 //------------------------------------------
-     OP_ORR_LSL_IMM,    // 000 1100 0 0000
-     OP_ORR_LSL_REG,    // 000 1100 0 0001
-     OP_ORR_LSR_IMM,    // 000 1100 0 0010
-     OP_ORR_LSR_REG,    // 000 1100 0 0011
-     OP_ORR_ASR_IMM,    // 000 1100 0 0100
-     OP_ORR_ASR_REG,    // 000 1100 0 0101
-     OP_ORR_ROR_IMM,    // 000 1100 0 0110
-     OP_ORR_ROR_REG,    // 000 1100 0 0111
+TABDECL(     OP_ORR_LSL_IMM),    // 000 1100 0 0000
+TABDECL(     OP_ORR_LSL_REG),    // 000 1100 0 0001
+TABDECL(     OP_ORR_LSR_IMM),    // 000 1100 0 0010
+TABDECL(     OP_ORR_LSR_REG),    // 000 1100 0 0011
+TABDECL(     OP_ORR_ASR_IMM),    // 000 1100 0 0100
+TABDECL(     OP_ORR_ASR_REG),    // 000 1100 0 0101
+TABDECL(     OP_ORR_ROR_IMM),    // 000 1100 0 0110
+TABDECL(     OP_ORR_ROR_REG),    // 000 1100 0 0111
      
-     OP_ORR_LSL_IMM,    // 000 1100 0 1000
-     OP_UND,            // 000 1100 0 1001
-     OP_ORR_LSR_IMM,    // OOO 110O O 1010
-     OP_STRH_P_REG_OFF, // 000 1100 0 1011
-     OP_ORR_ASR_IMM,    // 000 1100 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_ORR_LSL_IMM),    // 000 1100 0 1000
+TABDECL(     OP_UND),            // 000 1100 0 1001
+TABDECL(     OP_ORR_LSR_IMM),    // OOO 110O O 1010
+TABDECL(     OP_STRH_P_REG_OFF), // 000 1100 0 1011
+TABDECL(     OP_ORR_ASR_IMM),    // 000 1100 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1100 0 1101
-     OP_ORR_ROR_IMM,    // 000 1100 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_ORR_ROR_IMM),    // 000 1100 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1100 0 1111
      
-     OP_ORR_S_LSL_IMM,  // 000 1100 1 0000
-     OP_ORR_S_LSL_REG,  // 000 1100 1 0001
-     OP_ORR_S_LSR_IMM,  // 000 1100 1 0010
-     OP_ORR_S_LSR_REG,  // 000 1100 1 0011
-     OP_ORR_S_ASR_IMM,  // 000 1100 1 0100
-     OP_ORR_S_ASR_REG,  // 000 1100 1 0101
-     OP_ORR_S_ROR_IMM,  // 000 1100 1 0110
-     OP_ORR_S_ROR_REG,  // 000 1100 1 0111
+TABDECL(     OP_ORR_S_LSL_IMM),  // 000 1100 1 0000
+TABDECL(     OP_ORR_S_LSL_REG),  // 000 1100 1 0001
+TABDECL(     OP_ORR_S_LSR_IMM),  // 000 1100 1 0010
+TABDECL(     OP_ORR_S_LSR_REG),  // 000 1100 1 0011
+TABDECL(     OP_ORR_S_ASR_IMM),  // 000 1100 1 0100
+TABDECL(     OP_ORR_S_ASR_REG),  // 000 1100 1 0101
+TABDECL(     OP_ORR_S_ROR_IMM),  // 000 1100 1 0110
+TABDECL(     OP_ORR_S_ROR_REG),  // 000 1100 1 0111
      
-     OP_ORR_S_LSL_IMM,  // 000 1100 1 1000
-     OP_UND,            // 000 1100 1 1001
-     OP_ORR_S_LSR_IMM,  // 000 1100 1 1010
-     OP_LDRH_P_REG_OFF, // 000 1100 1 1011
-     OP_ORR_S_ASR_IMM,  // 000 1100 1 1100
-     OP_LDRSB_P_REG_OFF,// 000 1100 1 1101
-     OP_ORR_S_ROR_IMM,  // 000 1100 1 1110
-     OP_LDRSH_P_REG_OFF,// 000 1100 1 1111
+TABDECL(     OP_ORR_S_LSL_IMM),  // 000 1100 1 1000
+TABDECL(     OP_UND),            // 000 1100 1 1001
+TABDECL(     OP_ORR_S_LSR_IMM),  // 000 1100 1 1010
+TABDECL(     OP_LDRH_P_REG_OFF), // 000 1100 1 1011
+TABDECL(     OP_ORR_S_ASR_IMM),  // 000 1100 1 1100
+TABDECL(     OP_LDRSB_P_REG_OFF),// 000 1100 1 1101
+TABDECL(     OP_ORR_S_ROR_IMM),  // 000 1100 1 1110
+TABDECL(     OP_LDRSH_P_REG_OFF),// 000 1100 1 1111
 //------------------------------------------
-     OP_MOV_LSL_IMM,    // 000 1101 0 0000
-     OP_MOV_LSL_REG,    // 000 1101 0 0001
-     OP_MOV_LSR_IMM,    // 000 1101 0 0010
-     OP_MOV_LSR_REG,    // 000 1101 0 0011
-     OP_MOV_ASR_IMM,    // 000 1101 0 0100
-     OP_MOV_ASR_REG,    // 000 1101 0 0101
-     OP_MOV_ROR_IMM,    // 000 1101 0 0110
-     OP_MOV_ROR_REG,    // 000 1101 0 0111
+TABDECL(     OP_MOV_LSL_IMM),    // 000 1101 0 0000
+TABDECL(     OP_MOV_LSL_REG),    // 000 1101 0 0001
+TABDECL(     OP_MOV_LSR_IMM),    // 000 1101 0 0010
+TABDECL(     OP_MOV_LSR_REG),    // 000 1101 0 0011
+TABDECL(     OP_MOV_ASR_IMM),    // 000 1101 0 0100
+TABDECL(     OP_MOV_ASR_REG),    // 000 1101 0 0101
+TABDECL(     OP_MOV_ROR_IMM),    // 000 1101 0 0110
+TABDECL(     OP_MOV_ROR_REG),    // 000 1101 0 0111
      
-     OP_MOV_LSL_IMM,    // 000 1101 0 1000
-     OP_UND,            // 000 1101 0 1001
-     OP_MOV_LSR_IMM,    // OOO 1101 O 1010
-     OP_STRH_PRE_INDE_P_REG_OFF, // 000 1101 0 1011
-     OP_MOV_ASR_IMM,    // 000 1101 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_MOV_LSL_IMM),    // 000 1101 0 1000
+TABDECL(     OP_UND),            // 000 1101 0 1001
+TABDECL(     OP_MOV_LSR_IMM),    // OOO 1101 O 1010
+TABDECL(     OP_STRH_PRE_INDE_P_REG_OFF), // 000 1101 0 1011
+TABDECL(     OP_MOV_ASR_IMM),    // 000 1101 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1101 0 1101
-     OP_MOV_ROR_IMM,    // 000 1101 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_MOV_ROR_IMM),    // 000 1101 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1101 0 1111
      
-     OP_MOV_S_LSL_IMM,  // 000 1101 1 0000
-     OP_MOV_S_LSL_REG,  // 000 1101 1 0001
-     OP_MOV_S_LSR_IMM,  // 000 1101 1 0010
-     OP_MOV_S_LSR_REG,  // 000 1101 1 0011
-     OP_MOV_S_ASR_IMM,  // 000 1101 1 0100
-     OP_MOV_S_ASR_REG,  // 000 1101 1 0101
-     OP_MOV_S_ROR_IMM,  // 000 1101 1 0110
-     OP_MOV_S_ROR_REG,  // 000 1101 1 0111
+TABDECL(     OP_MOV_S_LSL_IMM),  // 000 1101 1 0000
+TABDECL(     OP_MOV_S_LSL_REG),  // 000 1101 1 0001
+TABDECL(     OP_MOV_S_LSR_IMM),  // 000 1101 1 0010
+TABDECL(     OP_MOV_S_LSR_REG),  // 000 1101 1 0011
+TABDECL(     OP_MOV_S_ASR_IMM),  // 000 1101 1 0100
+TABDECL(     OP_MOV_S_ASR_REG),  // 000 1101 1 0101
+TABDECL(     OP_MOV_S_ROR_IMM),  // 000 1101 1 0110
+TABDECL(     OP_MOV_S_ROR_REG),  // 000 1101 1 0111
      
-     OP_MOV_S_LSL_IMM,  // 000 1101 1 1000
-     OP_UND,            // 000 1101 1 1001
-     OP_MOV_S_LSR_IMM,  // 000 1101 1 1010
-     OP_LDRH_PRE_INDE_P_REG_OFF, // 000 1101 1 1011
-     OP_MOV_S_ASR_IMM,  // 000 1101 1 1100
-     OP_LDRSB_PRE_INDE_P_REG_OFF,// 000 1101 1 1101
-     OP_MOV_S_ROR_IMM,  // 000 1101 1 1110
-     OP_LDRSH_PRE_INDE_P_REG_OFF,// 000 1101 1 1111
+TABDECL(     OP_MOV_S_LSL_IMM),  // 000 1101 1 1000
+TABDECL(     OP_UND),            // 000 1101 1 1001
+TABDECL(     OP_MOV_S_LSR_IMM),  // 000 1101 1 1010
+TABDECL(     OP_LDRH_PRE_INDE_P_REG_OFF), // 000 1101 1 1011
+TABDECL(     OP_MOV_S_ASR_IMM),  // 000 1101 1 1100
+TABDECL(     OP_LDRSB_PRE_INDE_P_REG_OFF),// 000 1101 1 1101
+TABDECL(     OP_MOV_S_ROR_IMM),  // 000 1101 1 1110
+TABDECL(     OP_LDRSH_PRE_INDE_P_REG_OFF),// 000 1101 1 1111
 //------------------------------------------
-     OP_BIC_LSL_IMM,    // 000 1110 0 0000
-     OP_BIC_LSL_REG,    // 000 1110 0 0001
-     OP_BIC_LSR_IMM,    // 000 1110 0 0010
-     OP_BIC_LSR_REG,    // 000 1110 0 0011
-     OP_BIC_ASR_IMM,    // 000 1110 0 0100
-     OP_BIC_ASR_REG,    // 000 1110 0 0101
-     OP_BIC_ROR_IMM,    // 000 1110 0 0110
-     OP_BIC_ROR_REG,    // 000 1110 0 0111
+TABDECL(     OP_BIC_LSL_IMM),    // 000 1110 0 0000
+TABDECL(     OP_BIC_LSL_REG),    // 000 1110 0 0001
+TABDECL(     OP_BIC_LSR_IMM),    // 000 1110 0 0010
+TABDECL(     OP_BIC_LSR_REG),    // 000 1110 0 0011
+TABDECL(     OP_BIC_ASR_IMM),    // 000 1110 0 0100
+TABDECL(     OP_BIC_ASR_REG),    // 000 1110 0 0101
+TABDECL(     OP_BIC_ROR_IMM),    // 000 1110 0 0110
+TABDECL(     OP_BIC_ROR_REG),    // 000 1110 0 0111
      
-     OP_BIC_LSL_IMM,    // 000 1110 0 1000
-     OP_UND,            // 000 1110 0 1001
-     OP_BIC_LSR_IMM,    // OOO 111O O 1010
-     OP_STRH_P_IMM_OFF, // 000 1110 0 1011
-     OP_BIC_ASR_IMM,    // 000 1110 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_BIC_LSL_IMM),    // 000 1110 0 1000
+TABDECL(     OP_UND),            // 000 1110 0 1001
+TABDECL(     OP_BIC_LSR_IMM),    // OOO 111O O 1010
+TABDECL(     OP_STRH_P_IMM_OFF), // 000 1110 0 1011
+TABDECL(     OP_BIC_ASR_IMM),    // 000 1110 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1110 0 1101
-     OP_BIC_ROR_IMM,    // 000 1110 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_BIC_ROR_IMM),    // 000 1110 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1110 0 1111
      
-     OP_BIC_S_LSL_IMM,  // 000 1110 1 0000
-     OP_BIC_S_LSL_REG,  // 000 1110 1 0001
-     OP_BIC_S_LSR_IMM,  // 000 1110 1 0010
-     OP_BIC_S_LSR_REG,  // 000 1110 1 0011
-     OP_BIC_S_ASR_IMM,  // 000 1110 1 0100
-     OP_BIC_S_ASR_REG,  // 000 1110 1 0101
-     OP_BIC_S_ROR_IMM,  // 000 1110 1 0110
-     OP_BIC_S_ROR_REG,  // 000 1110 1 0111
+TABDECL(     OP_BIC_S_LSL_IMM),  // 000 1110 1 0000
+TABDECL(     OP_BIC_S_LSL_REG),  // 000 1110 1 0001
+TABDECL(     OP_BIC_S_LSR_IMM),  // 000 1110 1 0010
+TABDECL(     OP_BIC_S_LSR_REG),  // 000 1110 1 0011
+TABDECL(     OP_BIC_S_ASR_IMM),  // 000 1110 1 0100
+TABDECL(     OP_BIC_S_ASR_REG),  // 000 1110 1 0101
+TABDECL(     OP_BIC_S_ROR_IMM),  // 000 1110 1 0110
+TABDECL(     OP_BIC_S_ROR_REG),  // 000 1110 1 0111
      
-     OP_BIC_S_LSL_IMM,  // 000 1110 1 1000
-     OP_UND,            // 000 1110 1 1001
-     OP_BIC_S_LSR_IMM,  // 000 1110 1 1010
-     OP_LDRH_P_IMM_OFF, // 000 1110 1 1011
-     OP_BIC_S_ASR_IMM,  // 000 1110 1 1100
-     OP_LDRSB_P_IMM_OFF,// 000 1110 1 1101
-     OP_BIC_S_ROR_IMM,  // 000 1110 1 1110
-     OP_LDRSH_P_IMM_OFF,// 000 1110 1 1111
+TABDECL(     OP_BIC_S_LSL_IMM),  // 000 1110 1 1000
+TABDECL(     OP_UND),            // 000 1110 1 1001
+TABDECL(     OP_BIC_S_LSR_IMM),  // 000 1110 1 1010
+TABDECL(     OP_LDRH_P_IMM_OFF), // 000 1110 1 1011
+TABDECL(     OP_BIC_S_ASR_IMM),  // 000 1110 1 1100
+TABDECL(     OP_LDRSB_P_IMM_OFF),// 000 1110 1 1101
+TABDECL(     OP_BIC_S_ROR_IMM),  // 000 1110 1 1110
+TABDECL(     OP_LDRSH_P_IMM_OFF),// 000 1110 1 1111
 //-------------------------------------------
-     OP_MVN_LSL_IMM,    // 000 1111 0 0000
-     OP_MVN_LSL_REG,    // 000 1111 0 0001
-     OP_MVN_LSR_IMM,    // 000 1111 0 0010
-     OP_MVN_LSR_REG,    // 000 1111 0 0011
-     OP_MVN_ASR_IMM,    // 000 1111 0 0100
-     OP_MVN_ASR_REG,    // 000 1111 0 0101
-     OP_MVN_ROR_IMM,    // 000 1111 0 0110
-     OP_MVN_ROR_REG,    // 000 1111 0 0111
+TABDECL(     OP_MVN_LSL_IMM),    // 000 1111 0 0000
+TABDECL(     OP_MVN_LSL_REG),    // 000 1111 0 0001
+TABDECL(     OP_MVN_LSR_IMM),    // 000 1111 0 0010
+TABDECL(     OP_MVN_LSR_REG),    // 000 1111 0 0011
+TABDECL(     OP_MVN_ASR_IMM),    // 000 1111 0 0100
+TABDECL(     OP_MVN_ASR_REG),    // 000 1111 0 0101
+TABDECL(     OP_MVN_ROR_IMM),    // 000 1111 0 0110
+TABDECL(     OP_MVN_ROR_REG),    // 000 1111 0 0111
      
-     OP_MVN_LSL_IMM,    // 000 1111 0 1000
-     OP_UND,            // 000 1111 0 1001
-     OP_MVN_LSR_IMM,    // OOO 1111 O 1010
-     OP_STRH_PRE_INDE_P_IMM_OFF, // 000 1111 0 1011
-     OP_MVN_ASR_IMM,    // 000 1111 0 1100
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_MVN_LSL_IMM),    // 000 1111 0 1000
+TABDECL(     OP_UND),            // 000 1111 0 1001
+TABDECL(     OP_MVN_LSR_IMM),    // OOO 1111 O 1010
+TABDECL(     OP_STRH_PRE_INDE_P_IMM_OFF), // 000 1111 0 1011
+TABDECL(     OP_MVN_ASR_IMM),    // 000 1111 0 1100
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1111 0 1101
-     OP_MVN_ROR_IMM,    // 000 1111 0 1110
-     OP_LDRD_STRD_OFFSET_PRE_INDEX,
+TABDECL(     OP_MVN_ROR_IMM),    // 000 1111 0 1110
+TABDECL(     OP_LDRD_STRD_OFFSET_PRE_INDEX),
                         // 000 1111 0 1111
      
-     OP_MVN_S_LSL_IMM,  // 000 1111 1 0000
-     OP_MVN_S_LSL_REG,  // 000 1111 1 0001
-     OP_MVN_S_LSR_IMM,  // 000 1111 1 0010
-     OP_MVN_S_LSR_REG,  // 000 1111 1 0011
-     OP_MVN_S_ASR_IMM,  // 000 1111 1 0100
-     OP_MVN_S_ASR_REG,  // 000 1111 1 0101
-     OP_MVN_S_ROR_IMM,  // 000 1111 1 0110
-     OP_MVN_S_ROR_REG,  // 000 1111 1 0111
+TABDECL(     OP_MVN_S_LSL_IMM),  // 000 1111 1 0000
+TABDECL(     OP_MVN_S_LSL_REG),  // 000 1111 1 0001
+TABDECL(     OP_MVN_S_LSR_IMM),  // 000 1111 1 0010
+TABDECL(     OP_MVN_S_LSR_REG),  // 000 1111 1 0011
+TABDECL(     OP_MVN_S_ASR_IMM),  // 000 1111 1 0100
+TABDECL(     OP_MVN_S_ASR_REG),  // 000 1111 1 0101
+TABDECL(     OP_MVN_S_ROR_IMM),  // 000 1111 1 0110
+TABDECL(     OP_MVN_S_ROR_REG),  // 000 1111 1 0111
      
-     OP_MVN_S_LSL_IMM,  // 000 1111 1 1000
-     OP_UND,            // 000 1111 1 1001
-     OP_MVN_S_LSR_IMM,  // 000 1111 1 1010
-     OP_LDRH_PRE_INDE_P_IMM_OFF, // 000 1111 1 1011
-     OP_MVN_S_ASR_IMM,  // 000 1111 1 1100
-     OP_LDRSB_PRE_INDE_P_IMM_OFF,// 000 1111 1 1101
-     OP_MVN_S_ROR_IMM,  // 000 1111 1 1110
-     OP_LDRSH_PRE_INDE_P_IMM_OFF,// 000 1111 1 1111
+TABDECL(     OP_MVN_S_LSL_IMM),  // 000 1111 1 1000
+TABDECL(     OP_UND),            // 000 1111 1 1001
+TABDECL(     OP_MVN_S_LSR_IMM),  // 000 1111 1 1010
+TABDECL(     OP_LDRH_PRE_INDE_P_IMM_OFF), // 000 1111 1 1011
+TABDECL(     OP_MVN_S_ASR_IMM),  // 000 1111 1 1100
+TABDECL(     OP_LDRSB_PRE_INDE_P_IMM_OFF),// 000 1111 1 1101
+TABDECL(     OP_MVN_S_ROR_IMM),  // 000 1111 1 1110
+TABDECL(     OP_LDRSH_PRE_INDE_P_IMM_OFF),// 000 1111 1 1111
 //-------------------------------------------
-     OP_AND_IMM_VAL,    // 001 0000 0 0000
-     OP_AND_IMM_VAL,    // 001 0000 0 0001
-     OP_AND_IMM_VAL,    // 001 0000 0 0010
-     OP_AND_IMM_VAL,    // 001 0000 0 0011
-     OP_AND_IMM_VAL,    // 001 0000 0 0100
-     OP_AND_IMM_VAL,    // 001 0000 0 0101
-     OP_AND_IMM_VAL,    // 001 0000 0 0110
-     OP_AND_IMM_VAL,    // 001 0000 0 0111
-     OP_AND_IMM_VAL,    // 001 0000 0 1000
-     OP_AND_IMM_VAL,    // 001 0000 0 1001
-     OP_AND_IMM_VAL,    // 001 0000 0 1010
-     OP_AND_IMM_VAL,    // 001 0000 0 1011
-     OP_AND_IMM_VAL,    // 001 0000 0 1100
-     OP_AND_IMM_VAL,    // 001 0000 0 1101
-     OP_AND_IMM_VAL,    // 001 0000 0 1110
-     OP_AND_IMM_VAL,    // 001 0000 0 1111
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0000
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0001
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0010
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0011
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0100
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0101
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0110
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 0111
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1000
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1001
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1010
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1011
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1100
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1101
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1110
+TABDECL(     OP_AND_IMM_VAL),    // 001 0000 0 1111
      
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0000
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0001
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0010
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0011
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0100
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0101
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0110
-     OP_AND_S_IMM_VAL,  // 001 0000 1 0111
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1000
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1001
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1010
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1011
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1100
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1101
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1110
-     OP_AND_S_IMM_VAL,  // 001 0000 1 1111
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0000
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0001
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0010
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0011
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0100
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0101
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0110
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 0111
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1000
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1001
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1010
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1011
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1100
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1101
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1110
+TABDECL(     OP_AND_S_IMM_VAL),  // 001 0000 1 1111
 //------------------------------------------
-     OP_EOR_IMM_VAL,    // 001 0001 0 0000
-     OP_EOR_IMM_VAL,    // 001 0001 0 0001
-     OP_EOR_IMM_VAL,    // 001 0001 0 0010
-     OP_EOR_IMM_VAL,    // 001 0001 0 0011
-     OP_EOR_IMM_VAL,    // 001 0001 0 0100
-     OP_EOR_IMM_VAL,    // 001 0001 0 0101
-     OP_EOR_IMM_VAL,    // 001 0001 0 0110
-     OP_EOR_IMM_VAL,    // 001 0001 0 0111
-     OP_EOR_IMM_VAL,    // 001 0001 0 1000
-     OP_EOR_IMM_VAL,    // 001 0001 0 1001
-     OP_EOR_IMM_VAL,    // 001 0001 0 1010
-     OP_EOR_IMM_VAL,    // 001 0001 0 1011
-     OP_EOR_IMM_VAL,    // 001 0001 0 1100
-     OP_EOR_IMM_VAL,    // 001 0001 0 1101
-     OP_EOR_IMM_VAL,    // 001 0001 0 1110
-     OP_EOR_IMM_VAL,    // 001 0001 0 1111
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0000
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0001
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0010
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0011
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0100
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0101
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0110
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 0111
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1000
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1001
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1010
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1011
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1100
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1101
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1110
+TABDECL(     OP_EOR_IMM_VAL),    // 001 0001 0 1111
      
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0000
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0001
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0010
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0011
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0100
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0101
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0110
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 0111
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1000
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1001
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1010
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1011
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1100
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1101
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1110
-     OP_EOR_S_IMM_VAL,  // 001 0001 1 1111
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0000
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0001
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0010
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0011
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0100
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0101
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0110
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 0111
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1000
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1001
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1010
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1011
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1100
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1101
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1110
+TABDECL(     OP_EOR_S_IMM_VAL),  // 001 0001 1 1111
 //------------------------------------------
-     OP_SUB_IMM_VAL,    // 001 0010 0 0000
-     OP_SUB_IMM_VAL,    // 001 0010 0 0001
-     OP_SUB_IMM_VAL,    // 001 0010 0 0010
-     OP_SUB_IMM_VAL,    // 001 0010 0 0011
-     OP_SUB_IMM_VAL,    // 001 0010 0 0100
-     OP_SUB_IMM_VAL,    // 001 0010 0 0101
-     OP_SUB_IMM_VAL,    // 001 0010 0 0110
-     OP_SUB_IMM_VAL,    // 001 0010 0 0111
-     OP_SUB_IMM_VAL,    // 001 0010 0 1000
-     OP_SUB_IMM_VAL,    // 001 0010 0 1001
-     OP_SUB_IMM_VAL,    // 001 0010 0 1010
-     OP_SUB_IMM_VAL,    // 001 0010 0 1011
-     OP_SUB_IMM_VAL,    // 001 0010 0 1100
-     OP_SUB_IMM_VAL,    // 001 0010 0 1101
-     OP_SUB_IMM_VAL,    // 001 0010 0 1110
-     OP_SUB_IMM_VAL,    // 001 0010 0 1111
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0000
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0001
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0010
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0011
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0100
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0101
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0110
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 0111
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1000
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1001
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1010
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1011
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1100
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1101
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1110
+TABDECL(     OP_SUB_IMM_VAL),    // 001 0010 0 1111
      
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0000
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0001
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0010
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0011
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0100
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0101
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0110
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 0111
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1000
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1001
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1010
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1011
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1100
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1101
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1110
-     OP_SUB_S_IMM_VAL,  // 001 0010 1 1111
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0000
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0001
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0010
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0011
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0100
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0101
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0110
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 0111
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1000
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1001
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1010
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1011
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1100
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1101
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1110
+TABDECL(     OP_SUB_S_IMM_VAL),  // 001 0010 1 1111
 //------------------------------------------
-     OP_RSB_IMM_VAL,    // 001 0011 0 0000
-     OP_RSB_IMM_VAL,    // 001 0011 0 0001
-     OP_RSB_IMM_VAL,    // 001 0011 0 0010
-     OP_RSB_IMM_VAL,    // 001 0011 0 0011
-     OP_RSB_IMM_VAL,    // 001 0011 0 0100
-     OP_RSB_IMM_VAL,    // 001 0011 0 0101
-     OP_RSB_IMM_VAL,    // 001 0011 0 0110
-     OP_RSB_IMM_VAL,    // 001 0011 0 0111
-     OP_RSB_IMM_VAL,    // 001 0011 0 1000
-     OP_RSB_IMM_VAL,    // 001 0011 0 1001
-     OP_RSB_IMM_VAL,    // 001 0011 0 1010
-     OP_RSB_IMM_VAL,    // 001 0011 0 1011
-     OP_RSB_IMM_VAL,    // 001 0011 0 1100
-     OP_RSB_IMM_VAL,    // 001 0011 0 1101
-     OP_RSB_IMM_VAL,    // 001 0011 0 1110
-     OP_RSB_IMM_VAL,    // 001 0011 0 1111
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0000
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0001
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0010
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0011
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0100
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0101
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0110
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 0111
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1000
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1001
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1010
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1011
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1100
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1101
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1110
+TABDECL(     OP_RSB_IMM_VAL),    // 001 0011 0 1111
      
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0000
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0001
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0010
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0011
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0100
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0101
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0110
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 0111
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1000
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1001
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1010
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1011
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1100
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1101
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1110
-     OP_RSB_S_IMM_VAL,  // 001 0011 1 1111
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0000
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0001
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0010
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0011
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0100
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0101
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0110
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 0111
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1000
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1001
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1010
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1011
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1100
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1101
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1110
+TABDECL(     OP_RSB_S_IMM_VAL),  // 001 0011 1 1111
 //------------------------------------------
-     OP_ADD_IMM_VAL,    // 001 0100 0 0000
-     OP_ADD_IMM_VAL,    // 001 0100 0 0001
-     OP_ADD_IMM_VAL,    // 001 0100 0 0010
-     OP_ADD_IMM_VAL,    // 001 0100 0 0011
-     OP_ADD_IMM_VAL,    // 001 0100 0 0100
-     OP_ADD_IMM_VAL,    // 001 0100 0 0101
-     OP_ADD_IMM_VAL,    // 001 0100 0 0110
-     OP_ADD_IMM_VAL,    // 001 0100 0 0111
-     OP_ADD_IMM_VAL,    // 001 0100 0 1000
-     OP_ADD_IMM_VAL,    // 001 0100 0 1001
-     OP_ADD_IMM_VAL,    // 001 0100 0 1010
-     OP_ADD_IMM_VAL,    // 001 0100 0 1011
-     OP_ADD_IMM_VAL,    // 001 0100 0 1100
-     OP_ADD_IMM_VAL,    // 001 0100 0 1101
-     OP_ADD_IMM_VAL,    // 001 0100 0 1110
-     OP_ADD_IMM_VAL,    // 001 0100 0 1111
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0000
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0001
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0010
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0011
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0100
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0101
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0110
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 0111
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1000
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1001
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1010
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1011
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1100
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1101
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1110
+TABDECL(     OP_ADD_IMM_VAL),    // 001 0100 0 1111
      
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0000
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0001
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0010
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0011
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0100
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0101
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0110
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 0111
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1000
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1001
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1010
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1011
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1100
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1101
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1110
-     OP_ADD_S_IMM_VAL,  // 001 0100 1 1111
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0000
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0001
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0010
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0011
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0100
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0101
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0110
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 0111
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1000
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1001
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1010
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1011
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1100
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1101
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1110
+TABDECL(     OP_ADD_S_IMM_VAL),  // 001 0100 1 1111
 //------------------------------------------
-     OP_ADC_IMM_VAL,    // 001 0101 0 0000
-     OP_ADC_IMM_VAL,    // 001 0101 0 0001
-     OP_ADC_IMM_VAL,    // 001 0101 0 0010
-     OP_ADC_IMM_VAL,    // 001 0101 0 0011
-     OP_ADC_IMM_VAL,    // 001 0101 0 0100
-     OP_ADC_IMM_VAL,    // 001 0101 0 0101
-     OP_ADC_IMM_VAL,    // 001 0101 0 0110
-     OP_ADC_IMM_VAL,    // 001 0101 0 0111
-     OP_ADC_IMM_VAL,    // 001 0101 0 1000
-     OP_ADC_IMM_VAL,    // 001 0101 0 1001
-     OP_ADC_IMM_VAL,    // 001 0101 0 1010
-     OP_ADC_IMM_VAL,    // 001 0101 0 1011
-     OP_ADC_IMM_VAL,    // 001 0101 0 1100
-     OP_ADC_IMM_VAL,    // 001 0101 0 1101
-     OP_ADC_IMM_VAL,    // 001 0101 0 1110
-     OP_ADC_IMM_VAL,    // 001 0101 0 1111
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0000
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0001
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0010
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0011
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0100
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0101
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0110
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 0111
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1000
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1001
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1010
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1011
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1100
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1101
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1110
+TABDECL(     OP_ADC_IMM_VAL),    // 001 0101 0 1111
      
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0000
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0001
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0010
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0011
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0100
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0101
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0110
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 0111
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1000
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1001
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1010
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1011
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1100
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1101
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1110
-     OP_ADC_S_IMM_VAL,  // 001 0101 1 1111
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0000
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0001
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0010
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0011
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0100
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0101
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0110
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 0111
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1000
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1001
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1010
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1011
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1100
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1101
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1110
+TABDECL(     OP_ADC_S_IMM_VAL),  // 001 0101 1 1111
 //------------------------------------------
-     OP_SBC_IMM_VAL,    // 001 0110 0 0000
-     OP_SBC_IMM_VAL,    // 001 0110 0 0001
-     OP_SBC_IMM_VAL,    // 001 0110 0 0010
-     OP_SBC_IMM_VAL,    // 001 0110 0 0011
-     OP_SBC_IMM_VAL,    // 001 0110 0 0100
-     OP_SBC_IMM_VAL,    // 001 0110 0 0101
-     OP_SBC_IMM_VAL,    // 001 0110 0 0110
-     OP_SBC_IMM_VAL,    // 001 0110 0 0111
-     OP_SBC_IMM_VAL,    // 001 0110 0 1000
-     OP_SBC_IMM_VAL,    // 001 0110 0 1001
-     OP_SBC_IMM_VAL,    // 001 0110 0 1010
-     OP_SBC_IMM_VAL,    // 001 0110 0 1011
-     OP_SBC_IMM_VAL,    // 001 0110 0 1100
-     OP_SBC_IMM_VAL,    // 001 0110 0 1101
-     OP_SBC_IMM_VAL,    // 001 0110 0 1110
-     OP_SBC_IMM_VAL,    // 001 0110 0 1111
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0000
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0001
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0010
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0011
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0100
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0101
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0110
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 0111
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1000
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1001
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1010
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1011
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1100
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1101
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1110
+TABDECL(     OP_SBC_IMM_VAL),    // 001 0110 0 1111
      
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0000
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0001
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0010
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0011
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0100
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0101
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0110
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 0111
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1000
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1001
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1010
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1011
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1100
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1101
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1110
-     OP_SBC_S_IMM_VAL,  // 001 0110 1 1111
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0000
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0001
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0010
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0011
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0100
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0101
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0110
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 0111
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1000
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1001
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1010
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1011
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1100
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1101
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1110
+TABDECL(     OP_SBC_S_IMM_VAL),  // 001 0110 1 1111
 //------------------------------------------
-     OP_RSC_IMM_VAL,    // 001 0111 0 0000
-     OP_RSC_IMM_VAL,    // 001 0111 0 0001
-     OP_RSC_IMM_VAL,    // 001 0111 0 0010
-     OP_RSC_IMM_VAL,    // 001 0111 0 0011
-     OP_RSC_IMM_VAL,    // 001 0111 0 0100
-     OP_RSC_IMM_VAL,    // 001 0111 0 0101
-     OP_RSC_IMM_VAL,    // 001 0111 0 0110
-     OP_RSC_IMM_VAL,    // 001 0111 0 0111
-     OP_RSC_IMM_VAL,    // 001 0111 0 1000
-     OP_RSC_IMM_VAL,    // 001 0111 0 1001
-     OP_RSC_IMM_VAL,    // 001 0111 0 1010
-     OP_RSC_IMM_VAL,    // 001 0111 0 1011
-     OP_RSC_IMM_VAL,    // 001 0111 0 1100
-     OP_RSC_IMM_VAL,    // 001 0111 0 1101
-     OP_RSC_IMM_VAL,    // 001 0111 0 1110
-     OP_RSC_IMM_VAL,    // 001 0111 0 1111
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0000
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0001
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0010
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0011
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0100
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0101
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0110
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 0111
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1000
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1001
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1010
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1011
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1100
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1101
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1110
+TABDECL(     OP_RSC_IMM_VAL),    // 001 0111 0 1111
      
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0000
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0001
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0010
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0011
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0100
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0101
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0110
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 0111
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1000
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1001
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1010
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1011
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1100
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1101
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1110
-     OP_RSC_S_IMM_VAL,  // 001 0111 1 1111
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0000
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0001
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0010
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0011
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0100
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0101
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0110
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 0111
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1000
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1001
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1010
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1011
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1100
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1101
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1110
+TABDECL(     OP_RSC_S_IMM_VAL),  // 001 0111 1 1111
 //------------------------------------------
-     OP_UND,    // 001 1000 0 0000
-     OP_UND,    // 001 1000 0 0001
-     OP_UND,    // 001 1000 0 0010
-     OP_UND,    // 001 1000 0 0011
-     OP_UND,    // 001 1000 0 0100
-     OP_UND,    // 001 1000 0 0101
-     OP_UND,    // 001 1000 0 0110
-     OP_UND,    // 001 1000 0 0111
-     OP_UND,    // 001 1000 0 1000
-     OP_UND,    // 001 1000 0 1001
-     OP_UND,    // 001 1000 0 1010
-     OP_UND,    // 001 1000 0 1011
-     OP_UND,    // 001 1000 0 1100
-     OP_UND,    // 001 1000 0 1101
-     OP_UND,    // 001 1000 0 1110
-     OP_UND,    // 001 1000 0 1111
+TABDECL(     OP_UND),    // 001 1000 0 0000
+TABDECL(     OP_UND),    // 001 1000 0 0001
+TABDECL(     OP_UND),    // 001 1000 0 0010
+TABDECL(     OP_UND),    // 001 1000 0 0011
+TABDECL(     OP_UND),    // 001 1000 0 0100
+TABDECL(     OP_UND),    // 001 1000 0 0101
+TABDECL(     OP_UND),    // 001 1000 0 0110
+TABDECL(     OP_UND),    // 001 1000 0 0111
+TABDECL(     OP_UND),    // 001 1000 0 1000
+TABDECL(     OP_UND),    // 001 1000 0 1001
+TABDECL(     OP_UND),    // 001 1000 0 1010
+TABDECL(     OP_UND),    // 001 1000 0 1011
+TABDECL(     OP_UND),    // 001 1000 0 1100
+TABDECL(     OP_UND),    // 001 1000 0 1101
+TABDECL(     OP_UND),    // 001 1000 0 1110
+TABDECL(     OP_UND),    // 001 1000 0 1111
      
-     OP_TST_IMM_VAL,  // 001 1000 1 0000
-     OP_TST_IMM_VAL,  // 001 1000 1 0001
-     OP_TST_IMM_VAL,  // 001 1000 1 0010
-     OP_TST_IMM_VAL,  // 001 1000 1 0011
-     OP_TST_IMM_VAL,  // 001 1000 1 0100
-     OP_TST_IMM_VAL,  // 001 1000 1 0101
-     OP_TST_IMM_VAL,  // 001 1000 1 0110
-     OP_TST_IMM_VAL,  // 001 1000 1 0111
-     OP_TST_IMM_VAL,  // 001 1000 1 1000
-     OP_TST_IMM_VAL,  // 001 1000 1 1001
-     OP_TST_IMM_VAL,  // 001 1000 1 1010
-     OP_TST_IMM_VAL,  // 001 1000 1 1011
-     OP_TST_IMM_VAL,  // 001 1000 1 1100
-     OP_TST_IMM_VAL,  // 001 1000 1 1101
-     OP_TST_IMM_VAL,  // 001 1000 1 1110
-     OP_TST_IMM_VAL,  // 001 1000 1 1111
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0000
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0001
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0010
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0011
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0100
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0101
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0110
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 0111
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1000
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1001
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1010
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1011
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1100
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1101
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1110
+TABDECL(     OP_TST_IMM_VAL),  // 001 1000 1 1111
 //------------------------------------------
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0000
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0001
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0010
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0011
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0100
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0101
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0110
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 0111
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1000
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1001
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1010
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1011
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1100
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1101
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1110
-     OP_MSR_CPSR_IMM_VAL,    // 001 1001 0 1111
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0000
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0001
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0010
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0011
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0100
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0101
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0110
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 0111
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1000
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1001
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1010
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1011
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1100
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1101
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1110
+TABDECL(     OP_MSR_CPSR_IMM_VAL),    // 001 1001 0 1111
      
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0000
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0001
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0010
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0011
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0100
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0101
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0110
-     OP_TEQ_IMM_VAL,  // 001 1001 1 0111
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1000
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1001
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1010
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1011
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1100
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1101
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1110
-     OP_TEQ_IMM_VAL,  // 001 1001 1 1111
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0000
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0001
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0010
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0011
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0100
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0101
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0110
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 0111
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1000
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1001
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1010
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1011
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1100
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1101
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1110
+TABDECL(     OP_TEQ_IMM_VAL),  // 001 1001 1 1111
 //------------------------------------------
-     OP_UND,    // 001 1010 0 0000
-     OP_UND,    // 001 1010 0 0001
-     OP_UND,    // 001 1010 0 0010
-     OP_UND,    // 001 1010 0 0011
-     OP_UND,    // 001 1010 0 0100
-     OP_UND,    // 001 1010 0 0101
-     OP_UND,    // 001 1010 0 0110
-     OP_UND,    // 001 1010 0 0111
-     OP_UND,    // 001 1010 0 1000
-     OP_UND,    // 001 1010 0 1001
-     OP_UND,    // 001 1010 0 1010
-     OP_UND,    // 001 1010 0 1011
-     OP_UND,    // 001 1010 0 1100
-     OP_UND,    // 001 1010 0 1101
-     OP_UND,    // 001 1010 0 1110
-     OP_UND,    // 001 1010 0 1111
+TABDECL(     OP_UND),    // 001 1010 0 0000
+TABDECL(     OP_UND),    // 001 1010 0 0001
+TABDECL(     OP_UND),    // 001 1010 0 0010
+TABDECL(     OP_UND),    // 001 1010 0 0011
+TABDECL(     OP_UND),    // 001 1010 0 0100
+TABDECL(     OP_UND),    // 001 1010 0 0101
+TABDECL(     OP_UND),    // 001 1010 0 0110
+TABDECL(     OP_UND),    // 001 1010 0 0111
+TABDECL(     OP_UND),    // 001 1010 0 1000
+TABDECL(     OP_UND),    // 001 1010 0 1001
+TABDECL(     OP_UND),    // 001 1010 0 1010
+TABDECL(     OP_UND),    // 001 1010 0 1011
+TABDECL(     OP_UND),    // 001 1010 0 1100
+TABDECL(     OP_UND),    // 001 1010 0 1101
+TABDECL(     OP_UND),    // 001 1010 0 1110
+TABDECL(     OP_UND),    // 001 1010 0 1111
      
-     OP_CMP_IMM_VAL,  // 001 1010 1 0000
-     OP_CMP_IMM_VAL,  // 001 1010 1 0001
-     OP_CMP_IMM_VAL,  // 001 1010 1 0010
-     OP_CMP_IMM_VAL,  // 001 1010 1 0011
-     OP_CMP_IMM_VAL,  // 001 1010 1 0100
-     OP_CMP_IMM_VAL,  // 001 1010 1 0101
-     OP_CMP_IMM_VAL,  // 001 1010 1 0110
-     OP_CMP_IMM_VAL,  // 001 1010 1 0111
-     OP_CMP_IMM_VAL,  // 001 1010 1 1000
-     OP_CMP_IMM_VAL,  // 001 1010 1 1001
-     OP_CMP_IMM_VAL,  // 001 1010 1 1010
-     OP_CMP_IMM_VAL,  // 001 1010 1 1011
-     OP_CMP_IMM_VAL,  // 001 1010 1 1100
-     OP_CMP_IMM_VAL,  // 001 1010 1 1101
-     OP_CMP_IMM_VAL,  // 001 1010 1 1110
-     OP_CMP_IMM_VAL,  // 001 1010 1 1111
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0000
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0001
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0010
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0011
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0100
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0101
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0110
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 0111
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1000
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1001
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1010
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1011
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1100
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1101
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1110
+TABDECL(     OP_CMP_IMM_VAL),  // 001 1010 1 1111
 //------------------------------------------
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0000
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0001
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0010
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0011
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0100
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0101
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0110
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 0111
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1000
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1001
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1010
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1011
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1100
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1101
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1110
-     OP_MSR_SPSR_IMM_VAL,    // 001 1011 0 1111
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0000
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0001
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0010
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0011
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0100
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0101
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0110
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 0111
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1000
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1001
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1010
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1011
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1100
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1101
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1110
+TABDECL(     OP_MSR_SPSR_IMM_VAL),    // 001 1011 0 1111
      
-     OP_CMN_IMM_VAL,  // 001 1011 1 0000
-     OP_CMN_IMM_VAL,  // 001 1011 1 0001
-     OP_CMN_IMM_VAL,  // 001 1011 1 0010
-     OP_CMN_IMM_VAL,  // 001 1011 1 0011
-     OP_CMN_IMM_VAL,  // 001 1011 1 0100
-     OP_CMN_IMM_VAL,  // 001 1011 1 0101
-     OP_CMN_IMM_VAL,  // 001 1011 1 0110
-     OP_CMN_IMM_VAL,  // 001 1011 1 0111
-     OP_CMN_IMM_VAL,  // 001 1011 1 1000
-     OP_CMN_IMM_VAL,  // 001 1011 1 1001
-     OP_CMN_IMM_VAL,  // 001 1011 1 1010
-     OP_CMN_IMM_VAL,  // 001 1011 1 1011
-     OP_CMN_IMM_VAL,  // 001 1011 1 1100
-     OP_CMN_IMM_VAL,  // 001 1011 1 1101
-     OP_CMN_IMM_VAL,  // 001 1011 1 1110
-     OP_CMN_IMM_VAL,  // 001 1011 1 1111
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0000
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0001
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0010
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0011
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0100
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0101
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0110
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 0111
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1000
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1001
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1010
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1011
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1100
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1101
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1110
+TABDECL(     OP_CMN_IMM_VAL),  // 001 1011 1 1111
 //------------------------------------------
-     OP_ORR_IMM_VAL,    // 001 1100 0 0000
-     OP_ORR_IMM_VAL,    // 001 1100 0 0001
-     OP_ORR_IMM_VAL,    // 001 1100 0 0010
-     OP_ORR_IMM_VAL,    // 001 1100 0 0011
-     OP_ORR_IMM_VAL,    // 001 1100 0 0100
-     OP_ORR_IMM_VAL,    // 001 1100 0 0101
-     OP_ORR_IMM_VAL,    // 001 1100 0 0110
-     OP_ORR_IMM_VAL,    // 001 1100 0 0111
-     OP_ORR_IMM_VAL,    // 001 1100 0 1000
-     OP_ORR_IMM_VAL,    // 001 1100 0 1001
-     OP_ORR_IMM_VAL,    // 001 1100 0 1010
-     OP_ORR_IMM_VAL,    // 001 1100 0 1011
-     OP_ORR_IMM_VAL,    // 001 1100 0 1100
-     OP_ORR_IMM_VAL,    // 001 1100 0 1101
-     OP_ORR_IMM_VAL,    // 001 1100 0 1110
-     OP_ORR_IMM_VAL,    // 001 1100 0 1111
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0000
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0001
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0010
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0011
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0100
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0101
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0110
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 0111
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1000
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1001
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1010
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1011
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1100
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1101
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1110
+TABDECL(     OP_ORR_IMM_VAL),    // 001 1100 0 1111
      
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0000
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0001
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0010
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0011
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0100
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0101
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0110
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 0111
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1000
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1001
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1010
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1011
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1100
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1101
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1110
-     OP_ORR_S_IMM_VAL,  // 001 1100 1 1111
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0000
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0001
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0010
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0011
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0100
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0101
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0110
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 0111
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1000
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1001
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1010
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1011
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1100
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1101
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1110
+TABDECL(     OP_ORR_S_IMM_VAL),  // 001 1100 1 1111
 //------------------------------------------
-     OP_MOV_IMM_VAL,    // 001 1101 0 0000
-     OP_MOV_IMM_VAL,    // 001 1101 0 0001
-     OP_MOV_IMM_VAL,    // 001 1101 0 0010
-     OP_MOV_IMM_VAL,    // 001 1101 0 0011
-     OP_MOV_IMM_VAL,    // 001 1101 0 0100
-     OP_MOV_IMM_VAL,    // 001 1101 0 0101
-     OP_MOV_IMM_VAL,    // 001 1101 0 0110
-     OP_MOV_IMM_VAL,    // 001 1101 0 0111
-     OP_MOV_IMM_VAL,    // 001 1101 0 1000
-     OP_MOV_IMM_VAL,    // 001 1101 0 1001
-     OP_MOV_IMM_VAL,    // 001 1101 0 1010
-     OP_MOV_IMM_VAL,    // 001 1101 0 1011
-     OP_MOV_IMM_VAL,    // 001 1101 0 1100
-     OP_MOV_IMM_VAL,    // 001 1101 0 1101
-     OP_MOV_IMM_VAL,    // 001 1101 0 1110
-     OP_MOV_IMM_VAL,    // 001 1101 0 1111
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0000
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0001
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0010
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0011
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0100
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0101
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0110
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 0111
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1000
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1001
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1010
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1011
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1100
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1101
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1110
+TABDECL(     OP_MOV_IMM_VAL),    // 001 1101 0 1111
      
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0000
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0001
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0010
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0011
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0100
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0101
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0110
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 0111
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1000
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1001
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1010
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1011
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1100
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1101
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1110
-     OP_MOV_S_IMM_VAL,  // 001 1101 1 1111
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0000
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0001
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0010
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0011
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0100
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0101
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0110
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 0111
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1000
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1001
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1010
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1011
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1100
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1101
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1110
+TABDECL(     OP_MOV_S_IMM_VAL),  // 001 1101 1 1111
 //------------------------------------------
-     OP_BIC_IMM_VAL,    // 001 1110 0 0000
-     OP_BIC_IMM_VAL,    // 001 1110 0 0001
-     OP_BIC_IMM_VAL,    // 001 1110 0 0010
-     OP_BIC_IMM_VAL,    // 001 1110 0 0011
-     OP_BIC_IMM_VAL,    // 001 1110 0 0100
-     OP_BIC_IMM_VAL,    // 001 1110 0 0101
-     OP_BIC_IMM_VAL,    // 001 1110 0 0110
-     OP_BIC_IMM_VAL,    // 001 1110 0 0111
-     OP_BIC_IMM_VAL,    // 001 1110 0 1000
-     OP_BIC_IMM_VAL,    // 001 1110 0 1001
-     OP_BIC_IMM_VAL,    // 001 1110 0 1010
-     OP_BIC_IMM_VAL,    // 001 1110 0 1011
-     OP_BIC_IMM_VAL,    // 001 1110 0 1100
-     OP_BIC_IMM_VAL,    // 001 1110 0 1101
-     OP_BIC_IMM_VAL,    // 001 1110 0 1110
-     OP_BIC_IMM_VAL,    // 001 1110 0 1111
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0000
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0001
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0010
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0011
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0100
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0101
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0110
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 0111
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1000
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1001
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1010
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1011
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1100
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1101
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1110
+TABDECL(     OP_BIC_IMM_VAL),    // 001 1110 0 1111
      
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0000
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0001
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0010
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0011
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0100
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0101
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0110
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 0111
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1000
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1001
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1010
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1011
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1100
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1101
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1110
-     OP_BIC_S_IMM_VAL,  // 001 1110 1 1111
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0000
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0001
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0010
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0011
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0100
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0101
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0110
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 0111
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1000
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1001
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1010
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1011
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1100
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1101
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1110
+TABDECL(     OP_BIC_S_IMM_VAL),  // 001 1110 1 1111
 //------------------------------------------
-     OP_MVN_IMM_VAL,    // 001 1111 0 0000
-     OP_MVN_IMM_VAL,    // 001 1111 0 0001
-     OP_MVN_IMM_VAL,    // 001 1111 0 0010
-     OP_MVN_IMM_VAL,    // 001 1111 0 0011
-     OP_MVN_IMM_VAL,    // 001 1111 0 0100
-     OP_MVN_IMM_VAL,    // 001 1111 0 0101
-     OP_MVN_IMM_VAL,    // 001 1111 0 0110
-     OP_MVN_IMM_VAL,    // 001 1111 0 0111
-     OP_MVN_IMM_VAL,    // 001 1111 0 1000
-     OP_MVN_IMM_VAL,    // 001 1111 0 1001
-     OP_MVN_IMM_VAL,    // 001 1111 0 1010
-     OP_MVN_IMM_VAL,    // 001 1111 0 1011
-     OP_MVN_IMM_VAL,    // 001 1111 0 1100
-     OP_MVN_IMM_VAL,    // 001 1111 0 1101
-     OP_MVN_IMM_VAL,    // 001 1111 0 1110
-     OP_MVN_IMM_VAL,    // 001 1111 0 1111
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0000
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0001
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0010
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0011
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0100
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0101
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0110
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 0111
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1000
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1001
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1010
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1011
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1100
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1101
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1110
+TABDECL(     OP_MVN_IMM_VAL),    // 001 1111 0 1111
      
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0000
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0001
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0010
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0011
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0100
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0101
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0110
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 0111
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1000
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1001
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1010
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1011
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1100
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1101
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1110
-     OP_MVN_S_IMM_VAL,  // 001 1111 1 1111
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0000
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0001
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0010
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0011
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0100
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0101
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0110
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 0111
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1000
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1001
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1010
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1011
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1100
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1101
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1110
+TABDECL(     OP_MVN_S_IMM_VAL),  // 001 1111 1 1111
 //------------------------------------------
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0000
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0001
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0010
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0011
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0100
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0101
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0110
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 0111
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1000
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1001
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1010
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1011
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1100
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1101
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1110
-     OP_STR_M_IMM_OFF_POSTIND,  //010 0000 0 1111
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0000
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0001
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0010
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0011
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0100
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0101
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0110
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 0111
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1000
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1001
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1010
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1011
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1100
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1101
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1110
+TABDECL(     OP_STR_M_IMM_OFF_POSTIND),  //010 0000 0 1111
      
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0000
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0001
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0010
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0011
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0100
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0101
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0110
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 0111
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1000
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1001
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1010
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1011
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1100
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1101
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1110
-     OP_LDR_M_IMM_OFF_POSTIND,  //010 0000 1 1111
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0000
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0001
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0010
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0011
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0100
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0101
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0110
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 0111
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1000
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1001
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1010
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1011
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1100
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1101
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1110
+TABDECL(     OP_LDR_M_IMM_OFF_POSTIND),  //010 0000 1 1111
 //------------------------------------------
-     OP_UND,  //010 0001 0 0000
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
+TABDECL(     OP_UND),  //010 0001 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0000
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0001
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0010
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0011
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0100
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0101
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0110
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 0111
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1000
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1001
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1010
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1011
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1100
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1101
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1110
-     OP_STRB_M_IMM_OFF_POSTIND,  //010 0010 0 1111
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0000
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0001
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0010
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0011
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0100
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0101
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0110
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 0111
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1000
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1001
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1010
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1011
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1100
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1101
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1110
+TABDECL(     OP_STRB_M_IMM_OFF_POSTIND),  //010 0010 0 1111
      
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0000
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0001
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0010
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0011
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0100
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0101
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0110
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 0111
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1000
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1001
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1010
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1011
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1100
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1101
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1110
-     OP_LDRB_M_IMM_OFF_POSTIND,  //010 0010 1 1111
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0000
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0001
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0010
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0011
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0100
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0101
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0110
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 0111
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1000
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1001
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1010
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1011
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1100
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1101
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1110
+TABDECL(     OP_LDRB_M_IMM_OFF_POSTIND),  //010 0010 1 1111
 //------------------------------------------
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_STRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_STRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
      
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
-     OP_LDRBT_M_IMM_OFF_POSTIND,  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
+TABDECL(     OP_LDRBT_M_IMM_OFF_POSTIND),  //010 0011 0 0000
 //------------------------------------------
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
      
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
 //------------------------------------------
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STR_P_IMM_OFF_POSTIND,  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_POSTIND),  //010 0100 0 0000
      
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
-     OP_LDR_P_IMM_OFF_POSTIND2,  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
+TABDECL(     OP_LDR_P_IMM_OFF_POSTIND2),  //010 0100 0 0000
 //------------------------------------------
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0110 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0110 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
      
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRB_P_IMM_OFF_POSTIND,  //010 0110 1 1111
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRB_P_IMM_OFF_POSTIND),  //010 0110 1 1111
 //------------------------------------------
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0111 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_STRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0111 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_STRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
      
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0100 0 0000
-     OP_LDRBT_P_IMM_OFF_POSTIND,  //010 0111 1 1111
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0100 0 0000
+TABDECL(     OP_LDRBT_P_IMM_OFF_POSTIND),  //010 0111 1 1111
 //------------------------------------------
-     OP_STR_M_IMM_OFF,  //010 1000 0 0000
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
-     OP_STR_M_IMM_OFF,
+TABDECL(     OP_STR_M_IMM_OFF),  //010 1000 0 0000
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
+TABDECL(     OP_STR_M_IMM_OFF),
      
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,
-     OP_LDR_M_IMM_OFF,  //010 1000 1 1111
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),
+TABDECL(     OP_LDR_M_IMM_OFF),  //010 1000 1 1111
 //------------------------------------------
-     OP_STR_M_IMM_OFF_PREIND,  //010 1001 0 0000
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
-     OP_STR_M_IMM_OFF_PREIND,
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),  //010 1001 0 0000
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
+TABDECL(     OP_STR_M_IMM_OFF_PREIND),
      
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,
-     OP_LDR_M_IMM_OFF_PREIND,  //010 1001 1 1111
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_M_IMM_OFF_PREIND),  //010 1001 1 1111
 //------------------------------------------
-     OP_STRB_M_IMM_OFF,  //010 1010 0 0000
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
-     OP_STRB_M_IMM_OFF,
+TABDECL(     OP_STRB_M_IMM_OFF),  //010 1010 0 0000
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
+TABDECL(     OP_STRB_M_IMM_OFF),
      
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,
-     OP_LDRB_M_IMM_OFF,  //010 1010 1 1111
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),
+TABDECL(     OP_LDRB_M_IMM_OFF),  //010 1010 1 1111
 //------------------------------------------
-     OP_STRB_M_IMM_OFF_PREIND,  //010 1011 0 0000
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
-     OP_STRB_M_IMM_OFF_PREIND,
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),  //010 1011 0 0000
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_M_IMM_OFF_PREIND),
      
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,
-     OP_LDRB_M_IMM_OFF_PREIND,  //010 1011 1 1111
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_M_IMM_OFF_PREIND),  //010 1011 1 1111
 //------------------------------------------
-     OP_STR_P_IMM_OFF,  //010 1100 0 0000
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
-     OP_STR_P_IMM_OFF,
+TABDECL(     OP_STR_P_IMM_OFF),  //010 1100 0 0000
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
+TABDECL(     OP_STR_P_IMM_OFF),
      
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,
-     OP_LDR_P_IMM_OFF,  //010 1100 1 1111
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),
+TABDECL(     OP_LDR_P_IMM_OFF),  //010 1100 1 1111
 //------------------------------------------
-     OP_STR_P_IMM_OFF_PREIND,  //010 1101 0 0000
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
-     OP_STR_P_IMM_OFF_PREIND,
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),  //010 1101 0 0000
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
+TABDECL(     OP_STR_P_IMM_OFF_PREIND),
      
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,
-     OP_LDR_P_IMM_OFF_PREIND,  //010 1101 1 1111
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDR_P_IMM_OFF_PREIND),  //010 1101 1 1111
 //------------------------------------------
-     OP_STRB_P_IMM_OFF,  //010 1110 0 0000
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
-     OP_STRB_P_IMM_OFF,
+TABDECL(     OP_STRB_P_IMM_OFF),  //010 1110 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
+TABDECL(     OP_STRB_P_IMM_OFF),
      
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,
-     OP_LDRB_P_IMM_OFF,  //010 1110 1 1111
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),
+TABDECL(     OP_LDRB_P_IMM_OFF),  //010 1110 1 1111
 //------------------------------------------
-     OP_STRB_P_IMM_OFF_PREIND,  //010 1111 0 0000
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
-     OP_STRB_P_IMM_OFF_PREIND,
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),  //010 1111 0 0000
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_STRB_P_IMM_OFF_PREIND),
      
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,
-     OP_LDRB_P_IMM_OFF_PREIND,  //010 1111 1 1111
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),
+TABDECL(     OP_LDRB_P_IMM_OFF_PREIND),  //010 1111 1 1111
 //------------------------------------------
-     OP_STR_M_LSL_IMM_OFF_POSTIND,  //011 0000 0 0000
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STR_M_LSL_IMM_OFF_POSTIND),  //011 0000 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDR_M_LSL_IMM_OFF_POSTIND,  
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,                        //011 0000 1 1111
+TABDECL(     OP_LDR_M_LSL_IMM_OFF_POSTIND),  
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),                        //011 0000 1 1111
 //------------------------------------------
-     OP_UND, //011 0001 0 0000
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND, //011 0001 1 1111
+TABDECL(     OP_UND), //011 0001 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND), //011 0001 1 1111
 //------------------------------------------
-     OP_STRB_M_LSL_IMM_OFF_POSTIND,  //011 0010 0 0000
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STRB_M_LSL_IMM_OFF_POSTIND),  //011 0010 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDRB_M_LSL_IMM_OFF_POSTIND,  
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,                         //011 0010 1 1111
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF_POSTIND),  
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),                         //011 0010 1 1111
 //------------------------------------------
-     OP_STRBT_M_LSL_IMM_OFF_POSTIND,  //011 0011 0 0000
-     OP_UND,
-     OP_STRBT_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STRBT_M_LSL_IMM_OFF_POSTIND),  //011 0011 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDRBT_M_LSL_IMM_OFF_POSTIND, 
-     OP_UND,
-     OP_LDRBT_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_M_ROR_IMM_OFF_POSTIND,
-     OP_UND,                            //011 0011 1 1111
+TABDECL(     OP_LDRBT_M_LSL_IMM_OFF_POSTIND), 
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_M_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),                            //011 0011 1 1111
 //------------------------------------------
-     OP_STR_P_LSL_IMM_OFF_POSTIND,  //011 0100 0 0000
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STR_P_LSL_IMM_OFF_POSTIND),  //011 0100 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDR_P_LSL_IMM_OFF_POSTIND,  
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,     //011 0100 1 1111
+TABDECL(     OP_LDR_P_LSL_IMM_OFF_POSTIND),  
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),     //011 0100 1 1111
 //------------------------------------------
-     OP_UND,  //011 0101 0 0000
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
+TABDECL(     OP_UND),  //011 0101 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
 
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,
-     OP_UND,   //011 0101 1 1111
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),
+TABDECL(     OP_UND),   //011 0101 1 1111
 //------------------------------------------
-     OP_STRB_P_LSL_IMM_OFF_POSTIND,  //011 0110 0 0000
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STRB_P_LSL_IMM_OFF_POSTIND),  //011 0110 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDRB_P_LSL_IMM_OFF_POSTIND,  
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,     
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF_POSTIND),  
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),     
 //------------------------------------------
-     OP_STRBT_P_LSL_IMM_OFF_POSTIND,  //011 0111 0 0000
-     OP_UND,
-     OP_STRBT_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_STRBT_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
+TABDECL(     OP_STRBT_P_LSL_IMM_OFF_POSTIND),  //011 0111 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRBT_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
      
-     OP_LDRBT_P_LSL_IMM_OFF_POSTIND, 
-     OP_UND,
-     OP_LDRBT_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_LSL_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_LSR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_ASR_IMM_OFF_POSTIND,
-     OP_UND,
-     OP_LDRBT_P_ROR_IMM_OFF_POSTIND,
-     OP_UND,     
+TABDECL(     OP_LDRBT_P_LSL_IMM_OFF_POSTIND), 
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_LSL_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_LSR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_ASR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRBT_P_ROR_IMM_OFF_POSTIND),
+TABDECL(     OP_UND),     
 //------------------------------------------
-     OP_STR_M_LSL_IMM_OFF,  //011 1000 0 0000
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF,
-     OP_UND,
-     OP_STR_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_STR_M_LSL_IMM_OFF),  //011 1000 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
      
-     OP_LDR_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_LDR_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STR_M_LSL_IMM_OFF_PREIND,  //011 1001 0 0000
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_STR_M_LSL_IMM_OFF_PREIND),  //011 1001 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
      
-     OP_LDR_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_LDR_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STRB_M_LSL_IMM_OFF,  //011 1010 0 0000
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_STRB_M_LSL_IMM_OFF),  //011 1010 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
      
-     OP_LDRB_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STRB_M_LSL_IMM_OFF_PREIND, //011 1011 0 0000
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_STRB_M_LSL_IMM_OFF_PREIND), //011 1011 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
      
-     OP_LDRB_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_M_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_M_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STR_P_LSL_IMM_OFF, //011 1100 0 0000
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF,
-     OP_UND,
-     OP_STR_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_STR_P_LSL_IMM_OFF), //011 1100 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
      
-     OP_LDR_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_LDR_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STR_P_LSL_IMM_OFF_PREIND, //011 1101 0 0000
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STR_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_STR_P_LSL_IMM_OFF_PREIND), //011 1101 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STR_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
      
-     OP_LDR_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDR_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_LDR_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDR_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STRB_P_LSL_IMM_OFF, //011 1110 0 0000
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_STRB_P_LSL_IMM_OFF), //011 1110 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
      
-     OP_LDRB_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_LSL_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF,
-     OP_UND,
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF),
+TABDECL(     OP_UND),
 //------------------------------------------
-     OP_STRB_P_LSL_IMM_OFF_PREIND, //011 1111 0 0000
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_STRB_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
+TABDECL(     OP_STRB_P_LSL_IMM_OFF_PREIND), //011 1111 0 0000
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_STRB_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
      
-     OP_LDRB_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_LSL_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_LSR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_ASR_IMM_OFF_PREIND,
-     OP_UND,
-     OP_LDRB_P_ROR_IMM_OFF_PREIND,
-     OP_UND,           //011 1111 1 1111
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSL_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_LSR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ASR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),
+TABDECL(     OP_LDRB_P_ROR_IMM_OFF_PREIND),
+TABDECL(     OP_UND),           //011 1111 1 1111
 //------------------------------------------
-     OP_STMDA, //100 0000 0 0000
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
-     OP_STMDA,
+TABDECL(     OP_STMDA), //100 0000 0 0000
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
+TABDECL(     OP_STMDA),
      
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
-     OP_LDMDA,
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
+TABDECL(     OP_LDMDA),
 //------------------------------------------
-     OP_STMDA_W, //100 0001 0 0000
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
-     OP_STMDA_W,
+TABDECL(     OP_STMDA_W), //100 0001 0 0000
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
+TABDECL(     OP_STMDA_W),
      
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
-     OP_LDMDA_W,
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
+TABDECL(     OP_LDMDA_W),
 //------------------------------------------
-     OP_STMDA2, //100 0010 0 0000
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
-     OP_STMDA2,
+TABDECL(     OP_STMDA2), //100 0010 0 0000
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
+TABDECL(     OP_STMDA2),
      
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
-     OP_LDMDA2,
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
+TABDECL(     OP_LDMDA2),
 //------------------------------------------
-     OP_STMDA2_W, //100 0011 0 0000
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
-     OP_STMDA2_W,
+TABDECL(     OP_STMDA2_W), //100 0011 0 0000
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
+TABDECL(     OP_STMDA2_W),
      
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
-     OP_LDMDA2_W,
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
+TABDECL(     OP_LDMDA2_W),
 //------------------------------------------
-     OP_STMIA, //100 0100 0 0000
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
-     OP_STMIA,
+TABDECL(     OP_STMIA), //100 0100 0 0000
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
+TABDECL(     OP_STMIA),
      
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
-     OP_LDMIA,
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
+TABDECL(     OP_LDMIA),
 //------------------------------------------
-     OP_STMIA_W, //100 0101 0 0000
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
-     OP_STMIA_W,
+TABDECL(     OP_STMIA_W), //100 0101 0 0000
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
+TABDECL(     OP_STMIA_W),
      
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
-     OP_LDMIA_W,
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
+TABDECL(     OP_LDMIA_W),
 //------------------------------------------
-     OP_STMIA2, //100 0110 0 0000
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
-     OP_STMIA2,
+TABDECL(     OP_STMIA2), //100 0110 0 0000
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
+TABDECL(     OP_STMIA2),
      
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
-     OP_LDMIA2,
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
+TABDECL(     OP_LDMIA2),
 //------------------------------------------
-     OP_STMIA2_W, //100 0111 0 0000
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
-     OP_STMIA2_W,
+TABDECL(     OP_STMIA2_W), //100 0111 0 0000
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
+TABDECL(     OP_STMIA2_W),
      
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
-     OP_LDMIA2_W,
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
+TABDECL(     OP_LDMIA2_W),
 //------------------------------------------
-     OP_STMDB, //100 1000 0 0000
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
-     OP_STMDB,
+TABDECL(     OP_STMDB), //100 1000 0 0000
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
+TABDECL(     OP_STMDB),
      
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
-     OP_LDMDB,
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
+TABDECL(     OP_LDMDB),
 //------------------------------------------
-     OP_STMDB_W, //100 1001 0 0000
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
-     OP_STMDB_W,
+TABDECL(     OP_STMDB_W), //100 1001 0 0000
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
+TABDECL(     OP_STMDB_W),
      
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
-     OP_LDMDB_W,
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
+TABDECL(     OP_LDMDB_W),
 //------------------------------------------
-     OP_STMDB2, //100 1010 0 0000
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
-     OP_STMDB2,
+TABDECL(     OP_STMDB2), //100 1010 0 0000
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
+TABDECL(     OP_STMDB2),
      
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
-     OP_LDMDB2,
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
+TABDECL(     OP_LDMDB2),
 //------------------------------------------
-     OP_STMDB2_W, //100 1011 0 0000
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
-     OP_STMDB2_W,
+TABDECL(     OP_STMDB2_W), //100 1011 0 0000
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
+TABDECL(     OP_STMDB2_W),
      
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
-     OP_LDMDB2_W,
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
+TABDECL(     OP_LDMDB2_W),
 //------------------------------------------
 
 
-     OP_STMIB, //100 1100 0 0000
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
-     OP_STMIB,
+TABDECL(     OP_STMIB), //100 1100 0 0000
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
+TABDECL(     OP_STMIB),
      
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
-     OP_LDMIB,
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
+TABDECL(     OP_LDMIB),
 //------------------------------------------
-     OP_STMIB_W, //100 1101 0 0000
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
-     OP_STMIB_W,
+TABDECL(     OP_STMIB_W), //100 1101 0 0000
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
+TABDECL(     OP_STMIB_W),
      
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
-     OP_LDMIB_W,
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
+TABDECL(     OP_LDMIB_W),
 //------------------------------------------
-     OP_STMIB2, //100 1110 0 0000
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
-     OP_STMIB2,
+TABDECL(     OP_STMIB2), //100 1110 0 0000
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
+TABDECL(     OP_STMIB2),
      
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
-     OP_LDMIB2,
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
+TABDECL(     OP_LDMIB2),
 //------------------------------------------
-     OP_STMIB2_W, //100 1111 0 0000
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
-     OP_STMIB2_W,
+TABDECL(     OP_STMIB2_W), //100 1111 0 0000
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
+TABDECL(     OP_STMIB2_W),
      
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
-     OP_LDMIB2_W,
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
+TABDECL(     OP_LDMIB2_W),
 //------------------------------------------
-     OP_B, //101 0000 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0000 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0001 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0001 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0010 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0010 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0011 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0011 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0100 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0100 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0101 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0101 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0110 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0110 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_B, //101 0111 0 0000
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
-     OP_B,
+TABDECL(     OP_B), //101 0111 0 0000
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
+TABDECL(     OP_B),
 //------------------------------------------
-     OP_BL, //101 1000 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1000 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1001 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1001 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1010 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1010 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1011 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1011 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1100 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1100 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1101 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1101 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1110 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1110 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_BL, //101 1111 0 0000
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
-     OP_BL,
+TABDECL(     OP_BL), //101 1111 0 0000
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
+TABDECL(     OP_BL),
 //------------------------------------------
-     OP_STC_OPTION,  //110 0000 0 0000
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
+TABDECL(     OP_STC_OPTION),  //110 0000 0 0000
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
      
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
 //------------------------------------------
-     OP_STC_M_POSTIND,  //110 0001 0 0000
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
+TABDECL(     OP_STC_M_POSTIND),  //110 0001 0 0000
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
      
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
 //------------------------------------------
-     OP_STC_OPTION,  //110 0010 0 0000
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
+TABDECL(     OP_STC_OPTION),  //110 0010 0 0000
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
      
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
 //------------------------------------------
-     OP_STC_M_POSTIND,  //110 0011 0 0000
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
-     OP_STC_M_POSTIND,
+TABDECL(     OP_STC_M_POSTIND),  //110 0011 0 0000
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
+TABDECL(     OP_STC_M_POSTIND),
      
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
-     OP_LDC_M_POSTIND,
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
+TABDECL(     OP_LDC_M_POSTIND),
 //------------------------------------------
-     OP_STC_OPTION,  //110 0100 0 0000
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
+TABDECL(     OP_STC_OPTION),  //110 0100 0 0000
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
      
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
 //------------------------------------------
-     OP_STC_P_POSTIND,  //110 0101 0 0000
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
+TABDECL(     OP_STC_P_POSTIND),  //110 0101 0 0000
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
      
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
 //------------------------------------------
-     OP_STC_OPTION,  //110 0110 0 0000
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
-     OP_STC_OPTION,
+TABDECL(     OP_STC_OPTION),  //110 0110 0 0000
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
+TABDECL(     OP_STC_OPTION),
      
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
-     OP_LDC_OPTION,
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
+TABDECL(     OP_LDC_OPTION),
 //------------------------------------------
-     OP_STC_P_POSTIND,  //110 0111 0 0000
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
-     OP_STC_P_POSTIND,
+TABDECL(     OP_STC_P_POSTIND),  //110 0111 0 0000
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
+TABDECL(     OP_STC_P_POSTIND),
      
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
-     OP_LDC_P_POSTIND,
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
+TABDECL(     OP_LDC_P_POSTIND),
 //------------------------------------------
-     OP_STC_M_IMM_OFF,  //110 1000 0 0000
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
+TABDECL(     OP_STC_M_IMM_OFF),  //110 1000 0 0000
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
      
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
 //------------------------------------------
-     OP_STC_M_PREIND,  //110 1001 0 0000
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
+TABDECL(     OP_STC_M_PREIND),  //110 1001 0 0000
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
      
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
 //------------------------------------------
-     OP_STC_M_IMM_OFF,  //110 1010 0 0000
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
-     OP_STC_M_IMM_OFF,
+TABDECL(     OP_STC_M_IMM_OFF),  //110 1010 0 0000
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
+TABDECL(     OP_STC_M_IMM_OFF),
      
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
-     OP_LDC_M_IMM_OFF,
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
+TABDECL(     OP_LDC_M_IMM_OFF),
 //------------------------------------------
-     OP_STC_M_PREIND,  //110 1011 0 0000
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
-     OP_STC_M_PREIND,
+TABDECL(     OP_STC_M_PREIND),  //110 1011 0 0000
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
+TABDECL(     OP_STC_M_PREIND),
      
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
-     OP_LDC_M_PREIND,
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
+TABDECL(     OP_LDC_M_PREIND),
 //------------------------------------------
-     OP_STC_P_IMM_OFF,  //110 1100 0 0000
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
+TABDECL(     OP_STC_P_IMM_OFF),  //110 1100 0 0000
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
      
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
 //------------------------------------------
-     OP_STC_P_PREIND,  //110 1101 0 0000
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
+TABDECL(     OP_STC_P_PREIND),  //110 1101 0 0000
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
      
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
 //------------------------------------------
-     OP_STC_P_IMM_OFF,  //110 1110 0 0000
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
-     OP_STC_P_IMM_OFF,
+TABDECL(     OP_STC_P_IMM_OFF),  //110 1110 0 0000
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
+TABDECL(     OP_STC_P_IMM_OFF),
      
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
-     OP_LDC_P_IMM_OFF,
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
+TABDECL(     OP_LDC_P_IMM_OFF),
 //------------------------------------------
-     OP_STC_P_PREIND,  //110 1111 0 0000
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
-     OP_STC_P_PREIND,
+TABDECL(     OP_STC_P_PREIND),  //110 1111 0 0000
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
+TABDECL(     OP_STC_P_PREIND),
      
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
-     OP_LDC_P_PREIND,
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
+TABDECL(     OP_LDC_P_PREIND),
 //------------------------------------------
-     OP_CDP,  //111 0000 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0000 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0001 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0001 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0010 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0010 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0011 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0011 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0100 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0100 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0101 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0101 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0110 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0110 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_CDP,  //111 0111 0 0000
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
-     OP_CDP,
-     OP_MCR,
+TABDECL(     OP_CDP),  //111 0111 0 0000
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MCR),
      
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
-     OP_CDP,
-     OP_MRC,
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
+TABDECL(     OP_CDP),
+TABDECL(     OP_MRC),
 //---------------------------------------------
-     OP_SWI,  //111 1000 0 0000
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI, 
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
-     OP_SWI,
+TABDECL(     OP_SWI),  //111 1000 0 0000
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI), 
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
+TABDECL(     OP_SWI),
 };
 
diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp
index 145a7f4f9..7d91d6b00 100644
--- a/desmume/src/thumb_instructions.cpp
+++ b/desmume/src/thumb_instructions.cpp
@@ -33,6 +33,9 @@
 #include "debug.h"
 #include "MMU.h"
 
+#define cpu (&ARMPROC)
+#define TEMPLATE template<int PROCNUM> 
+
 #define REG_NUM(i, n) (((i)>>n)&0x7)
 
 extern volatile BOOL execute;
@@ -54,13 +57,13 @@ extern volatile BOOL execute;
 	#define WRITE8(a,b,c)	MMU_write8(cpu->proc_ID,b,c)
 #endif
 
-static u32 FASTCALL OP_UND_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_UND_THUMB()
 {
      execute = FALSE;
      return 1;
 }
 
-static u32 FASTCALL OP_LSL_0(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSL_0()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] = cpu->R[REG_NUM(i, 3)];
@@ -70,7 +73,7 @@ static u32 FASTCALL OP_LSL_0(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_LSL(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSL()
 {
      u32 i = cpu->instruction;
      u32 v = (i>>6) & 0x1F;
@@ -82,7 +85,7 @@ static u32 FASTCALL OP_LSL(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_LSR_0(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSR_0()
 {
      u32 i = cpu->instruction;
 	  // cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 0)]);
@@ -94,7 +97,7 @@ static u32 FASTCALL OP_LSR_0(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_LSR(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSR()
 {
      u32 i = cpu->instruction;
      u32 v = (i>>6) & 0x1F;
@@ -106,7 +109,7 @@ static u32 FASTCALL OP_LSR(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_ASR_0(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ASR_0()
 {
      u32 i = cpu->instruction;
      cpu->CPSR.bits.C = BIT31(cpu->R[REG_NUM(i, 3)]);
@@ -117,7 +120,7 @@ static u32 FASTCALL OP_ASR_0(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_ASR(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ASR()
 {
      u32 i = cpu->instruction;
      u32 v = (i>>6) & 0x1F;
@@ -129,7 +132,7 @@ static u32 FASTCALL OP_ASR(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_ADD_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_REG()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 3)];
@@ -143,7 +146,7 @@ static u32 FASTCALL OP_ADD_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_SUB_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_SUB_REG()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 3)];
@@ -157,7 +160,7 @@ static u32 FASTCALL OP_SUB_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_IMM3()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 3)];
@@ -170,7 +173,7 @@ static u32 FASTCALL OP_ADD_IMM3(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_SUB_IMM3()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 3)];
@@ -183,7 +186,7 @@ static u32 FASTCALL OP_SUB_IMM3(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_MOV_IMM8()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 8)] = i & 0xFF;
@@ -193,7 +196,7 @@ static u32 FASTCALL OP_MOV_IMM8(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_CMP_IMM8()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
@@ -205,7 +208,7 @@ static u32 FASTCALL OP_CMP_IMM8(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_IMM8()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 8)] + (i & 0xFF);
@@ -218,7 +221,7 @@ static u32 FASTCALL OP_ADD_IMM8(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_SUB_IMM8()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 8)] - (i & 0xFF);
@@ -231,7 +234,7 @@ static u32 FASTCALL OP_SUB_IMM8(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_AND(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_AND()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] &= cpu->R[REG_NUM(i, 3)];
@@ -241,7 +244,7 @@ static u32 FASTCALL OP_AND(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_EOR(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_EOR()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] ^= cpu->R[REG_NUM(i, 3)];
@@ -251,7 +254,7 @@ static u32 FASTCALL OP_EOR(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_LSL_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSL_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@@ -281,7 +284,7 @@ static u32 FASTCALL OP_LSL_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_LSR_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LSR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@@ -311,7 +314,7 @@ static u32 FASTCALL OP_LSR_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ASR_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ASR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@@ -339,7 +342,7 @@ static u32 FASTCALL OP_ASR_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ADC_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADC_REG()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 0)];
@@ -358,7 +361,7 @@ static u32 FASTCALL OP_ADC_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_SBC_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_SBC_REG()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 0)];
@@ -376,7 +379,7 @@ static u32 FASTCALL OP_SBC_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ROR_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ROR_REG()
 {
      u32 i = cpu->instruction;
      u32 v = cpu->R[REG_NUM(i, 3)]&0xFF;
@@ -403,7 +406,7 @@ static u32 FASTCALL OP_ROR_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_TST(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_TST()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 0)] & cpu->R[REG_NUM(i, 3)];
@@ -413,7 +416,7 @@ static u32 FASTCALL OP_TST(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_NEG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_NEG()
 {
      u32 i = cpu->instruction;
      u32 a = cpu->R[REG_NUM(i, 3)];
@@ -427,7 +430,7 @@ static u32 FASTCALL OP_NEG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_CMP(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_CMP()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 0)] -cpu->R[REG_NUM(i, 3)];
@@ -440,7 +443,7 @@ static u32 FASTCALL OP_CMP(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_CMN(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_CMN()
 {
      u32 i = cpu->instruction;
      u32 tmp = cpu->R[REG_NUM(i, 0)] + cpu->R[REG_NUM(i, 3)];
@@ -455,7 +458,7 @@ static u32 FASTCALL OP_CMN(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ORR(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ORR()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] |= cpu->R[REG_NUM(i, 3)];
@@ -465,7 +468,7 @@ static u32 FASTCALL OP_ORR(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_MUL_REG(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_MUL_REG()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] *= cpu->R[REG_NUM(i, 3)];
@@ -475,7 +478,7 @@ static u32 FASTCALL OP_MUL_REG(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_BIC(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BIC()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] &= (~cpu->R[REG_NUM(i, 3)]);
@@ -485,7 +488,7 @@ static u32 FASTCALL OP_BIC(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_MVN(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_MVN()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 0)] = (~cpu->R[REG_NUM(i, 3)]);
@@ -495,7 +498,7 @@ static u32 FASTCALL OP_MVN(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_SPE()
 {
      u32 i = cpu->instruction;
      u32 Rd = (i&7) | ((i>>4)&8);
@@ -507,7 +510,7 @@ static u32 FASTCALL OP_ADD_SPE(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_CMP_SPE()
 {
      u32 i = cpu->instruction;
      u32 Rn = (i&7) | ((i>>4)&8);
@@ -521,7 +524,7 @@ static u32 FASTCALL OP_CMP_SPE(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_MOV_SPE()
 {
      u32 i = cpu->instruction;
      u32 Rd = (i&7) | ((i>>4)&8);
@@ -533,7 +536,7 @@ static u32 FASTCALL OP_MOV_SPE(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BX_THUMB()
 {
      u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)];
      
@@ -544,7 +547,7 @@ static u32 FASTCALL OP_BX_THUMB(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BLX_THUMB()
 {
      u32 Rm = cpu->R[REG_POS(cpu->instruction, 3)];
      
@@ -556,7 +559,7 @@ static u32 FASTCALL OP_BLX_THUMB(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDR_PCREL()
 {
 	u32 adr = (cpu->R[15]&0xFFFFFFFC) + ((cpu->instruction&0xFF)<<2);
      
@@ -565,7 +568,7 @@ static u32 FASTCALL OP_LDR_PCREL(armcpu_t *cpu)
     return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STR_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 6)] + cpu->R[REG_NUM(i, 3)];
@@ -574,7 +577,7 @@ static u32 FASTCALL OP_STR_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STRH_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -583,7 +586,7 @@ static u32 FASTCALL OP_STRH_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STRB_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -592,7 +595,7 @@ static u32 FASTCALL OP_STRB_REG_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRSB_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -601,7 +604,7 @@ static u32 FASTCALL OP_LDRSB_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDR_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = (cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)]);
@@ -614,7 +617,7 @@ static u32 FASTCALL OP_LDR_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRH_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -623,7 +626,7 @@ static u32 FASTCALL OP_LDRH_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRB_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -632,7 +635,7 @@ static u32 FASTCALL OP_LDRB_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRSH_REG_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + cpu->R[REG_NUM(i, 6)];
@@ -641,7 +644,7 @@ static u32 FASTCALL OP_LDRSH_REG_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
@@ -650,7 +653,7 @@ static u32 FASTCALL OP_STR_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDR_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>4)&0x7C);
@@ -662,7 +665,7 @@ static u32 FASTCALL OP_LDR_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STRB_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
@@ -671,7 +674,7 @@ static u32 FASTCALL OP_STRB_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRB_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>6)&0x1F);
@@ -680,7 +683,7 @@ static u32 FASTCALL OP_LDRB_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STRH_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
@@ -689,7 +692,7 @@ static u32 FASTCALL OP_STRH_IMM_OFF(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDRH_IMM_OFF()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 3)] + ((i>>5)&0x3E);
@@ -698,7 +701,7 @@ static u32 FASTCALL OP_LDRH_IMM_OFF(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STR_SPREL()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13] + ((i&0xFF)<<2);
@@ -707,7 +710,7 @@ static u32 FASTCALL OP_STR_SPREL(armcpu_t *cpu)
      return 2 + MMU.MMU_WAIT16[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDR_SPREL()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13] + ((i&0xFF)<<2);
@@ -716,7 +719,7 @@ static u32 FASTCALL OP_LDR_SPREL(armcpu_t *cpu)
      return 3 + MMU.MMU_WAIT32[cpu->proc_ID][(adr>>24)&0xF];
 }
 
-static u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_2PC()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 8)] = (cpu->R[15]&0xFFFFFFFC) + ((i&0xFF)<<2);
@@ -724,7 +727,7 @@ static u32 FASTCALL OP_ADD_2PC(armcpu_t *cpu)
      return 5;
 }
 
-static u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADD_2SP()
 {
      u32 i = cpu->instruction;
      cpu->R[REG_NUM(i, 8)] = cpu->R[13] + ((i&0xFF)<<2);
@@ -732,21 +735,21 @@ static u32 FASTCALL OP_ADD_2SP(armcpu_t *cpu)
      return 2;
 }
 
-static u32 FASTCALL OP_ADJUST_P_SP(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADJUST_P_SP()
 {
      cpu->R[13] += ((cpu->instruction&0x7F)<<2);
      
      return 1;
 }
 
-static u32 FASTCALL OP_ADJUST_M_SP(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_ADJUST_M_SP()
 {
      cpu->R[13] -= ((cpu->instruction&0x7F)<<2);
      
      return 1;
 }
 
-static u32 FASTCALL OP_PUSH(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_PUSH()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13] - 4;
@@ -764,7 +767,7 @@ static u32 FASTCALL OP_PUSH(armcpu_t *cpu)
      return c + 3;
 }
 
-static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_PUSH_LR()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13] - 4;
@@ -786,7 +789,7 @@ static u32 FASTCALL OP_PUSH_LR(armcpu_t *cpu)
      return c + 4;
 }
 
-static u32 FASTCALL OP_POP(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_POP()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13];
@@ -804,7 +807,7 @@ static u32 FASTCALL OP_POP(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL OP_POP_PC(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_POP_PC()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[13];
@@ -831,12 +834,12 @@ static u32 FASTCALL OP_POP_PC(armcpu_t *cpu)
      return c + 5;    
 }
 
-static u32 FASTCALL OP_BKPT_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BKPT_THUMB()
 {
      return 1;
 }
 
-static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_STMIA_THUMB()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 8)];
@@ -853,7 +856,7 @@ static u32 FASTCALL OP_STMIA_THUMB(armcpu_t *cpu)
      return c + 2;
 }
 
-static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_LDMIA_THUMB()
 {
      u32 i = cpu->instruction;
      u32 adr = cpu->R[REG_NUM(i, 8)];
@@ -870,7 +873,7 @@ static u32 FASTCALL OP_LDMIA_THUMB(armcpu_t *cpu)
      return c + 3;
 }
 
-static u32 FASTCALL OP_B_COND(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_B_COND()
 {
      u32 i = cpu->instruction;
      if(!TEST_COND((i>>8)&0xF, 0, cpu->CPSR))
@@ -881,7 +884,7 @@ static u32 FASTCALL OP_B_COND(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_SWI_THUMB()
 {
      if (((cpu->intVector != 0) ^ (cpu->proc_ID == ARMCPU_ARM9)))
      {
@@ -907,7 +910,7 @@ static u32 FASTCALL OP_SWI_THUMB(armcpu_t *cpu)
 
 #define SIGNEEXT_IMM11(i)     (((i)&0x7FF) | (BIT10(i) * 0xFFFFF800))
 
-static u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_B_UNCOND()
 {
      u32 i = cpu->instruction;
      cpu->R[15] += (SIGNEEXT_IMM11(i)<<1);
@@ -915,7 +918,7 @@ static u32 FASTCALL OP_B_UNCOND(armcpu_t *cpu)
      return 3;
 }
  
-static u32 FASTCALL OP_BLX(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BLX()
 {
      u32 i = cpu->instruction;
      cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1))&0xFFFFFFFC;
@@ -925,14 +928,14 @@ static u32 FASTCALL OP_BLX(armcpu_t *cpu)
      return 3;
 }
 
-static u32 FASTCALL OP_BL_10(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BL_10()
 {
      u32 i = cpu->instruction;
      cpu->R[14] = cpu->R[15] + (SIGNEEXT_IMM11(i)<<12);
      return 1;
 }
 
-static u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu)
+TEMPLATE static  u32 FASTCALL OP_BL_THUMB()
 {
      u32 i = cpu->instruction;
      cpu->R[15] = (cpu->R[14] + ((i&0x7FF)<<1));
@@ -943,7 +946,22 @@ static u32 FASTCALL OP_BL_THUMB(armcpu_t *cpu)
 
 #define TYPE_RETOUR u32
 #define CALLTYPE FASTCALL 
-#define PARAMETRES  armcpu_t *cpu
-#define NOM_THUMB_TAB     thumb_instructions_set
+#define PARAMETRES
+#define NOM_THUMB_TAB     thumb_instructions_set_0
+#define TABDECL(x)		x<0>
 
 #include "thumb_tabdef.inc"
+
+#undef TYPE_RETOUR
+#undef PARAMETRES  
+#undef CALLTYPE
+#undef NOM_THUMB_TAB
+#undef TABDECL
+
+#define TYPE_RETOUR u32
+#define PARAMETRES  
+#define CALLTYPE    FASTCALL 
+#define NOM_THUMB_TAB     thumb_instructions_set_1
+#define TABDECL(x)		x<1>
+
+#include "thumb_tabdef.inc"
\ No newline at end of file
diff --git a/desmume/src/thumb_instructions.h b/desmume/src/thumb_instructions.h
index 27088a6e3..08db2521c 100644
--- a/desmume/src/thumb_instructions.h
+++ b/desmume/src/thumb_instructions.h
@@ -24,7 +24,8 @@
 
 #include "armcpu.h"
 
-extern u32 (FASTCALL* thumb_instructions_set[1024])(armcpu_t * cpu);
+extern u32 (FASTCALL* thumb_instructions_set_0[1024])();
+extern u32 (FASTCALL* thumb_instructions_set_1[1024])();
 
 #endif
  
diff --git a/desmume/src/thumb_tabdef.inc b/desmume/src/thumb_tabdef.inc
index 1a9c53b03..dbe80733d 100644
--- a/desmume/src/thumb_tabdef.inc
+++ b/desmume/src/thumb_tabdef.inc
@@ -20,1092 +20,1092 @@
 */
 
 TYPE_RETOUR (* CALLTYPE NOM_THUMB_TAB[1024])(PARAMETRES)={
-            OP_LSL_0,  //00 0000 0000
-            OP_LSL,  //00 0000 0001
-            OP_LSL,  //00 0000 0010
-            OP_LSL,  //00 0000 0011
-            OP_LSL,  //00 0000 0100
-            OP_LSL,  //00 0000 0101
-            OP_LSL,  //00 0000 0110
-            OP_LSL,  //00 0000 0111
-            OP_LSL,  //00 0000 1000
-            OP_LSL,  //00 0000 1001
-            OP_LSL,  //00 0000 1010
-            OP_LSL,  //00 0000 1011
-            OP_LSL,  //00 0000 1100
-            OP_LSL,  //00 0000 1101
-            OP_LSL,  //00 0000 1110
-            OP_LSL,  //00 0000 1111
+TABDECL(            OP_LSL_0),  //00 0000 0000
+TABDECL(            OP_LSL),  //00 0000 0001
+TABDECL(            OP_LSL),  //00 0000 0010
+TABDECL(            OP_LSL),  //00 0000 0011
+TABDECL(            OP_LSL),  //00 0000 0100
+TABDECL(            OP_LSL),  //00 0000 0101
+TABDECL(            OP_LSL),  //00 0000 0110
+TABDECL(            OP_LSL),  //00 0000 0111
+TABDECL(            OP_LSL),  //00 0000 1000
+TABDECL(            OP_LSL),  //00 0000 1001
+TABDECL(            OP_LSL),  //00 0000 1010
+TABDECL(            OP_LSL),  //00 0000 1011
+TABDECL(            OP_LSL),  //00 0000 1100
+TABDECL(            OP_LSL),  //00 0000 1101
+TABDECL(            OP_LSL),  //00 0000 1110
+TABDECL(            OP_LSL),  //00 0000 1111
 
-            OP_LSL,  //00 0001 0000
-            OP_LSL,  //00 0001 0001
-            OP_LSL,  //00 0001 0010
-            OP_LSL,  //00 0001 0011
-            OP_LSL,  //00 0001 0100
-            OP_LSL,  //00 0001 0101
-            OP_LSL,  //00 0001 0110
-            OP_LSL,  //00 0001 0111
-            OP_LSL,  //00 0001 1000
-            OP_LSL,  //00 0001 1001
-            OP_LSL,  //00 0001 1010
-            OP_LSL,  //00 0001 1011
-            OP_LSL,  //00 0001 1100
-            OP_LSL,  //00 0001 1101
-            OP_LSL,  //00 0001 1110
-            OP_LSL,  //00 0001 1111
+TABDECL(            OP_LSL),  //00 0001 0000
+TABDECL(            OP_LSL),  //00 0001 0001
+TABDECL(            OP_LSL),  //00 0001 0010
+TABDECL(            OP_LSL),  //00 0001 0011
+TABDECL(            OP_LSL),  //00 0001 0100
+TABDECL(            OP_LSL),  //00 0001 0101
+TABDECL(            OP_LSL),  //00 0001 0110
+TABDECL(            OP_LSL),  //00 0001 0111
+TABDECL(            OP_LSL),  //00 0001 1000
+TABDECL(            OP_LSL),  //00 0001 1001
+TABDECL(            OP_LSL),  //00 0001 1010
+TABDECL(            OP_LSL),  //00 0001 1011
+TABDECL(            OP_LSL),  //00 0001 1100
+TABDECL(            OP_LSL),  //00 0001 1101
+TABDECL(            OP_LSL),  //00 0001 1110
+TABDECL(            OP_LSL),  //00 0001 1111
 
-            OP_LSR_0,  //00 0010 0000
-            OP_LSR,  //00 0010 0001
-            OP_LSR,  //00 0010 0010
-            OP_LSR,  //00 0010 0011
-            OP_LSR,  //00 0010 0100
-            OP_LSR,  //00 0010 0101
-            OP_LSR,  //00 0010 0110
-            OP_LSR,  //00 0010 0111
-            OP_LSR,  //00 0010 1000
-            OP_LSR,  //00 0010 1001
-            OP_LSR,  //00 0010 1010
-            OP_LSR,  //00 0010 1011
-            OP_LSR,  //00 0010 1100
-            OP_LSR,  //00 0010 1101
-            OP_LSR,  //00 0010 1110
-            OP_LSR,  //00 0010 1111
+TABDECL(            OP_LSR_0),  //00 0010 0000
+TABDECL(            OP_LSR),  //00 0010 0001
+TABDECL(            OP_LSR),  //00 0010 0010
+TABDECL(            OP_LSR),  //00 0010 0011
+TABDECL(            OP_LSR),  //00 0010 0100
+TABDECL(            OP_LSR),  //00 0010 0101
+TABDECL(            OP_LSR),  //00 0010 0110
+TABDECL(            OP_LSR),  //00 0010 0111
+TABDECL(            OP_LSR),  //00 0010 1000
+TABDECL(            OP_LSR),  //00 0010 1001
+TABDECL(            OP_LSR),  //00 0010 1010
+TABDECL(            OP_LSR),  //00 0010 1011
+TABDECL(            OP_LSR),  //00 0010 1100
+TABDECL(            OP_LSR),  //00 0010 1101
+TABDECL(            OP_LSR),  //00 0010 1110
+TABDECL(            OP_LSR),  //00 0010 1111
 
-            OP_LSR,  //00 0011 0000
-            OP_LSR,  //00 0011 0001
-            OP_LSR,  //00 0011 0010
-            OP_LSR,  //00 0011 0011
-            OP_LSR,  //00 0011 0100
-            OP_LSR,  //00 0011 0101
-            OP_LSR,  //00 0011 0110
-            OP_LSR,  //00 0011 0111
-            OP_LSR,  //00 0011 1000
-            OP_LSR,  //00 0011 1001
-            OP_LSR,  //00 0011 1010
-            OP_LSR,  //00 0011 1011
-            OP_LSR,  //00 0011 1100
-            OP_LSR,  //00 0011 1101
-            OP_LSR,  //00 0011 1110
-            OP_LSR,  //00 0011 1111
+TABDECL(            OP_LSR),  //00 0011 0000
+TABDECL(            OP_LSR),  //00 0011 0001
+TABDECL(            OP_LSR),  //00 0011 0010
+TABDECL(            OP_LSR),  //00 0011 0011
+TABDECL(            OP_LSR),  //00 0011 0100
+TABDECL(            OP_LSR),  //00 0011 0101
+TABDECL(            OP_LSR),  //00 0011 0110
+TABDECL(            OP_LSR),  //00 0011 0111
+TABDECL(            OP_LSR),  //00 0011 1000
+TABDECL(            OP_LSR),  //00 0011 1001
+TABDECL(            OP_LSR),  //00 0011 1010
+TABDECL(            OP_LSR),  //00 0011 1011
+TABDECL(            OP_LSR),  //00 0011 1100
+TABDECL(            OP_LSR),  //00 0011 1101
+TABDECL(            OP_LSR),  //00 0011 1110
+TABDECL(            OP_LSR),  //00 0011 1111
 
-            OP_ASR_0,  //00 0100 0000
-            OP_ASR,  //00 0100 0001
-            OP_ASR,  //00 0100 0010
-            OP_ASR,  //00 0100 0011
-            OP_ASR,  //00 0100 0100
-            OP_ASR,  //00 0100 0101
-            OP_ASR,  //00 0100 0110
-            OP_ASR,  //00 0100 0111
-            OP_ASR,  //00 0100 1000
-            OP_ASR,  //00 0100 1001
-            OP_ASR,  //00 0100 1010
-            OP_ASR,  //00 0100 1011
-            OP_ASR,  //00 0100 1100
-            OP_ASR,  //00 0100 1101
-            OP_ASR,  //00 0100 1110
-            OP_ASR,  //00 0100 1111
+TABDECL(            OP_ASR_0),  //00 0100 0000
+TABDECL(            OP_ASR),  //00 0100 0001
+TABDECL(            OP_ASR),  //00 0100 0010
+TABDECL(            OP_ASR),  //00 0100 0011
+TABDECL(            OP_ASR),  //00 0100 0100
+TABDECL(            OP_ASR),  //00 0100 0101
+TABDECL(            OP_ASR),  //00 0100 0110
+TABDECL(            OP_ASR),  //00 0100 0111
+TABDECL(            OP_ASR),  //00 0100 1000
+TABDECL(            OP_ASR),  //00 0100 1001
+TABDECL(            OP_ASR),  //00 0100 1010
+TABDECL(            OP_ASR),  //00 0100 1011
+TABDECL(            OP_ASR),  //00 0100 1100
+TABDECL(            OP_ASR),  //00 0100 1101
+TABDECL(            OP_ASR),  //00 0100 1110
+TABDECL(            OP_ASR),  //00 0100 1111
 
-            OP_ASR,  //00 0101 0000
-            OP_ASR,  //00 0101 0001
-            OP_ASR,  //00 0101 0010
-            OP_ASR,  //00 0101 0011
-            OP_ASR,  //00 0101 0100
-            OP_ASR,  //00 0101 0101
-            OP_ASR,  //00 0101 0110
-            OP_ASR,  //00 0101 0111
-            OP_ASR,  //00 0101 1000
-            OP_ASR,  //00 0101 1001
-            OP_ASR,  //00 0101 1010
-            OP_ASR,  //00 0101 1011
-            OP_ASR,  //00 0101 1100
-            OP_ASR,  //00 0101 1101
-            OP_ASR,  //00 0101 1110
-            OP_ASR,  //00 0101 1111
+TABDECL(            OP_ASR),  //00 0101 0000
+TABDECL(            OP_ASR),  //00 0101 0001
+TABDECL(            OP_ASR),  //00 0101 0010
+TABDECL(            OP_ASR),  //00 0101 0011
+TABDECL(            OP_ASR),  //00 0101 0100
+TABDECL(            OP_ASR),  //00 0101 0101
+TABDECL(            OP_ASR),  //00 0101 0110
+TABDECL(            OP_ASR),  //00 0101 0111
+TABDECL(            OP_ASR),  //00 0101 1000
+TABDECL(            OP_ASR),  //00 0101 1001
+TABDECL(            OP_ASR),  //00 0101 1010
+TABDECL(            OP_ASR),  //00 0101 1011
+TABDECL(            OP_ASR),  //00 0101 1100
+TABDECL(            OP_ASR),  //00 0101 1101
+TABDECL(            OP_ASR),  //00 0101 1110
+TABDECL(            OP_ASR),  //00 0101 1111
 
-            OP_ADD_REG,  //00 0110 0000
-            OP_ADD_REG,  //00 0110 0001
-            OP_ADD_REG,  //00 0110 0010
-            OP_ADD_REG,  //00 0110 0011
-            OP_ADD_REG,  //00 0110 0100
-            OP_ADD_REG,  //00 0110 0101
-            OP_ADD_REG,  //00 0110 0110
-            OP_ADD_REG,  //00 0110 0111
-            OP_SUB_REG,  //00 0110 1000
-            OP_SUB_REG,  //00 0110 1001
-            OP_SUB_REG,  //00 0110 1010
-            OP_SUB_REG,  //00 0110 1011
-            OP_SUB_REG,  //00 0110 1100
-            OP_SUB_REG,  //00 0110 1101
-            OP_SUB_REG,  //00 0110 1110
-            OP_SUB_REG,  //00 0110 1111
+TABDECL(            OP_ADD_REG),  //00 0110 0000
+TABDECL(            OP_ADD_REG),  //00 0110 0001
+TABDECL(            OP_ADD_REG),  //00 0110 0010
+TABDECL(            OP_ADD_REG),  //00 0110 0011
+TABDECL(            OP_ADD_REG),  //00 0110 0100
+TABDECL(            OP_ADD_REG),  //00 0110 0101
+TABDECL(            OP_ADD_REG),  //00 0110 0110
+TABDECL(            OP_ADD_REG),  //00 0110 0111
+TABDECL(            OP_SUB_REG),  //00 0110 1000
+TABDECL(            OP_SUB_REG),  //00 0110 1001
+TABDECL(            OP_SUB_REG),  //00 0110 1010
+TABDECL(            OP_SUB_REG),  //00 0110 1011
+TABDECL(            OP_SUB_REG),  //00 0110 1100
+TABDECL(            OP_SUB_REG),  //00 0110 1101
+TABDECL(            OP_SUB_REG),  //00 0110 1110
+TABDECL(            OP_SUB_REG),  //00 0110 1111
 
-            OP_ADD_IMM3,  //00 0111 0000
-            OP_ADD_IMM3,  //00 0111 0001
-            OP_ADD_IMM3,  //00 0111 0010
-            OP_ADD_IMM3,  //00 0111 0011
-            OP_ADD_IMM3,  //00 0111 0100
-            OP_ADD_IMM3,  //00 0111 0101
-            OP_ADD_IMM3,  //00 0111 0110
-            OP_ADD_IMM3,  //00 0111 0111
-            OP_SUB_IMM3,  //00 0111 1000
-            OP_SUB_IMM3,  //00 0111 1001
-            OP_SUB_IMM3,  //00 0111 1010
-            OP_SUB_IMM3,  //00 0111 1011
-            OP_SUB_IMM3,  //00 0111 1100
-            OP_SUB_IMM3,  //00 0111 1101
-            OP_SUB_IMM3,  //00 0111 1110
-            OP_SUB_IMM3,  //00 0111 1111
+TABDECL(            OP_ADD_IMM3),  //00 0111 0000
+TABDECL(            OP_ADD_IMM3),  //00 0111 0001
+TABDECL(            OP_ADD_IMM3),  //00 0111 0010
+TABDECL(            OP_ADD_IMM3),  //00 0111 0011
+TABDECL(            OP_ADD_IMM3),  //00 0111 0100
+TABDECL(            OP_ADD_IMM3),  //00 0111 0101
+TABDECL(            OP_ADD_IMM3),  //00 0111 0110
+TABDECL(            OP_ADD_IMM3),  //00 0111 0111
+TABDECL(            OP_SUB_IMM3),  //00 0111 1000
+TABDECL(            OP_SUB_IMM3),  //00 0111 1001
+TABDECL(            OP_SUB_IMM3),  //00 0111 1010
+TABDECL(            OP_SUB_IMM3),  //00 0111 1011
+TABDECL(            OP_SUB_IMM3),  //00 0111 1100
+TABDECL(            OP_SUB_IMM3),  //00 0111 1101
+TABDECL(            OP_SUB_IMM3),  //00 0111 1110
+TABDECL(            OP_SUB_IMM3),  //00 0111 1111
 
-            OP_MOV_IMM8,  //00 1000 0000
-            OP_MOV_IMM8,  //00 1000 0001
-            OP_MOV_IMM8,  //00 1000 0010
-            OP_MOV_IMM8,  //00 1000 0011
-            OP_MOV_IMM8,  //00 1000 0100
-            OP_MOV_IMM8,  //00 1000 0101
-            OP_MOV_IMM8,  //00 1000 0110
-            OP_MOV_IMM8,  //00 1000 0111
-            OP_MOV_IMM8,  //00 1000 1000
-            OP_MOV_IMM8,  //00 1000 1001
-            OP_MOV_IMM8,  //00 1000 1010
-            OP_MOV_IMM8,  //00 1000 1011
-            OP_MOV_IMM8,  //00 1000 1100
-            OP_MOV_IMM8,  //00 1000 1101
-            OP_MOV_IMM8,  //00 1000 1110
-            OP_MOV_IMM8,  //00 1000 1111
+TABDECL(            OP_MOV_IMM8),  //00 1000 0000
+TABDECL(            OP_MOV_IMM8),  //00 1000 0001
+TABDECL(            OP_MOV_IMM8),  //00 1000 0010
+TABDECL(            OP_MOV_IMM8),  //00 1000 0011
+TABDECL(            OP_MOV_IMM8),  //00 1000 0100
+TABDECL(            OP_MOV_IMM8),  //00 1000 0101
+TABDECL(            OP_MOV_IMM8),  //00 1000 0110
+TABDECL(            OP_MOV_IMM8),  //00 1000 0111
+TABDECL(            OP_MOV_IMM8),  //00 1000 1000
+TABDECL(            OP_MOV_IMM8),  //00 1000 1001
+TABDECL(            OP_MOV_IMM8),  //00 1000 1010
+TABDECL(            OP_MOV_IMM8),  //00 1000 1011
+TABDECL(            OP_MOV_IMM8),  //00 1000 1100
+TABDECL(            OP_MOV_IMM8),  //00 1000 1101
+TABDECL(            OP_MOV_IMM8),  //00 1000 1110
+TABDECL(            OP_MOV_IMM8),  //00 1000 1111
 
-            OP_MOV_IMM8,  //00 1001 0000
-            OP_MOV_IMM8,  //00 1001 0001
-            OP_MOV_IMM8,  //00 1001 0010
-            OP_MOV_IMM8,  //00 1001 0011
-            OP_MOV_IMM8,  //00 1001 0100
-            OP_MOV_IMM8,  //00 1001 0101
-            OP_MOV_IMM8,  //00 1001 0110
-            OP_MOV_IMM8,  //00 1001 0111
-            OP_MOV_IMM8,  //00 1001 1000
-            OP_MOV_IMM8,  //00 1001 1001
-            OP_MOV_IMM8,  //00 1001 1010
-            OP_MOV_IMM8,  //00 1001 1011
-            OP_MOV_IMM8,  //00 1001 1100
-            OP_MOV_IMM8,  //00 1001 1101
-            OP_MOV_IMM8,  //00 1001 1110
-            OP_MOV_IMM8,  //00 1001 1111
+TABDECL(            OP_MOV_IMM8),  //00 1001 0000
+TABDECL(            OP_MOV_IMM8),  //00 1001 0001
+TABDECL(            OP_MOV_IMM8),  //00 1001 0010
+TABDECL(            OP_MOV_IMM8),  //00 1001 0011
+TABDECL(            OP_MOV_IMM8),  //00 1001 0100
+TABDECL(            OP_MOV_IMM8),  //00 1001 0101
+TABDECL(            OP_MOV_IMM8),  //00 1001 0110
+TABDECL(            OP_MOV_IMM8),  //00 1001 0111
+TABDECL(            OP_MOV_IMM8),  //00 1001 1000
+TABDECL(            OP_MOV_IMM8),  //00 1001 1001
+TABDECL(            OP_MOV_IMM8),  //00 1001 1010
+TABDECL(            OP_MOV_IMM8),  //00 1001 1011
+TABDECL(            OP_MOV_IMM8),  //00 1001 1100
+TABDECL(            OP_MOV_IMM8),  //00 1001 1101
+TABDECL(            OP_MOV_IMM8),  //00 1001 1110
+TABDECL(            OP_MOV_IMM8),  //00 1001 1111
 
-            OP_CMP_IMM8,  //00 1010 0000
-            OP_CMP_IMM8,  //00 1010 0001
-            OP_CMP_IMM8,  //00 1010 0010
-            OP_CMP_IMM8,  //00 1010 0011
-            OP_CMP_IMM8,  //00 1010 0100
-            OP_CMP_IMM8,  //00 1010 0101
-            OP_CMP_IMM8,  //00 1010 0110
-            OP_CMP_IMM8,  //00 1010 0111
-            OP_CMP_IMM8,  //00 1010 1000
-            OP_CMP_IMM8,  //00 1010 1001
-            OP_CMP_IMM8,  //00 1010 1010
-            OP_CMP_IMM8,  //00 1010 1011
-            OP_CMP_IMM8,  //00 1010 1100
-            OP_CMP_IMM8,  //00 1010 1101
-            OP_CMP_IMM8,  //00 1010 1110
-            OP_CMP_IMM8,  //00 1010 1111
+TABDECL(            OP_CMP_IMM8),  //00 1010 0000
+TABDECL(            OP_CMP_IMM8),  //00 1010 0001
+TABDECL(            OP_CMP_IMM8),  //00 1010 0010
+TABDECL(            OP_CMP_IMM8),  //00 1010 0011
+TABDECL(            OP_CMP_IMM8),  //00 1010 0100
+TABDECL(            OP_CMP_IMM8),  //00 1010 0101
+TABDECL(            OP_CMP_IMM8),  //00 1010 0110
+TABDECL(            OP_CMP_IMM8),  //00 1010 0111
+TABDECL(            OP_CMP_IMM8),  //00 1010 1000
+TABDECL(            OP_CMP_IMM8),  //00 1010 1001
+TABDECL(            OP_CMP_IMM8),  //00 1010 1010
+TABDECL(            OP_CMP_IMM8),  //00 1010 1011
+TABDECL(            OP_CMP_IMM8),  //00 1010 1100
+TABDECL(            OP_CMP_IMM8),  //00 1010 1101
+TABDECL(            OP_CMP_IMM8),  //00 1010 1110
+TABDECL(            OP_CMP_IMM8),  //00 1010 1111
 
-            OP_CMP_IMM8,  //00 1011 0000
-            OP_CMP_IMM8,  //00 1011 0001
-            OP_CMP_IMM8,  //00 1011 0010
-            OP_CMP_IMM8,  //00 1011 0011
-            OP_CMP_IMM8,  //00 1011 0100
-            OP_CMP_IMM8,  //00 1011 0101
-            OP_CMP_IMM8,  //00 1011 0110
-            OP_CMP_IMM8,  //00 1011 0111
-            OP_CMP_IMM8,  //00 1011 1000
-            OP_CMP_IMM8,  //00 1011 1001
-            OP_CMP_IMM8,  //00 1011 1010
-            OP_CMP_IMM8,  //00 1011 1011
-            OP_CMP_IMM8,  //00 1011 1100
-            OP_CMP_IMM8,  //00 1011 1101
-            OP_CMP_IMM8,  //00 1011 1110
-            OP_CMP_IMM8,  //00 1011 1111
+TABDECL(            OP_CMP_IMM8),  //00 1011 0000
+TABDECL(            OP_CMP_IMM8),  //00 1011 0001
+TABDECL(            OP_CMP_IMM8),  //00 1011 0010
+TABDECL(            OP_CMP_IMM8),  //00 1011 0011
+TABDECL(            OP_CMP_IMM8),  //00 1011 0100
+TABDECL(            OP_CMP_IMM8),  //00 1011 0101
+TABDECL(            OP_CMP_IMM8),  //00 1011 0110
+TABDECL(            OP_CMP_IMM8),  //00 1011 0111
+TABDECL(            OP_CMP_IMM8),  //00 1011 1000
+TABDECL(            OP_CMP_IMM8),  //00 1011 1001
+TABDECL(            OP_CMP_IMM8),  //00 1011 1010
+TABDECL(            OP_CMP_IMM8),  //00 1011 1011
+TABDECL(            OP_CMP_IMM8),  //00 1011 1100
+TABDECL(            OP_CMP_IMM8),  //00 1011 1101
+TABDECL(            OP_CMP_IMM8),  //00 1011 1110
+TABDECL(            OP_CMP_IMM8),  //00 1011 1111
 
-            OP_ADD_IMM8,  //00 1100 0000
-            OP_ADD_IMM8,  //00 1100 0001
-            OP_ADD_IMM8,  //00 1100 0010
-            OP_ADD_IMM8,  //00 1100 0011
-            OP_ADD_IMM8,  //00 1100 0100
-            OP_ADD_IMM8,  //00 1100 0101
-            OP_ADD_IMM8,  //00 1100 0110
-            OP_ADD_IMM8,  //00 1100 0111
-            OP_ADD_IMM8,  //00 1100 1000
-            OP_ADD_IMM8,  //00 1100 1001
-            OP_ADD_IMM8,  //00 1100 1010
-            OP_ADD_IMM8,  //00 1100 1011
-            OP_ADD_IMM8,  //00 1100 1100
-            OP_ADD_IMM8,  //00 1100 1101
-            OP_ADD_IMM8,  //00 1100 1110
-            OP_ADD_IMM8,  //00 1100 1111
+TABDECL(            OP_ADD_IMM8),  //00 1100 0000
+TABDECL(            OP_ADD_IMM8),  //00 1100 0001
+TABDECL(            OP_ADD_IMM8),  //00 1100 0010
+TABDECL(            OP_ADD_IMM8),  //00 1100 0011
+TABDECL(            OP_ADD_IMM8),  //00 1100 0100
+TABDECL(            OP_ADD_IMM8),  //00 1100 0101
+TABDECL(            OP_ADD_IMM8),  //00 1100 0110
+TABDECL(            OP_ADD_IMM8),  //00 1100 0111
+TABDECL(            OP_ADD_IMM8),  //00 1100 1000
+TABDECL(            OP_ADD_IMM8),  //00 1100 1001
+TABDECL(            OP_ADD_IMM8),  //00 1100 1010
+TABDECL(            OP_ADD_IMM8),  //00 1100 1011
+TABDECL(            OP_ADD_IMM8),  //00 1100 1100
+TABDECL(            OP_ADD_IMM8),  //00 1100 1101
+TABDECL(            OP_ADD_IMM8),  //00 1100 1110
+TABDECL(            OP_ADD_IMM8),  //00 1100 1111
 
-            OP_ADD_IMM8,  //00 1101 0000
-            OP_ADD_IMM8,  //00 1101 0001
-            OP_ADD_IMM8,  //00 1101 0010
-            OP_ADD_IMM8,  //00 1101 0011
-            OP_ADD_IMM8,  //00 1101 0100
-            OP_ADD_IMM8,  //00 1101 0101
-            OP_ADD_IMM8,  //00 1101 0110
-            OP_ADD_IMM8,  //00 1101 0111
-            OP_ADD_IMM8,  //00 1101 1000
-            OP_ADD_IMM8,  //00 1101 1001
-            OP_ADD_IMM8,  //00 1101 1010
-            OP_ADD_IMM8,  //00 1101 1011
-            OP_ADD_IMM8,  //00 1101 1100
-            OP_ADD_IMM8,  //00 1101 1101
-            OP_ADD_IMM8,  //00 1101 1110
-            OP_ADD_IMM8,  //00 1101 1111
+TABDECL(            OP_ADD_IMM8),  //00 1101 0000
+TABDECL(            OP_ADD_IMM8),  //00 1101 0001
+TABDECL(            OP_ADD_IMM8),  //00 1101 0010
+TABDECL(            OP_ADD_IMM8),  //00 1101 0011
+TABDECL(            OP_ADD_IMM8),  //00 1101 0100
+TABDECL(            OP_ADD_IMM8),  //00 1101 0101
+TABDECL(            OP_ADD_IMM8),  //00 1101 0110
+TABDECL(            OP_ADD_IMM8),  //00 1101 0111
+TABDECL(            OP_ADD_IMM8),  //00 1101 1000
+TABDECL(            OP_ADD_IMM8),  //00 1101 1001
+TABDECL(            OP_ADD_IMM8),  //00 1101 1010
+TABDECL(            OP_ADD_IMM8),  //00 1101 1011
+TABDECL(            OP_ADD_IMM8),  //00 1101 1100
+TABDECL(            OP_ADD_IMM8),  //00 1101 1101
+TABDECL(            OP_ADD_IMM8),  //00 1101 1110
+TABDECL(            OP_ADD_IMM8),  //00 1101 1111
 
-            OP_SUB_IMM8,  //00 1110 0000
-            OP_SUB_IMM8,  //00 1110 0001
-            OP_SUB_IMM8,  //00 1110 0010
-            OP_SUB_IMM8,  //00 1110 0011
-            OP_SUB_IMM8,  //00 1110 0100
-            OP_SUB_IMM8,  //00 1110 0101
-            OP_SUB_IMM8,  //00 1110 0110
-            OP_SUB_IMM8,  //00 1110 0111
-            OP_SUB_IMM8,  //00 1110 1000
-            OP_SUB_IMM8,  //00 1110 1001
-            OP_SUB_IMM8,  //00 1110 1010
-            OP_SUB_IMM8,  //00 1110 1011
-            OP_SUB_IMM8,  //00 1110 1100
-            OP_SUB_IMM8,  //00 1110 1101
-            OP_SUB_IMM8,  //00 1110 1110
-            OP_SUB_IMM8,  //00 1110 1111
+TABDECL(            OP_SUB_IMM8),  //00 1110 0000
+TABDECL(            OP_SUB_IMM8),  //00 1110 0001
+TABDECL(            OP_SUB_IMM8),  //00 1110 0010
+TABDECL(            OP_SUB_IMM8),  //00 1110 0011
+TABDECL(            OP_SUB_IMM8),  //00 1110 0100
+TABDECL(            OP_SUB_IMM8),  //00 1110 0101
+TABDECL(            OP_SUB_IMM8),  //00 1110 0110
+TABDECL(            OP_SUB_IMM8),  //00 1110 0111
+TABDECL(            OP_SUB_IMM8),  //00 1110 1000
+TABDECL(            OP_SUB_IMM8),  //00 1110 1001
+TABDECL(            OP_SUB_IMM8),  //00 1110 1010
+TABDECL(            OP_SUB_IMM8),  //00 1110 1011
+TABDECL(            OP_SUB_IMM8),  //00 1110 1100
+TABDECL(            OP_SUB_IMM8),  //00 1110 1101
+TABDECL(            OP_SUB_IMM8),  //00 1110 1110
+TABDECL(            OP_SUB_IMM8),  //00 1110 1111
 
-            OP_SUB_IMM8,  //00 1111 0000
-            OP_SUB_IMM8,  //00 1111 0001
-            OP_SUB_IMM8,  //00 1111 0010
-            OP_SUB_IMM8,  //00 1111 0011
-            OP_SUB_IMM8,  //00 1111 0100
-            OP_SUB_IMM8,  //00 1111 0101
-            OP_SUB_IMM8,  //00 1111 0110
-            OP_SUB_IMM8,  //00 1111 0111
-            OP_SUB_IMM8,  //00 1111 1000
-            OP_SUB_IMM8,  //00 1111 1001
-            OP_SUB_IMM8,  //00 1111 1010
-            OP_SUB_IMM8,  //00 1111 1011
-            OP_SUB_IMM8,  //00 1111 1100
-            OP_SUB_IMM8,  //00 1111 1101
-            OP_SUB_IMM8,  //00 1111 1110
-            OP_SUB_IMM8,  //00 1111 1111
+TABDECL(            OP_SUB_IMM8),  //00 1111 0000
+TABDECL(            OP_SUB_IMM8),  //00 1111 0001
+TABDECL(            OP_SUB_IMM8),  //00 1111 0010
+TABDECL(            OP_SUB_IMM8),  //00 1111 0011
+TABDECL(            OP_SUB_IMM8),  //00 1111 0100
+TABDECL(            OP_SUB_IMM8),  //00 1111 0101
+TABDECL(            OP_SUB_IMM8),  //00 1111 0110
+TABDECL(            OP_SUB_IMM8),  //00 1111 0111
+TABDECL(            OP_SUB_IMM8),  //00 1111 1000
+TABDECL(            OP_SUB_IMM8),  //00 1111 1001
+TABDECL(            OP_SUB_IMM8),  //00 1111 1010
+TABDECL(            OP_SUB_IMM8),  //00 1111 1011
+TABDECL(            OP_SUB_IMM8),  //00 1111 1100
+TABDECL(            OP_SUB_IMM8),  //00 1111 1101
+TABDECL(            OP_SUB_IMM8),  //00 1111 1110
+TABDECL(            OP_SUB_IMM8),  //00 1111 1111
 
-            OP_AND,  //01 0000 0000
-            OP_EOR,  //01 0000 0001
-            OP_LSL_REG,  //01 0000 0010
-            OP_LSR_REG,  //01 0000 0011
-            OP_ASR_REG,  //01 0000 0100
-            OP_ADC_REG,  //01 0000 0101
-            OP_SBC_REG,  //01 0000 0110
-            OP_ROR_REG,  //01 0000 0111
-            OP_TST,  //01 0000 1000
-            OP_NEG,  //01 0000 1001
-            OP_CMP,  //01 0000 1010
-            OP_CMN,  //01 0000 1011
-            OP_ORR,  //01 0000 1100
-            OP_MUL_REG,  //01 0000 1101
-            OP_BIC,  //01 0000 1110
-            OP_MVN,  //01 0000 1111
+TABDECL(            OP_AND),  //01 0000 0000
+TABDECL(            OP_EOR),  //01 0000 0001
+TABDECL(            OP_LSL_REG),  //01 0000 0010
+TABDECL(            OP_LSR_REG),  //01 0000 0011
+TABDECL(            OP_ASR_REG),  //01 0000 0100
+TABDECL(            OP_ADC_REG),  //01 0000 0101
+TABDECL(            OP_SBC_REG),  //01 0000 0110
+TABDECL(            OP_ROR_REG),  //01 0000 0111
+TABDECL(            OP_TST),  //01 0000 1000
+TABDECL(            OP_NEG),  //01 0000 1001
+TABDECL(            OP_CMP),  //01 0000 1010
+TABDECL(            OP_CMN),  //01 0000 1011
+TABDECL(            OP_ORR),  //01 0000 1100
+TABDECL(            OP_MUL_REG),  //01 0000 1101
+TABDECL(            OP_BIC),  //01 0000 1110
+TABDECL(            OP_MVN),  //01 0000 1111
 
-            OP_ADD_SPE,  //01 0001 0000
-            OP_ADD_SPE,  //01 0001 0001
-            OP_ADD_SPE,  //01 0001 0010
-            OP_ADD_SPE,  //01 0001 0011
-            OP_CMP_SPE,  //01 0001 0100
-            OP_CMP_SPE,  //01 0001 0101
-            OP_CMP_SPE,  //01 0001 0110
-            OP_CMP_SPE,  //01 0001 0111
-            OP_MOV_SPE,  //01 0001 1000
-            OP_MOV_SPE,  //01 0001 1001
-            OP_MOV_SPE,  //01 0001 1010
-            OP_MOV_SPE,  //01 0001 1011
-            OP_BX_THUMB,  //01 0001 1100
-            OP_BX_THUMB,  //01 0001 1101
-            OP_BLX_THUMB,  //01 0001 1110
-            OP_BLX_THUMB,  //01 0001 1111 
+TABDECL(            OP_ADD_SPE),  //01 0001 0000
+TABDECL(            OP_ADD_SPE),  //01 0001 0001
+TABDECL(            OP_ADD_SPE),  //01 0001 0010
+TABDECL(            OP_ADD_SPE),  //01 0001 0011
+TABDECL(            OP_CMP_SPE),  //01 0001 0100
+TABDECL(            OP_CMP_SPE),  //01 0001 0101
+TABDECL(            OP_CMP_SPE),  //01 0001 0110
+TABDECL(            OP_CMP_SPE),  //01 0001 0111
+TABDECL(            OP_MOV_SPE),  //01 0001 1000
+TABDECL(            OP_MOV_SPE),  //01 0001 1001
+TABDECL(            OP_MOV_SPE),  //01 0001 1010
+TABDECL(            OP_MOV_SPE),  //01 0001 1011
+TABDECL(            OP_BX_THUMB),  //01 0001 1100
+TABDECL(            OP_BX_THUMB),  //01 0001 1101
+TABDECL(            OP_BLX_THUMB),  //01 0001 1110
+TABDECL(            OP_BLX_THUMB),  //01 0001 1111 
 
-            OP_LDR_PCREL,  //01 0010 0000
-            OP_LDR_PCREL,  //01 0010 0001
-            OP_LDR_PCREL,  //01 0010 0010
-            OP_LDR_PCREL,  //01 0010 0011
-            OP_LDR_PCREL,  //01 0010 0100
-            OP_LDR_PCREL,  //01 0010 0101
-            OP_LDR_PCREL,  //01 0010 0110
-            OP_LDR_PCREL,  //01 0010 0111
-            OP_LDR_PCREL,  //01 0010 1000
-            OP_LDR_PCREL,  //01 0010 1001
-            OP_LDR_PCREL,  //01 0010 1010
-            OP_LDR_PCREL,  //01 0010 1011
-            OP_LDR_PCREL,  //01 0010 1100
-            OP_LDR_PCREL,  //01 0010 1101
-            OP_LDR_PCREL,  //01 0010 1110
-            OP_LDR_PCREL,  //01 0010 1111
+TABDECL(            OP_LDR_PCREL),  //01 0010 0000
+TABDECL(            OP_LDR_PCREL),  //01 0010 0001
+TABDECL(            OP_LDR_PCREL),  //01 0010 0010
+TABDECL(            OP_LDR_PCREL),  //01 0010 0011
+TABDECL(            OP_LDR_PCREL),  //01 0010 0100
+TABDECL(            OP_LDR_PCREL),  //01 0010 0101
+TABDECL(            OP_LDR_PCREL),  //01 0010 0110
+TABDECL(            OP_LDR_PCREL),  //01 0010 0111
+TABDECL(            OP_LDR_PCREL),  //01 0010 1000
+TABDECL(            OP_LDR_PCREL),  //01 0010 1001
+TABDECL(            OP_LDR_PCREL),  //01 0010 1010
+TABDECL(            OP_LDR_PCREL),  //01 0010 1011
+TABDECL(            OP_LDR_PCREL),  //01 0010 1100
+TABDECL(            OP_LDR_PCREL),  //01 0010 1101
+TABDECL(            OP_LDR_PCREL),  //01 0010 1110
+TABDECL(            OP_LDR_PCREL),  //01 0010 1111
 
-            OP_LDR_PCREL,  //01 0011 0000
-            OP_LDR_PCREL,  //01 0011 0001
-            OP_LDR_PCREL,  //01 0011 0010
-            OP_LDR_PCREL,  //01 0011 0011
-            OP_LDR_PCREL,  //01 0011 0100
-            OP_LDR_PCREL,  //01 0011 0101
-            OP_LDR_PCREL,  //01 0011 0110
-            OP_LDR_PCREL,  //01 0011 0111
-            OP_LDR_PCREL,  //01 0011 1000
-            OP_LDR_PCREL,  //01 0011 1001
-            OP_LDR_PCREL,  //01 0011 1010
-            OP_LDR_PCREL,  //01 0011 1011
-            OP_LDR_PCREL,  //01 0011 1100
-            OP_LDR_PCREL,  //01 0011 1101
-            OP_LDR_PCREL,  //01 0011 1110
-            OP_LDR_PCREL,  //01 0011 1111
+TABDECL(            OP_LDR_PCREL),  //01 0011 0000
+TABDECL(            OP_LDR_PCREL),  //01 0011 0001
+TABDECL(            OP_LDR_PCREL),  //01 0011 0010
+TABDECL(            OP_LDR_PCREL),  //01 0011 0011
+TABDECL(            OP_LDR_PCREL),  //01 0011 0100
+TABDECL(            OP_LDR_PCREL),  //01 0011 0101
+TABDECL(            OP_LDR_PCREL),  //01 0011 0110
+TABDECL(            OP_LDR_PCREL),  //01 0011 0111
+TABDECL(            OP_LDR_PCREL),  //01 0011 1000
+TABDECL(            OP_LDR_PCREL),  //01 0011 1001
+TABDECL(            OP_LDR_PCREL),  //01 0011 1010
+TABDECL(            OP_LDR_PCREL),  //01 0011 1011
+TABDECL(            OP_LDR_PCREL),  //01 0011 1100
+TABDECL(            OP_LDR_PCREL),  //01 0011 1101
+TABDECL(            OP_LDR_PCREL),  //01 0011 1110
+TABDECL(            OP_LDR_PCREL),  //01 0011 1111
 
-            OP_STR_REG_OFF,  //01 0100 0000
-            OP_STR_REG_OFF,  //01 0100 0001
-            OP_STR_REG_OFF,  //01 0100 0010
-            OP_STR_REG_OFF,  //01 0100 0011
-            OP_STR_REG_OFF,  //01 0100 0100
-            OP_STR_REG_OFF,  //01 0100 0101
-            OP_STR_REG_OFF,  //01 0100 0110
-            OP_STR_REG_OFF,  //01 0100 0111
-            OP_STRH_REG_OFF,  //01 0100 1000
-            OP_STRH_REG_OFF,  //01 0100 1001
-            OP_STRH_REG_OFF,  //01 0100 1010
-            OP_STRH_REG_OFF,  //01 0100 1011
-            OP_STRH_REG_OFF,  //01 0100 1100
-            OP_STRH_REG_OFF,  //01 0100 1101
-            OP_STRH_REG_OFF,  //01 0100 1110
-            OP_STRH_REG_OFF,  //01 0100 1111
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0000
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0001
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0010
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0011
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0100
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0101
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0110
+TABDECL(            OP_STR_REG_OFF),  //01 0100 0111
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1000
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1001
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1010
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1011
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1100
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1101
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1110
+TABDECL(            OP_STRH_REG_OFF),  //01 0100 1111
 
-            OP_STRB_REG_OFF,  //01 0101 0000
-            OP_STRB_REG_OFF,  //01 0101 0001
-            OP_STRB_REG_OFF,  //01 0101 0010
-            OP_STRB_REG_OFF,  //01 0101 0011
-            OP_STRB_REG_OFF,  //01 0101 0100
-            OP_STRB_REG_OFF,  //01 0101 0101
-            OP_STRB_REG_OFF,  //01 0101 0110
-            OP_STRB_REG_OFF,  //01 0101 0111
-            OP_LDRSB_REG_OFF,  //01 0101 1000
-            OP_LDRSB_REG_OFF,  //01 0101 1001
-            OP_LDRSB_REG_OFF,  //01 0101 1010
-            OP_LDRSB_REG_OFF,  //01 0101 1011
-            OP_LDRSB_REG_OFF,  //01 0101 1100
-            OP_LDRSB_REG_OFF,  //01 0101 1101
-            OP_LDRSB_REG_OFF,  //01 0101 1110
-            OP_LDRSB_REG_OFF,  //01 0101 1111
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0000
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0001
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0010
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0011
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0100
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0101
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0110
+TABDECL(            OP_STRB_REG_OFF),  //01 0101 0111
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1000
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1001
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1010
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1011
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1100
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1101
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1110
+TABDECL(            OP_LDRSB_REG_OFF),  //01 0101 1111
 
-            OP_LDR_REG_OFF,  //01 0110 0000
-            OP_LDR_REG_OFF,  //01 0110 0001
-            OP_LDR_REG_OFF,  //01 0110 0010
-            OP_LDR_REG_OFF,  //01 0110 0011
-            OP_LDR_REG_OFF,  //01 0110 0100
-            OP_LDR_REG_OFF,  //01 0110 0101
-            OP_LDR_REG_OFF,  //01 0110 0110
-            OP_LDR_REG_OFF,  //01 0110 0111
-            OP_LDRH_REG_OFF,  //01 0110 1000
-            OP_LDRH_REG_OFF,  //01 0110 1001
-            OP_LDRH_REG_OFF,  //01 0110 1010
-            OP_LDRH_REG_OFF,  //01 0110 1011
-            OP_LDRH_REG_OFF,  //01 0110 1100
-            OP_LDRH_REG_OFF,  //01 0110 1101
-            OP_LDRH_REG_OFF,  //01 0110 1110
-            OP_LDRH_REG_OFF,  //01 0110 1111
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0000
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0001
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0010
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0011
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0100
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0101
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0110
+TABDECL(            OP_LDR_REG_OFF),  //01 0110 0111
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1000
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1001
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1010
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1011
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1100
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1101
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1110
+TABDECL(            OP_LDRH_REG_OFF),  //01 0110 1111
 
-            OP_LDRB_REG_OFF,  //01 0111 0000
-            OP_LDRB_REG_OFF,  //01 0111 0001
-            OP_LDRB_REG_OFF,  //01 0111 0010
-            OP_LDRB_REG_OFF,  //01 0111 0011
-            OP_LDRB_REG_OFF,  //01 0111 0100
-            OP_LDRB_REG_OFF,  //01 0111 0101
-            OP_LDRB_REG_OFF,  //01 0111 0110
-            OP_LDRB_REG_OFF,  //01 0111 0111
-            OP_LDRSH_REG_OFF,  //01 0111 1000
-            OP_LDRSH_REG_OFF,  //01 0111 1001
-            OP_LDRSH_REG_OFF,  //01 0111 1010
-            OP_LDRSH_REG_OFF,  //01 0111 1011
-            OP_LDRSH_REG_OFF,  //01 0111 1100
-            OP_LDRSH_REG_OFF,  //01 0111 1101
-            OP_LDRSH_REG_OFF,  //01 0111 1110
-            OP_LDRSH_REG_OFF,  //01 0111 1111
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0000
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0001
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0010
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0011
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0100
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0101
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0110
+TABDECL(            OP_LDRB_REG_OFF),  //01 0111 0111
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1000
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1001
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1010
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1011
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1100
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1101
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1110
+TABDECL(            OP_LDRSH_REG_OFF),  //01 0111 1111
 
-            OP_STR_IMM_OFF,  //01 1000 0000
-            OP_STR_IMM_OFF,  //01 1000 0001
-            OP_STR_IMM_OFF,  //01 1000 0010
-            OP_STR_IMM_OFF,  //01 1000 0011
-            OP_STR_IMM_OFF,  //01 1000 0100
-            OP_STR_IMM_OFF,  //01 1000 0101
-            OP_STR_IMM_OFF,  //01 1000 0110
-            OP_STR_IMM_OFF,  //01 1000 0111
-            OP_STR_IMM_OFF,  //01 1000 1000
-            OP_STR_IMM_OFF,  //01 1000 1001
-            OP_STR_IMM_OFF,  //01 1000 1010
-            OP_STR_IMM_OFF,  //01 1000 1011
-            OP_STR_IMM_OFF,  //01 1000 1100
-            OP_STR_IMM_OFF,  //01 1000 1101
-            OP_STR_IMM_OFF,  //01 1000 1110
-            OP_STR_IMM_OFF,  //01 1000 1111
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0000
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0001
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0010
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0011
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0100
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0101
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0110
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 0111
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1000
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1001
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1010
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1011
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1100
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1101
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1110
+TABDECL(            OP_STR_IMM_OFF),  //01 1000 1111
 
-            OP_STR_IMM_OFF,  //01 1001 0000
-            OP_STR_IMM_OFF,  //01 1001 0001
-            OP_STR_IMM_OFF,  //01 1001 0010
-            OP_STR_IMM_OFF,  //01 1001 0011
-            OP_STR_IMM_OFF,  //01 1001 0100
-            OP_STR_IMM_OFF,  //01 1001 0101
-            OP_STR_IMM_OFF,  //01 1001 0110
-            OP_STR_IMM_OFF,  //01 1001 0111
-            OP_STR_IMM_OFF,  //01 1001 1000
-            OP_STR_IMM_OFF,  //01 1001 1001
-            OP_STR_IMM_OFF,  //01 1001 1010
-            OP_STR_IMM_OFF,  //01 1001 1011
-            OP_STR_IMM_OFF,  //01 1001 1100
-            OP_STR_IMM_OFF,  //01 1001 1101
-            OP_STR_IMM_OFF,  //01 1001 1110
-            OP_STR_IMM_OFF,  //01 1001 1111
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0000
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0001
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0010
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0011
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0100
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0101
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0110
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 0111
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1000
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1001
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1010
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1011
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1100
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1101
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1110
+TABDECL(            OP_STR_IMM_OFF),  //01 1001 1111
 
-            OP_LDR_IMM_OFF,  //01 1010 0000
-            OP_LDR_IMM_OFF,  //01 1010 0001
-            OP_LDR_IMM_OFF,  //01 1010 0010
-            OP_LDR_IMM_OFF,  //01 1010 0011
-            OP_LDR_IMM_OFF,  //01 1010 0100
-            OP_LDR_IMM_OFF,  //01 1010 0101
-            OP_LDR_IMM_OFF,  //01 1010 0110
-            OP_LDR_IMM_OFF,  //01 1010 0111
-            OP_LDR_IMM_OFF,  //01 1010 1000
-            OP_LDR_IMM_OFF,  //01 1010 1001
-            OP_LDR_IMM_OFF,  //01 1010 1010
-            OP_LDR_IMM_OFF,  //01 1010 1011
-            OP_LDR_IMM_OFF,  //01 1010 1100
-            OP_LDR_IMM_OFF,  //01 1010 1101
-            OP_LDR_IMM_OFF,  //01 1010 1110
-            OP_LDR_IMM_OFF,  //01 1010 1111
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0000
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0001
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0010
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0011
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0100
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0101
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0110
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 0111
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1000
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1001
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1010
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1011
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1100
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1101
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1110
+TABDECL(            OP_LDR_IMM_OFF),  //01 1010 1111
             
-            OP_LDR_IMM_OFF,  //01 1011 0000
-            OP_LDR_IMM_OFF,  //01 1011 0001
-            OP_LDR_IMM_OFF,  //01 1011 0010
-            OP_LDR_IMM_OFF,  //01 1011 0011
-            OP_LDR_IMM_OFF,  //01 1011 0100
-            OP_LDR_IMM_OFF,  //01 1011 0101
-            OP_LDR_IMM_OFF,  //01 1011 0110
-            OP_LDR_IMM_OFF,  //01 1011 0111
-            OP_LDR_IMM_OFF,  //01 1011 1000
-            OP_LDR_IMM_OFF,  //01 1011 1001
-            OP_LDR_IMM_OFF,  //01 1011 1010
-            OP_LDR_IMM_OFF,  //01 1011 1011
-            OP_LDR_IMM_OFF,  //01 1011 1100
-            OP_LDR_IMM_OFF,  //01 1011 1101
-            OP_LDR_IMM_OFF,  //01 1011 1110
-            OP_LDR_IMM_OFF,  //01 1011 1111
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0000
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0001
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0010
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0011
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0100
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0101
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0110
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 0111
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1000
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1001
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1010
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1011
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1100
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1101
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1110
+TABDECL(            OP_LDR_IMM_OFF),  //01 1011 1111
 
-            OP_STRB_IMM_OFF,  //01 1100 0000
-            OP_STRB_IMM_OFF,  //01 1100 0001
-            OP_STRB_IMM_OFF,  //01 1100 0010
-            OP_STRB_IMM_OFF,  //01 1100 0011
-            OP_STRB_IMM_OFF,  //01 1100 0100
-            OP_STRB_IMM_OFF,  //01 1100 0101
-            OP_STRB_IMM_OFF,  //01 1100 0110
-            OP_STRB_IMM_OFF,  //01 1100 0111
-            OP_STRB_IMM_OFF,  //01 1100 1000
-            OP_STRB_IMM_OFF,  //01 1100 1001
-            OP_STRB_IMM_OFF,  //01 1100 1010
-            OP_STRB_IMM_OFF,  //01 1100 1011
-            OP_STRB_IMM_OFF,  //01 1100 1100
-            OP_STRB_IMM_OFF,  //01 1100 1101
-            OP_STRB_IMM_OFF,  //01 1100 1110
-            OP_STRB_IMM_OFF,  //01 1100 1111
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0000
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0001
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0010
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0011
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0100
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0101
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0110
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 0111
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1000
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1001
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1010
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1011
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1100
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1101
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1110
+TABDECL(            OP_STRB_IMM_OFF),  //01 1100 1111
 
-            OP_STRB_IMM_OFF,  //01 1101 0000
-            OP_STRB_IMM_OFF,  //01 1101 0001
-            OP_STRB_IMM_OFF,  //01 1101 0010
-            OP_STRB_IMM_OFF,  //01 1101 0011
-            OP_STRB_IMM_OFF,  //01 1101 0100
-            OP_STRB_IMM_OFF,  //01 1101 0101
-            OP_STRB_IMM_OFF,  //01 1101 0110
-            OP_STRB_IMM_OFF,  //01 1101 0111
-            OP_STRB_IMM_OFF,  //01 1101 1000
-            OP_STRB_IMM_OFF,  //01 1101 1001
-            OP_STRB_IMM_OFF,  //01 1101 1010
-            OP_STRB_IMM_OFF,  //01 1101 1011
-            OP_STRB_IMM_OFF,  //01 1101 1100
-            OP_STRB_IMM_OFF,  //01 1101 1101
-            OP_STRB_IMM_OFF,  //01 1101 1110
-            OP_STRB_IMM_OFF,  //01 1101 1111
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0000
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0001
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0010
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0011
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0100
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0101
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0110
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 0111
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1000
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1001
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1010
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1011
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1100
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1101
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1110
+TABDECL(            OP_STRB_IMM_OFF),  //01 1101 1111
 
-            OP_LDRB_IMM_OFF,  //01 1110 0000
-            OP_LDRB_IMM_OFF,  //01 1110 0001
-            OP_LDRB_IMM_OFF,  //01 1110 0010
-            OP_LDRB_IMM_OFF,  //01 1110 0011
-            OP_LDRB_IMM_OFF,  //01 1110 0100
-            OP_LDRB_IMM_OFF,  //01 1110 0101
-            OP_LDRB_IMM_OFF,  //01 1110 0110
-            OP_LDRB_IMM_OFF,  //01 1110 0111
-            OP_LDRB_IMM_OFF,  //01 1110 1000
-            OP_LDRB_IMM_OFF,  //01 1110 1001
-            OP_LDRB_IMM_OFF,  //01 1110 1010
-            OP_LDRB_IMM_OFF,  //01 1110 1011
-            OP_LDRB_IMM_OFF,  //01 1110 1100
-            OP_LDRB_IMM_OFF,  //01 1110 1101
-            OP_LDRB_IMM_OFF,  //01 1110 1110
-            OP_LDRB_IMM_OFF,  //01 1110 1111
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0000
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0001
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0010
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0011
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0100
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0101
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0110
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 0111
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1000
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1001
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1010
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1011
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1100
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1101
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1110
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1110 1111
 
-            OP_LDRB_IMM_OFF,  //01 1111 0000
-            OP_LDRB_IMM_OFF,  //01 1111 0001
-            OP_LDRB_IMM_OFF,  //01 1111 0010
-            OP_LDRB_IMM_OFF,  //01 1111 0011
-            OP_LDRB_IMM_OFF,  //01 1111 0100
-            OP_LDRB_IMM_OFF,  //01 1111 0101
-            OP_LDRB_IMM_OFF,  //01 1111 0110
-            OP_LDRB_IMM_OFF,  //01 1111 0111
-            OP_LDRB_IMM_OFF,  //01 1111 1000
-            OP_LDRB_IMM_OFF,  //01 1111 1001
-            OP_LDRB_IMM_OFF,  //01 1111 1010
-            OP_LDRB_IMM_OFF,  //01 1111 1011
-            OP_LDRB_IMM_OFF,  //01 1111 1100
-            OP_LDRB_IMM_OFF,  //01 1111 1101
-            OP_LDRB_IMM_OFF,  //01 1111 1110
-            OP_LDRB_IMM_OFF,  //01 1111 1111
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0000
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0001
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0010
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0011
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0100
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0101
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0110
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 0111
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1000
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1001
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1010
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1011
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1100
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1101
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1110
+TABDECL(            OP_LDRB_IMM_OFF),  //01 1111 1111
 
-            OP_STRH_IMM_OFF,  //10 0000 0000
-            OP_STRH_IMM_OFF,  //10 0000 0001
-            OP_STRH_IMM_OFF,  //10 0000 0010
-            OP_STRH_IMM_OFF,  //10 0000 0011
-            OP_STRH_IMM_OFF,  //10 0000 0100
-            OP_STRH_IMM_OFF,  //10 0000 0101
-            OP_STRH_IMM_OFF,  //10 0000 0110
-            OP_STRH_IMM_OFF,  //10 0000 0111
-            OP_STRH_IMM_OFF,  //10 0000 1000
-            OP_STRH_IMM_OFF,  //10 0000 1001
-            OP_STRH_IMM_OFF,  //10 0000 1010
-            OP_STRH_IMM_OFF,  //10 0000 1011
-            OP_STRH_IMM_OFF,  //10 0000 1100
-            OP_STRH_IMM_OFF,  //10 0000 1101
-            OP_STRH_IMM_OFF,  //10 0000 1110
-            OP_STRH_IMM_OFF,  //10 0000 1111
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0000
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0001
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0010
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0011
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0100
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0101
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0110
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 0111
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1000
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1001
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1010
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1011
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1100
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1101
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1110
+TABDECL(            OP_STRH_IMM_OFF),  //10 0000 1111
 
-            OP_STRH_IMM_OFF,  //10 0001 0000
-            OP_STRH_IMM_OFF,  //10 0001 0001
-            OP_STRH_IMM_OFF,  //10 0001 0010
-            OP_STRH_IMM_OFF,  //10 0001 0011
-            OP_STRH_IMM_OFF,  //10 0001 0100
-            OP_STRH_IMM_OFF,  //10 0001 0101
-            OP_STRH_IMM_OFF,  //10 0001 0110
-            OP_STRH_IMM_OFF,  //10 0001 0111
-            OP_STRH_IMM_OFF,  //10 0001 1000
-            OP_STRH_IMM_OFF,  //10 0001 1001
-            OP_STRH_IMM_OFF,  //10 0001 1010
-            OP_STRH_IMM_OFF,  //10 0001 1011
-            OP_STRH_IMM_OFF,  //10 0001 1100
-            OP_STRH_IMM_OFF,  //10 0001 1101
-            OP_STRH_IMM_OFF,  //10 0001 1110
-            OP_STRH_IMM_OFF,  //10 0001 1111
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0000
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0001
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0010
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0011
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0100
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0101
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0110
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 0111
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1000
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1001
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1010
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1011
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1100
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1101
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1110
+TABDECL(            OP_STRH_IMM_OFF),  //10 0001 1111
 
-            OP_LDRH_IMM_OFF,  //10 0010 0000
-            OP_LDRH_IMM_OFF,  //10 0010 0001
-            OP_LDRH_IMM_OFF,  //10 0010 0010
-            OP_LDRH_IMM_OFF,  //10 0010 0011
-            OP_LDRH_IMM_OFF,  //10 0010 0100
-            OP_LDRH_IMM_OFF,  //10 0010 0101
-            OP_LDRH_IMM_OFF,  //10 0010 0110
-            OP_LDRH_IMM_OFF,  //10 0010 0111
-            OP_LDRH_IMM_OFF,  //10 0010 1000
-            OP_LDRH_IMM_OFF,  //10 0010 1001
-            OP_LDRH_IMM_OFF,  //10 0010 1010
-            OP_LDRH_IMM_OFF,  //10 0010 1011
-            OP_LDRH_IMM_OFF,  //10 0010 1100
-            OP_LDRH_IMM_OFF,  //10 0010 1101
-            OP_LDRH_IMM_OFF,  //10 0010 1110
-            OP_LDRH_IMM_OFF,  //10 0010 1111
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0000
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0001
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0010
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0011
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0100
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0101
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0110
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 0111
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1000
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1001
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1010
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1011
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1100
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1101
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1110
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0010 1111
 
-            OP_LDRH_IMM_OFF,  //10 0011 0000
-            OP_LDRH_IMM_OFF,  //10 0011 0001
-            OP_LDRH_IMM_OFF,  //10 0011 0010
-            OP_LDRH_IMM_OFF,  //10 0011 0011
-            OP_LDRH_IMM_OFF,  //10 0011 0100
-            OP_LDRH_IMM_OFF,  //10 0011 0101
-            OP_LDRH_IMM_OFF,  //10 0011 0110
-            OP_LDRH_IMM_OFF,  //10 0011 0111
-            OP_LDRH_IMM_OFF,  //10 0011 1000
-            OP_LDRH_IMM_OFF,  //10 0011 1001
-            OP_LDRH_IMM_OFF,  //10 0011 1010
-            OP_LDRH_IMM_OFF,  //10 0011 1011
-            OP_LDRH_IMM_OFF,  //10 0011 1100
-            OP_LDRH_IMM_OFF,  //10 0011 1101
-            OP_LDRH_IMM_OFF,  //10 0011 1110
-            OP_LDRH_IMM_OFF,  //10 0011 1111
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0000
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0001
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0010
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0011
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0100
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0101
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0110
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 0111
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1000
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1001
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1010
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1011
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1100
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1101
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1110
+TABDECL(            OP_LDRH_IMM_OFF),  //10 0011 1111
 
-            OP_STR_SPREL,  //10 0100 0000
-            OP_STR_SPREL,  //10 0100 0001
-            OP_STR_SPREL,  //10 0100 0010
-            OP_STR_SPREL,  //10 0100 0011
-            OP_STR_SPREL,  //10 0100 0100
-            OP_STR_SPREL,  //10 0100 0101
-            OP_STR_SPREL,  //10 0100 0110
-            OP_STR_SPREL,  //10 0100 0111
-            OP_STR_SPREL,  //10 0100 1000
-            OP_STR_SPREL,  //10 0100 1001
-            OP_STR_SPREL,  //10 0100 1010
-            OP_STR_SPREL,  //10 0100 1011
-            OP_STR_SPREL,  //10 0100 1100
-            OP_STR_SPREL,  //10 0100 1101
-            OP_STR_SPREL,  //10 0100 1110
-            OP_STR_SPREL,  //10 0100 1111
+TABDECL(            OP_STR_SPREL),  //10 0100 0000
+TABDECL(            OP_STR_SPREL),  //10 0100 0001
+TABDECL(            OP_STR_SPREL),  //10 0100 0010
+TABDECL(            OP_STR_SPREL),  //10 0100 0011
+TABDECL(            OP_STR_SPREL),  //10 0100 0100
+TABDECL(            OP_STR_SPREL),  //10 0100 0101
+TABDECL(            OP_STR_SPREL),  //10 0100 0110
+TABDECL(            OP_STR_SPREL),  //10 0100 0111
+TABDECL(            OP_STR_SPREL),  //10 0100 1000
+TABDECL(            OP_STR_SPREL),  //10 0100 1001
+TABDECL(            OP_STR_SPREL),  //10 0100 1010
+TABDECL(            OP_STR_SPREL),  //10 0100 1011
+TABDECL(            OP_STR_SPREL),  //10 0100 1100
+TABDECL(            OP_STR_SPREL),  //10 0100 1101
+TABDECL(            OP_STR_SPREL),  //10 0100 1110
+TABDECL(            OP_STR_SPREL),  //10 0100 1111
 
-            OP_STR_SPREL,  //10 0101 0000
-            OP_STR_SPREL,  //10 0101 0001
-            OP_STR_SPREL,  //10 0101 0010
-            OP_STR_SPREL,  //10 0101 0011
-            OP_STR_SPREL,  //10 0101 0100
-            OP_STR_SPREL,  //10 0101 0101
-            OP_STR_SPREL,  //10 0101 0110
-            OP_STR_SPREL,  //10 0101 0111
-            OP_STR_SPREL,  //10 0101 1000
-            OP_STR_SPREL,  //10 0101 1001
-            OP_STR_SPREL,  //10 0101 1010
-            OP_STR_SPREL,  //10 0101 1011
-            OP_STR_SPREL,  //10 0101 1100
-            OP_STR_SPREL,  //10 0101 1101
-            OP_STR_SPREL,  //10 0101 1110
-            OP_STR_SPREL,  //10 0101 1111
+TABDECL(            OP_STR_SPREL),  //10 0101 0000
+TABDECL(            OP_STR_SPREL),  //10 0101 0001
+TABDECL(            OP_STR_SPREL),  //10 0101 0010
+TABDECL(            OP_STR_SPREL),  //10 0101 0011
+TABDECL(            OP_STR_SPREL),  //10 0101 0100
+TABDECL(            OP_STR_SPREL),  //10 0101 0101
+TABDECL(            OP_STR_SPREL),  //10 0101 0110
+TABDECL(            OP_STR_SPREL),  //10 0101 0111
+TABDECL(            OP_STR_SPREL),  //10 0101 1000
+TABDECL(            OP_STR_SPREL),  //10 0101 1001
+TABDECL(            OP_STR_SPREL),  //10 0101 1010
+TABDECL(            OP_STR_SPREL),  //10 0101 1011
+TABDECL(            OP_STR_SPREL),  //10 0101 1100
+TABDECL(            OP_STR_SPREL),  //10 0101 1101
+TABDECL(            OP_STR_SPREL),  //10 0101 1110
+TABDECL(            OP_STR_SPREL),  //10 0101 1111
 
-            OP_LDR_SPREL,  //10 0110 0000
-            OP_LDR_SPREL,  //10 0110 0001
-            OP_LDR_SPREL,  //10 0110 0010
-            OP_LDR_SPREL,  //10 0110 0011
-            OP_LDR_SPREL,  //10 0110 0100
-            OP_LDR_SPREL,  //10 0110 0101
-            OP_LDR_SPREL,  //10 0110 0110
-            OP_LDR_SPREL,  //10 0110 0111
-            OP_LDR_SPREL,  //10 0110 1000
-            OP_LDR_SPREL,  //10 0110 1001
-            OP_LDR_SPREL,  //10 0110 1010
-            OP_LDR_SPREL,  //10 0110 1011
-            OP_LDR_SPREL,  //10 0110 1100
-            OP_LDR_SPREL,  //10 0110 1101
-            OP_LDR_SPREL,  //10 0110 1110
-            OP_LDR_SPREL,  //10 0110 1111
+TABDECL(            OP_LDR_SPREL),  //10 0110 0000
+TABDECL(            OP_LDR_SPREL),  //10 0110 0001
+TABDECL(            OP_LDR_SPREL),  //10 0110 0010
+TABDECL(            OP_LDR_SPREL),  //10 0110 0011
+TABDECL(            OP_LDR_SPREL),  //10 0110 0100
+TABDECL(            OP_LDR_SPREL),  //10 0110 0101
+TABDECL(            OP_LDR_SPREL),  //10 0110 0110
+TABDECL(            OP_LDR_SPREL),  //10 0110 0111
+TABDECL(            OP_LDR_SPREL),  //10 0110 1000
+TABDECL(            OP_LDR_SPREL),  //10 0110 1001
+TABDECL(            OP_LDR_SPREL),  //10 0110 1010
+TABDECL(            OP_LDR_SPREL),  //10 0110 1011
+TABDECL(            OP_LDR_SPREL),  //10 0110 1100
+TABDECL(            OP_LDR_SPREL),  //10 0110 1101
+TABDECL(            OP_LDR_SPREL),  //10 0110 1110
+TABDECL(            OP_LDR_SPREL),  //10 0110 1111
 
-            OP_LDR_SPREL,  //10 0111 0000
-            OP_LDR_SPREL,  //10 0111 0001
-            OP_LDR_SPREL,  //10 0111 0010
-            OP_LDR_SPREL,  //10 0111 0011
-            OP_LDR_SPREL,  //10 0111 0100
-            OP_LDR_SPREL,  //10 0111 0101
-            OP_LDR_SPREL,  //10 0111 0110
-            OP_LDR_SPREL,  //10 0111 0111
-            OP_LDR_SPREL,  //10 0111 1000
-            OP_LDR_SPREL,  //10 0111 1001
-            OP_LDR_SPREL,  //10 0111 1010
-            OP_LDR_SPREL,  //10 0111 1011
-            OP_LDR_SPREL,  //10 0111 1100
-            OP_LDR_SPREL,  //10 0111 1101
-            OP_LDR_SPREL,  //10 0111 1110
-            OP_LDR_SPREL,  //10 0111 1111
+TABDECL(            OP_LDR_SPREL),  //10 0111 0000
+TABDECL(            OP_LDR_SPREL),  //10 0111 0001
+TABDECL(            OP_LDR_SPREL),  //10 0111 0010
+TABDECL(            OP_LDR_SPREL),  //10 0111 0011
+TABDECL(            OP_LDR_SPREL),  //10 0111 0100
+TABDECL(            OP_LDR_SPREL),  //10 0111 0101
+TABDECL(            OP_LDR_SPREL),  //10 0111 0110
+TABDECL(            OP_LDR_SPREL),  //10 0111 0111
+TABDECL(            OP_LDR_SPREL),  //10 0111 1000
+TABDECL(            OP_LDR_SPREL),  //10 0111 1001
+TABDECL(            OP_LDR_SPREL),  //10 0111 1010
+TABDECL(            OP_LDR_SPREL),  //10 0111 1011
+TABDECL(            OP_LDR_SPREL),  //10 0111 1100
+TABDECL(            OP_LDR_SPREL),  //10 0111 1101
+TABDECL(            OP_LDR_SPREL),  //10 0111 1110
+TABDECL(            OP_LDR_SPREL),  //10 0111 1111
 
-            OP_ADD_2PC,  //10 1000 0000
-            OP_ADD_2PC,  //10 1000 0001
-            OP_ADD_2PC,  //10 1000 0010
-            OP_ADD_2PC,  //10 1000 0011
-            OP_ADD_2PC,  //10 1000 0100
-            OP_ADD_2PC,  //10 1000 0101
-            OP_ADD_2PC,  //10 1000 0110
-            OP_ADD_2PC,  //10 1000 0111
-            OP_ADD_2PC,  //10 1000 1000
-            OP_ADD_2PC,  //10 1000 1001
-            OP_ADD_2PC,  //10 1000 1010
-            OP_ADD_2PC,  //10 1000 1011
-            OP_ADD_2PC,  //10 1000 1100
-            OP_ADD_2PC,  //10 1000 1101
-            OP_ADD_2PC,  //10 1000 1110
-            OP_ADD_2PC,  //10 1000 1111
+TABDECL(            OP_ADD_2PC),  //10 1000 0000
+TABDECL(            OP_ADD_2PC),  //10 1000 0001
+TABDECL(            OP_ADD_2PC),  //10 1000 0010
+TABDECL(            OP_ADD_2PC),  //10 1000 0011
+TABDECL(            OP_ADD_2PC),  //10 1000 0100
+TABDECL(            OP_ADD_2PC),  //10 1000 0101
+TABDECL(            OP_ADD_2PC),  //10 1000 0110
+TABDECL(            OP_ADD_2PC),  //10 1000 0111
+TABDECL(            OP_ADD_2PC),  //10 1000 1000
+TABDECL(            OP_ADD_2PC),  //10 1000 1001
+TABDECL(            OP_ADD_2PC),  //10 1000 1010
+TABDECL(            OP_ADD_2PC),  //10 1000 1011
+TABDECL(            OP_ADD_2PC),  //10 1000 1100
+TABDECL(            OP_ADD_2PC),  //10 1000 1101
+TABDECL(            OP_ADD_2PC),  //10 1000 1110
+TABDECL(            OP_ADD_2PC),  //10 1000 1111
 
-            OP_ADD_2PC,  //10 1001 0000
-            OP_ADD_2PC,  //10 1001 0001
-            OP_ADD_2PC,  //10 1001 0010
-            OP_ADD_2PC,  //10 1001 0011
-            OP_ADD_2PC,  //10 1001 0100
-            OP_ADD_2PC,  //10 1001 0101
-            OP_ADD_2PC,  //10 1001 0110
-            OP_ADD_2PC,  //10 1001 0111
-            OP_ADD_2PC,  //10 1001 1000
-            OP_ADD_2PC,  //10 1001 1001
-            OP_ADD_2PC,  //10 1001 1010
-            OP_ADD_2PC,  //10 1001 1011
-            OP_ADD_2PC,  //10 1001 1100
-            OP_ADD_2PC,  //10 1001 1101
-            OP_ADD_2PC,  //10 1001 1110
-            OP_ADD_2PC,  //10 1001 1111
+TABDECL(            OP_ADD_2PC),  //10 1001 0000
+TABDECL(            OP_ADD_2PC),  //10 1001 0001
+TABDECL(            OP_ADD_2PC),  //10 1001 0010
+TABDECL(            OP_ADD_2PC),  //10 1001 0011
+TABDECL(            OP_ADD_2PC),  //10 1001 0100
+TABDECL(            OP_ADD_2PC),  //10 1001 0101
+TABDECL(            OP_ADD_2PC),  //10 1001 0110
+TABDECL(            OP_ADD_2PC),  //10 1001 0111
+TABDECL(            OP_ADD_2PC),  //10 1001 1000
+TABDECL(            OP_ADD_2PC),  //10 1001 1001
+TABDECL(            OP_ADD_2PC),  //10 1001 1010
+TABDECL(            OP_ADD_2PC),  //10 1001 1011
+TABDECL(            OP_ADD_2PC),  //10 1001 1100
+TABDECL(            OP_ADD_2PC),  //10 1001 1101
+TABDECL(            OP_ADD_2PC),  //10 1001 1110
+TABDECL(            OP_ADD_2PC),  //10 1001 1111
 
-            OP_ADD_2SP,  //10 1010 0000
-            OP_ADD_2SP,  //10 1010 0001
-            OP_ADD_2SP,  //10 1010 0010
-            OP_ADD_2SP,  //10 1010 0011
-            OP_ADD_2SP,  //10 1010 0100
-            OP_ADD_2SP,  //10 1010 0101
-            OP_ADD_2SP,  //10 1010 0110
-            OP_ADD_2SP,  //10 1010 0111
-            OP_ADD_2SP,  //10 1010 1000
-            OP_ADD_2SP,  //10 1010 1001
-            OP_ADD_2SP,  //10 1010 1010
-            OP_ADD_2SP,  //10 1010 1011
-            OP_ADD_2SP,  //10 1010 1100
-            OP_ADD_2SP,  //10 1010 1101
-            OP_ADD_2SP,  //10 1010 1110
-            OP_ADD_2SP,  //10 1010 1111
+TABDECL(            OP_ADD_2SP),  //10 1010 0000
+TABDECL(            OP_ADD_2SP),  //10 1010 0001
+TABDECL(            OP_ADD_2SP),  //10 1010 0010
+TABDECL(            OP_ADD_2SP),  //10 1010 0011
+TABDECL(            OP_ADD_2SP),  //10 1010 0100
+TABDECL(            OP_ADD_2SP),  //10 1010 0101
+TABDECL(            OP_ADD_2SP),  //10 1010 0110
+TABDECL(            OP_ADD_2SP),  //10 1010 0111
+TABDECL(            OP_ADD_2SP),  //10 1010 1000
+TABDECL(            OP_ADD_2SP),  //10 1010 1001
+TABDECL(            OP_ADD_2SP),  //10 1010 1010
+TABDECL(            OP_ADD_2SP),  //10 1010 1011
+TABDECL(            OP_ADD_2SP),  //10 1010 1100
+TABDECL(            OP_ADD_2SP),  //10 1010 1101
+TABDECL(            OP_ADD_2SP),  //10 1010 1110
+TABDECL(            OP_ADD_2SP),  //10 1010 1111
 
-            OP_ADD_2SP,  //10 1011 0000
-            OP_ADD_2SP,  //10 1011 0001
-            OP_ADD_2SP,  //10 1011 0010
-            OP_ADD_2SP,  //10 1011 0011
-            OP_ADD_2SP,  //10 1011 0100
-            OP_ADD_2SP,  //10 1011 0101
-            OP_ADD_2SP,  //10 1011 0110
-            OP_ADD_2SP,  //10 1011 0111
-            OP_ADD_2SP,  //10 1011 1000
-            OP_ADD_2SP,  //10 1011 1001
-            OP_ADD_2SP,  //10 1011 1010
-            OP_ADD_2SP,  //10 1011 1011
-            OP_ADD_2SP,  //10 1011 1100
-            OP_ADD_2SP,  //10 1011 1101
-            OP_ADD_2SP,  //10 1011 1110
-            OP_ADD_2SP,  //10 1011 1111
+TABDECL(            OP_ADD_2SP),  //10 1011 0000
+TABDECL(            OP_ADD_2SP),  //10 1011 0001
+TABDECL(            OP_ADD_2SP),  //10 1011 0010
+TABDECL(            OP_ADD_2SP),  //10 1011 0011
+TABDECL(            OP_ADD_2SP),  //10 1011 0100
+TABDECL(            OP_ADD_2SP),  //10 1011 0101
+TABDECL(            OP_ADD_2SP),  //10 1011 0110
+TABDECL(            OP_ADD_2SP),  //10 1011 0111
+TABDECL(            OP_ADD_2SP),  //10 1011 1000
+TABDECL(            OP_ADD_2SP),  //10 1011 1001
+TABDECL(            OP_ADD_2SP),  //10 1011 1010
+TABDECL(            OP_ADD_2SP),  //10 1011 1011
+TABDECL(            OP_ADD_2SP),  //10 1011 1100
+TABDECL(            OP_ADD_2SP),  //10 1011 1101
+TABDECL(            OP_ADD_2SP),  //10 1011 1110
+TABDECL(            OP_ADD_2SP),  //10 1011 1111
 
-            OP_ADJUST_P_SP,  //10 1100 0000
-            OP_ADJUST_P_SP,  //10 1100 0001
-            OP_ADJUST_M_SP,  //10 1100 0010
-            OP_ADJUST_M_SP,  //10 1100 0011
-            OP_UND_THUMB,  //10 1100 0100
-            OP_UND_THUMB,  //10 1100 0101
-            OP_UND_THUMB,  //10 1100 0110
-            OP_UND_THUMB,  //10 1100 0111
-            OP_UND_THUMB,  //10 1100 1000
-            OP_UND_THUMB,  //10 1100 1001
-            OP_UND_THUMB,  //10 1100 1010
-            OP_UND_THUMB,  //10 1100 1011
-            OP_UND_THUMB,  //10 1100 1100
-            OP_UND_THUMB,  //10 1100 1101
-            OP_UND_THUMB,  //10 1100 1110
-            OP_UND_THUMB,  //10 1100 1111
+TABDECL(            OP_ADJUST_P_SP),  //10 1100 0000
+TABDECL(            OP_ADJUST_P_SP),  //10 1100 0001
+TABDECL(            OP_ADJUST_M_SP),  //10 1100 0010
+TABDECL(            OP_ADJUST_M_SP),  //10 1100 0011
+TABDECL(            OP_UND_THUMB),  //10 1100 0100
+TABDECL(            OP_UND_THUMB),  //10 1100 0101
+TABDECL(            OP_UND_THUMB),  //10 1100 0110
+TABDECL(            OP_UND_THUMB),  //10 1100 0111
+TABDECL(            OP_UND_THUMB),  //10 1100 1000
+TABDECL(            OP_UND_THUMB),  //10 1100 1001
+TABDECL(            OP_UND_THUMB),  //10 1100 1010
+TABDECL(            OP_UND_THUMB),  //10 1100 1011
+TABDECL(            OP_UND_THUMB),  //10 1100 1100
+TABDECL(            OP_UND_THUMB),  //10 1100 1101
+TABDECL(            OP_UND_THUMB),  //10 1100 1110
+TABDECL(            OP_UND_THUMB),  //10 1100 1111
 
-            OP_PUSH,  //10 1101 0000
-            OP_PUSH,  //10 1101 0001
-            OP_PUSH,  //10 1101 0010
-            OP_PUSH,  //10 1101 0011
-            OP_PUSH_LR,  //10 1101 0100
-            OP_PUSH_LR,  //10 1101 0101
-            OP_PUSH_LR,  //10 1101 0110
-            OP_PUSH_LR,  //10 1101 0111
-            OP_UND_THUMB,  //10 1101 1000
-            OP_UND_THUMB,  //10 1101 1001
-            OP_UND_THUMB,  //10 1101 1010
-            OP_UND_THUMB,  //10 1101 1011
-            OP_UND_THUMB,  //10 1101 1100
-            OP_UND_THUMB,  //10 1101 1101
-            OP_UND_THUMB,  //10 1101 1110
-            OP_UND_THUMB,  //10 1101 1111
+TABDECL(            OP_PUSH),  //10 1101 0000
+TABDECL(            OP_PUSH),  //10 1101 0001
+TABDECL(            OP_PUSH),  //10 1101 0010
+TABDECL(            OP_PUSH),  //10 1101 0011
+TABDECL(            OP_PUSH_LR),  //10 1101 0100
+TABDECL(            OP_PUSH_LR),  //10 1101 0101
+TABDECL(            OP_PUSH_LR),  //10 1101 0110
+TABDECL(            OP_PUSH_LR),  //10 1101 0111
+TABDECL(            OP_UND_THUMB),  //10 1101 1000
+TABDECL(            OP_UND_THUMB),  //10 1101 1001
+TABDECL(            OP_UND_THUMB),  //10 1101 1010
+TABDECL(            OP_UND_THUMB),  //10 1101 1011
+TABDECL(            OP_UND_THUMB),  //10 1101 1100
+TABDECL(            OP_UND_THUMB),  //10 1101 1101
+TABDECL(            OP_UND_THUMB),  //10 1101 1110
+TABDECL(            OP_UND_THUMB),  //10 1101 1111
 
-            OP_UND_THUMB,  //10 1110 0000
-            OP_UND_THUMB,  //10 1110 0001
-            OP_UND_THUMB,  //10 1110 0010
-            OP_UND_THUMB,  //10 1110 0011
-            OP_UND_THUMB,  //10 1110 0100
-            OP_UND_THUMB,  //10 1110 0101
-            OP_UND_THUMB,  //10 1110 0110
-            OP_UND_THUMB,  //10 1110 0111
-            OP_UND_THUMB,  //10 1110 1000
-            OP_UND_THUMB,  //10 1110 1001
-            OP_UND_THUMB,  //10 1110 1010
-            OP_UND_THUMB,  //10 1110 1011
-            OP_UND_THUMB,  //10 1110 1100
-            OP_UND_THUMB,  //10 1110 1101
-            OP_UND_THUMB,  //10 1110 1110
-            OP_UND_THUMB,  //10 1110 1111
+TABDECL(            OP_UND_THUMB),  //10 1110 0000
+TABDECL(            OP_UND_THUMB),  //10 1110 0001
+TABDECL(            OP_UND_THUMB),  //10 1110 0010
+TABDECL(            OP_UND_THUMB),  //10 1110 0011
+TABDECL(            OP_UND_THUMB),  //10 1110 0100
+TABDECL(            OP_UND_THUMB),  //10 1110 0101
+TABDECL(            OP_UND_THUMB),  //10 1110 0110
+TABDECL(            OP_UND_THUMB),  //10 1110 0111
+TABDECL(            OP_UND_THUMB),  //10 1110 1000
+TABDECL(            OP_UND_THUMB),  //10 1110 1001
+TABDECL(            OP_UND_THUMB),  //10 1110 1010
+TABDECL(            OP_UND_THUMB),  //10 1110 1011
+TABDECL(            OP_UND_THUMB),  //10 1110 1100
+TABDECL(            OP_UND_THUMB),  //10 1110 1101
+TABDECL(            OP_UND_THUMB),  //10 1110 1110
+TABDECL(            OP_UND_THUMB),  //10 1110 1111
 
-            OP_POP,  //10 1111 0000
-            OP_POP,  //10 1111 0001
-            OP_POP,  //10 1111 0010
-            OP_POP,  //10 1111 0011
-            OP_POP_PC,  //10 1111 0100
-            OP_POP_PC,  //10 1111 0101
-            OP_POP_PC,  //10 1111 0110
-            OP_POP_PC,  //10 1111 0111
-            OP_BKPT_THUMB,  //10 1111 1000
-            OP_BKPT_THUMB,  //10 1111 1001
-            OP_BKPT_THUMB,  //10 1111 1010
-            OP_BKPT_THUMB,  //10 1111 1011
-            OP_UND_THUMB,  //10 1111 1100
-            OP_UND_THUMB,  //10 1111 1101
-            OP_UND_THUMB,  //10 1111 1110
-            OP_UND_THUMB,  //10 1111 1111
+TABDECL(            OP_POP),  //10 1111 0000
+TABDECL(            OP_POP),  //10 1111 0001
+TABDECL(            OP_POP),  //10 1111 0010
+TABDECL(            OP_POP),  //10 1111 0011
+TABDECL(            OP_POP_PC),  //10 1111 0100
+TABDECL(            OP_POP_PC),  //10 1111 0101
+TABDECL(            OP_POP_PC),  //10 1111 0110
+TABDECL(            OP_POP_PC),  //10 1111 0111
+TABDECL(            OP_BKPT_THUMB),  //10 1111 1000
+TABDECL(            OP_BKPT_THUMB),  //10 1111 1001
+TABDECL(            OP_BKPT_THUMB),  //10 1111 1010
+TABDECL(            OP_BKPT_THUMB),  //10 1111 1011
+TABDECL(            OP_UND_THUMB),  //10 1111 1100
+TABDECL(            OP_UND_THUMB),  //10 1111 1101
+TABDECL(            OP_UND_THUMB),  //10 1111 1110
+TABDECL(            OP_UND_THUMB),  //10 1111 1111
 
-            OP_STMIA_THUMB,  //11 0000 0000
-            OP_STMIA_THUMB,  //11 0000 0001
-            OP_STMIA_THUMB,  //11 0000 0010
-            OP_STMIA_THUMB,  //11 0000 0011
-            OP_STMIA_THUMB,  //11 0000 0100
-            OP_STMIA_THUMB,  //11 0000 0101
-            OP_STMIA_THUMB,  //11 0000 0110
-            OP_STMIA_THUMB,  //11 0000 0111
-            OP_STMIA_THUMB,  //11 0000 1000
-            OP_STMIA_THUMB,  //11 0000 1001
-            OP_STMIA_THUMB,  //11 0000 1010
-            OP_STMIA_THUMB,  //11 0000 1011
-            OP_STMIA_THUMB,  //11 0000 1100
-            OP_STMIA_THUMB,  //11 0000 1101
-            OP_STMIA_THUMB,  //11 0000 1110
-            OP_STMIA_THUMB,  //11 0000 1111
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0000
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0001
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0010
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0011
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0100
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0101
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0110
+TABDECL(            OP_STMIA_THUMB),  //11 0000 0111
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1000
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1001
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1010
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1011
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1100
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1101
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1110
+TABDECL(            OP_STMIA_THUMB),  //11 0000 1111
 
-            OP_STMIA_THUMB,  //11 0001 0000
-            OP_STMIA_THUMB,  //11 0001 0001
-            OP_STMIA_THUMB,  //11 0001 0010
-            OP_STMIA_THUMB,  //11 0001 0011
-            OP_STMIA_THUMB,  //11 0001 0100
-            OP_STMIA_THUMB,  //11 0001 0101
-            OP_STMIA_THUMB,  //11 0001 0110
-            OP_STMIA_THUMB,  //11 0001 0111
-            OP_STMIA_THUMB,  //11 0001 1000
-            OP_STMIA_THUMB,  //11 0001 1001
-            OP_STMIA_THUMB,  //11 0001 1010
-            OP_STMIA_THUMB,  //11 0001 1011
-            OP_STMIA_THUMB,  //11 0001 1100
-            OP_STMIA_THUMB,  //11 0001 1101
-            OP_STMIA_THUMB,  //11 0001 1110
-            OP_STMIA_THUMB,  //11 0001 1111
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0000
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0001
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0010
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0011
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0100
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0101
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0110
+TABDECL(            OP_STMIA_THUMB),  //11 0001 0111
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1000
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1001
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1010
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1011
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1100
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1101
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1110
+TABDECL(            OP_STMIA_THUMB),  //11 0001 1111
 
-            OP_LDMIA_THUMB,  //11 0010 0000
-            OP_LDMIA_THUMB,  //11 0010 0001
-            OP_LDMIA_THUMB,  //11 0010 0010
-            OP_LDMIA_THUMB,  //11 0010 0011
-            OP_LDMIA_THUMB,  //11 0010 0100
-            OP_LDMIA_THUMB,  //11 0010 0101
-            OP_LDMIA_THUMB,  //11 0010 0110
-            OP_LDMIA_THUMB,  //11 0010 0111
-            OP_LDMIA_THUMB,  //11 0010 1000
-            OP_LDMIA_THUMB,  //11 0010 1001
-            OP_LDMIA_THUMB,  //11 0010 1010
-            OP_LDMIA_THUMB,  //11 0010 1011
-            OP_LDMIA_THUMB,  //11 0010 1100
-            OP_LDMIA_THUMB,  //11 0010 1101
-            OP_LDMIA_THUMB,  //11 0010 1110
-            OP_LDMIA_THUMB,  //11 0010 1111
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0000
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0001
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0010
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0011
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0100
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0101
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0110
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 0111
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1000
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1001
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1010
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1011
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1100
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1101
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1110
+TABDECL(            OP_LDMIA_THUMB),  //11 0010 1111
 
-            OP_LDMIA_THUMB,  //11 0011 0000
-            OP_LDMIA_THUMB,  //11 0011 0001
-            OP_LDMIA_THUMB,  //11 0011 0010
-            OP_LDMIA_THUMB,  //11 0011 0011
-            OP_LDMIA_THUMB,  //11 0011 0100
-            OP_LDMIA_THUMB,  //11 0011 0101
-            OP_LDMIA_THUMB,  //11 0011 0110
-            OP_LDMIA_THUMB,  //11 0011 0111
-            OP_LDMIA_THUMB,  //11 0011 1000
-            OP_LDMIA_THUMB,  //11 0011 1001
-            OP_LDMIA_THUMB,  //11 0011 1010
-            OP_LDMIA_THUMB,  //11 0011 1011
-            OP_LDMIA_THUMB,  //11 0011 1100
-            OP_LDMIA_THUMB,  //11 0011 1101
-            OP_LDMIA_THUMB,  //11 0011 1110
-            OP_LDMIA_THUMB,  //11 0011 1111
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0000
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0001
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0010
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0011
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0100
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0101
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0110
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 0111
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1000
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1001
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1010
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1011
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1100
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1101
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1110
+TABDECL(            OP_LDMIA_THUMB),  //11 0011 1111
 
-            OP_B_COND,  //11 0100 0000
-            OP_B_COND,  //11 0100 0001
-            OP_B_COND,  //11 0100 0010
-            OP_B_COND,  //11 0100 0011
-            OP_B_COND,  //11 0100 0100
-            OP_B_COND,  //11 0100 0101
-            OP_B_COND,  //11 0100 0110
-            OP_B_COND,  //11 0100 0111
-            OP_B_COND,  //11 0100 1000
-            OP_B_COND,  //11 0100 1001
-            OP_B_COND,  //11 0100 1010
-            OP_B_COND,  //11 0100 1011
-            OP_B_COND,  //11 0100 1100
-            OP_B_COND,  //11 0100 1101
-            OP_B_COND,  //11 0100 1110
-            OP_B_COND,  //11 0100 1111
+TABDECL(            OP_B_COND),  //11 0100 0000
+TABDECL(            OP_B_COND),  //11 0100 0001
+TABDECL(            OP_B_COND),  //11 0100 0010
+TABDECL(            OP_B_COND),  //11 0100 0011
+TABDECL(            OP_B_COND),  //11 0100 0100
+TABDECL(            OP_B_COND),  //11 0100 0101
+TABDECL(            OP_B_COND),  //11 0100 0110
+TABDECL(            OP_B_COND),  //11 0100 0111
+TABDECL(            OP_B_COND),  //11 0100 1000
+TABDECL(            OP_B_COND),  //11 0100 1001
+TABDECL(            OP_B_COND),  //11 0100 1010
+TABDECL(            OP_B_COND),  //11 0100 1011
+TABDECL(            OP_B_COND),  //11 0100 1100
+TABDECL(            OP_B_COND),  //11 0100 1101
+TABDECL(            OP_B_COND),  //11 0100 1110
+TABDECL(            OP_B_COND),  //11 0100 1111
 
-            OP_B_COND,  //11 0101 0000
-            OP_B_COND,  //11 0101 0001
-            OP_B_COND,  //11 0101 0010
-            OP_B_COND,  //11 0101 0011
-            OP_B_COND,  //11 0101 0100
-            OP_B_COND,  //11 0101 0101
-            OP_B_COND,  //11 0101 0110
-            OP_B_COND,  //11 0101 0111
-            OP_B_COND,  //11 0101 1000
-            OP_B_COND,  //11 0101 1001
-            OP_B_COND,  //11 0101 1010
-            OP_B_COND,  //11 0101 1011
-            OP_B_COND,  //11 0101 1100
-            OP_B_COND,  //11 0101 1101
-            OP_B_COND,  //11 0101 1110
-            OP_B_COND,  //11 0101 1111
+TABDECL(            OP_B_COND),  //11 0101 0000
+TABDECL(            OP_B_COND),  //11 0101 0001
+TABDECL(            OP_B_COND),  //11 0101 0010
+TABDECL(            OP_B_COND),  //11 0101 0011
+TABDECL(            OP_B_COND),  //11 0101 0100
+TABDECL(            OP_B_COND),  //11 0101 0101
+TABDECL(            OP_B_COND),  //11 0101 0110
+TABDECL(            OP_B_COND),  //11 0101 0111
+TABDECL(            OP_B_COND),  //11 0101 1000
+TABDECL(            OP_B_COND),  //11 0101 1001
+TABDECL(            OP_B_COND),  //11 0101 1010
+TABDECL(            OP_B_COND),  //11 0101 1011
+TABDECL(            OP_B_COND),  //11 0101 1100
+TABDECL(            OP_B_COND),  //11 0101 1101
+TABDECL(            OP_B_COND),  //11 0101 1110
+TABDECL(            OP_B_COND),  //11 0101 1111
 
-            OP_B_COND,  //11 0110 0000
-            OP_B_COND,  //11 0110 0001
-            OP_B_COND,  //11 0110 0010
-            OP_B_COND,  //11 0110 0011
-            OP_B_COND,  //11 0110 0100
-            OP_B_COND,  //11 0110 0101
-            OP_B_COND,  //11 0110 0110
-            OP_B_COND,  //11 0110 0111
-            OP_B_COND,  //11 0110 1000
-            OP_B_COND,  //11 0110 1001
-            OP_B_COND,  //11 0110 1010
-            OP_B_COND,  //11 0110 1011
-            OP_B_COND,  //11 0110 1100
-            OP_B_COND,  //11 0110 1101
-            OP_B_COND,  //11 0110 1110
-            OP_B_COND,  //11 0110 1111
+TABDECL(            OP_B_COND),  //11 0110 0000
+TABDECL(            OP_B_COND),  //11 0110 0001
+TABDECL(            OP_B_COND),  //11 0110 0010
+TABDECL(            OP_B_COND),  //11 0110 0011
+TABDECL(            OP_B_COND),  //11 0110 0100
+TABDECL(            OP_B_COND),  //11 0110 0101
+TABDECL(            OP_B_COND),  //11 0110 0110
+TABDECL(            OP_B_COND),  //11 0110 0111
+TABDECL(            OP_B_COND),  //11 0110 1000
+TABDECL(            OP_B_COND),  //11 0110 1001
+TABDECL(            OP_B_COND),  //11 0110 1010
+TABDECL(            OP_B_COND),  //11 0110 1011
+TABDECL(            OP_B_COND),  //11 0110 1100
+TABDECL(            OP_B_COND),  //11 0110 1101
+TABDECL(            OP_B_COND),  //11 0110 1110
+TABDECL(            OP_B_COND),  //11 0110 1111
 
-            OP_B_COND,  //11 0111 0000
-            OP_B_COND,  //11 0111 0001
-            OP_B_COND,  //11 0111 0010
-            OP_B_COND,  //11 0111 0011
-            OP_B_COND,  //11 0111 0100
-            OP_B_COND,  //11 0111 0101
-            OP_B_COND,  //11 0111 0110
-            OP_B_COND,  //11 0111 0111
-            OP_B_COND,  //11 0111 1000
-            OP_B_COND,  //11 0111 1001
-            OP_B_COND,  //11 0111 1010
-            OP_B_COND,  //11 0111 1011
-            OP_SWI_THUMB,  //11 0111 1100
-            OP_SWI_THUMB,  //11 0111 1101
-            OP_SWI_THUMB,  //11 0111 1110
-            OP_SWI_THUMB,  //11 0111 1111
+TABDECL(            OP_B_COND),  //11 0111 0000
+TABDECL(            OP_B_COND),  //11 0111 0001
+TABDECL(            OP_B_COND),  //11 0111 0010
+TABDECL(            OP_B_COND),  //11 0111 0011
+TABDECL(            OP_B_COND),  //11 0111 0100
+TABDECL(            OP_B_COND),  //11 0111 0101
+TABDECL(            OP_B_COND),  //11 0111 0110
+TABDECL(            OP_B_COND),  //11 0111 0111
+TABDECL(            OP_B_COND),  //11 0111 1000
+TABDECL(            OP_B_COND),  //11 0111 1001
+TABDECL(            OP_B_COND),  //11 0111 1010
+TABDECL(            OP_B_COND),  //11 0111 1011
+TABDECL(            OP_SWI_THUMB),  //11 0111 1100
+TABDECL(            OP_SWI_THUMB),  //11 0111 1101
+TABDECL(            OP_SWI_THUMB),  //11 0111 1110
+TABDECL(            OP_SWI_THUMB),  //11 0111 1111
 
-            OP_B_UNCOND,  //11 1000 0000
-            OP_B_UNCOND,  //11 1000 0001
-            OP_B_UNCOND,  //11 1000 0010
-            OP_B_UNCOND,  //11 1000 0011
-            OP_B_UNCOND,  //11 1000 0100
-            OP_B_UNCOND,  //11 1000 0101
-            OP_B_UNCOND,  //11 1000 0110
-            OP_B_UNCOND,  //11 1000 0111
-            OP_B_UNCOND,  //11 1000 1000
-            OP_B_UNCOND,  //11 1000 1001
-            OP_B_UNCOND,  //11 1000 1010
-            OP_B_UNCOND,  //11 1000 1011
-            OP_B_UNCOND,  //11 1000 1100
-            OP_B_UNCOND,  //11 1000 1101
-            OP_B_UNCOND,  //11 1000 1110
-            OP_B_UNCOND,  //11 1000 1111
+TABDECL(            OP_B_UNCOND),  //11 1000 0000
+TABDECL(            OP_B_UNCOND),  //11 1000 0001
+TABDECL(            OP_B_UNCOND),  //11 1000 0010
+TABDECL(            OP_B_UNCOND),  //11 1000 0011
+TABDECL(            OP_B_UNCOND),  //11 1000 0100
+TABDECL(            OP_B_UNCOND),  //11 1000 0101
+TABDECL(            OP_B_UNCOND),  //11 1000 0110
+TABDECL(            OP_B_UNCOND),  //11 1000 0111
+TABDECL(            OP_B_UNCOND),  //11 1000 1000
+TABDECL(            OP_B_UNCOND),  //11 1000 1001
+TABDECL(            OP_B_UNCOND),  //11 1000 1010
+TABDECL(            OP_B_UNCOND),  //11 1000 1011
+TABDECL(            OP_B_UNCOND),  //11 1000 1100
+TABDECL(            OP_B_UNCOND),  //11 1000 1101
+TABDECL(            OP_B_UNCOND),  //11 1000 1110
+TABDECL(            OP_B_UNCOND),  //11 1000 1111
 
-            OP_B_UNCOND,  //11 1001 0000
-            OP_B_UNCOND,  //11 1001 0001
-            OP_B_UNCOND,  //11 1001 0010
-            OP_B_UNCOND,  //11 1001 0011
-            OP_B_UNCOND,  //11 1001 0100
-            OP_B_UNCOND,  //11 1001 0101
-            OP_B_UNCOND,  //11 1001 0110
-            OP_B_UNCOND,  //11 1001 0111
-            OP_B_UNCOND,  //11 1001 1000
-            OP_B_UNCOND,  //11 1001 1001
-            OP_B_UNCOND,  //11 1001 1010
-            OP_B_UNCOND,  //11 1001 1011
-            OP_B_UNCOND,  //11 1001 1100
-            OP_B_UNCOND,  //11 1001 1101
-            OP_B_UNCOND,  //11 1001 1110
-            OP_B_UNCOND,  //11 1001 1111
+TABDECL(            OP_B_UNCOND),  //11 1001 0000
+TABDECL(            OP_B_UNCOND),  //11 1001 0001
+TABDECL(            OP_B_UNCOND),  //11 1001 0010
+TABDECL(            OP_B_UNCOND),  //11 1001 0011
+TABDECL(            OP_B_UNCOND),  //11 1001 0100
+TABDECL(            OP_B_UNCOND),  //11 1001 0101
+TABDECL(            OP_B_UNCOND),  //11 1001 0110
+TABDECL(            OP_B_UNCOND),  //11 1001 0111
+TABDECL(            OP_B_UNCOND),  //11 1001 1000
+TABDECL(            OP_B_UNCOND),  //11 1001 1001
+TABDECL(            OP_B_UNCOND),  //11 1001 1010
+TABDECL(            OP_B_UNCOND),  //11 1001 1011
+TABDECL(            OP_B_UNCOND),  //11 1001 1100
+TABDECL(            OP_B_UNCOND),  //11 1001 1101
+TABDECL(            OP_B_UNCOND),  //11 1001 1110
+TABDECL(            OP_B_UNCOND),  //11 1001 1111
 
-            OP_BLX,  //11 1010 0000
-            OP_BLX,  //11 1010 0001
-            OP_BLX,  //11 1010 0010
-            OP_BLX,  //11 1010 0011
-            OP_BLX,  //11 1010 0100
-            OP_BLX,  //11 1010 0101
-            OP_BLX,  //11 1010 0110
-            OP_BLX,  //11 1010 0111
-            OP_BLX,  //11 1010 1000
-            OP_BLX,  //11 1010 1001
-            OP_BLX,  //11 1010 1010
-            OP_BLX,  //11 1010 1011
-            OP_BLX,  //11 1010 1100
-            OP_BLX,  //11 1010 1101
-            OP_BLX,  //11 1010 1110
-            OP_BLX,  //11 1010 1111
+TABDECL(            OP_BLX),  //11 1010 0000
+TABDECL(            OP_BLX),  //11 1010 0001
+TABDECL(            OP_BLX),  //11 1010 0010
+TABDECL(            OP_BLX),  //11 1010 0011
+TABDECL(            OP_BLX),  //11 1010 0100
+TABDECL(            OP_BLX),  //11 1010 0101
+TABDECL(            OP_BLX),  //11 1010 0110
+TABDECL(            OP_BLX),  //11 1010 0111
+TABDECL(            OP_BLX),  //11 1010 1000
+TABDECL(            OP_BLX),  //11 1010 1001
+TABDECL(            OP_BLX),  //11 1010 1010
+TABDECL(            OP_BLX),  //11 1010 1011
+TABDECL(            OP_BLX),  //11 1010 1100
+TABDECL(            OP_BLX),  //11 1010 1101
+TABDECL(            OP_BLX),  //11 1010 1110
+TABDECL(            OP_BLX),  //11 1010 1111
 
-            OP_BLX,  //11 1011 0000
-            OP_BLX,  //11 1011 0001
-            OP_BLX,  //11 1011 0010
-            OP_BLX,  //11 1011 0011
-            OP_BLX,  //11 1011 0100
-            OP_BLX,  //11 1011 0101
-            OP_BLX,  //11 1011 0110
-            OP_BLX,  //11 1011 0111
-            OP_BLX,  //11 1011 1000
-            OP_BLX,  //11 1011 1001
-            OP_BLX,  //11 1011 1010
-            OP_BLX,  //11 1011 1011
-            OP_BLX,  //11 1011 1100
-            OP_BLX,  //11 1011 1101
-            OP_BLX,  //11 1011 1110
-            OP_BLX,  //11 1011 1111
+TABDECL(            OP_BLX),  //11 1011 0000
+TABDECL(            OP_BLX),  //11 1011 0001
+TABDECL(            OP_BLX),  //11 1011 0010
+TABDECL(            OP_BLX),  //11 1011 0011
+TABDECL(            OP_BLX),  //11 1011 0100
+TABDECL(            OP_BLX),  //11 1011 0101
+TABDECL(            OP_BLX),  //11 1011 0110
+TABDECL(            OP_BLX),  //11 1011 0111
+TABDECL(            OP_BLX),  //11 1011 1000
+TABDECL(            OP_BLX),  //11 1011 1001
+TABDECL(            OP_BLX),  //11 1011 1010
+TABDECL(            OP_BLX),  //11 1011 1011
+TABDECL(            OP_BLX),  //11 1011 1100
+TABDECL(            OP_BLX),  //11 1011 1101
+TABDECL(            OP_BLX),  //11 1011 1110
+TABDECL(            OP_BLX),  //11 1011 1111
 
-            OP_BL_10,  //11 1100 0000
-            OP_BL_10,  //11 1100 0001
-            OP_BL_10,  //11 1100 0010
-            OP_BL_10,  //11 1100 0011
-            OP_BL_10,  //11 1100 0100
-            OP_BL_10,  //11 1100 0101
-            OP_BL_10,  //11 1100 0110
-            OP_BL_10,  //11 1100 0111
-            OP_BL_10,  //11 1100 1000
-            OP_BL_10,  //11 1100 1001
-            OP_BL_10,  //11 1100 1010
-            OP_BL_10,  //11 1100 1011
-            OP_BL_10,  //11 1100 1100
-            OP_BL_10,  //11 1100 1101
-            OP_BL_10,  //11 1100 1110
-            OP_BL_10,  //11 1100 1111
+TABDECL(            OP_BL_10),  //11 1100 0000
+TABDECL(            OP_BL_10),  //11 1100 0001
+TABDECL(            OP_BL_10),  //11 1100 0010
+TABDECL(            OP_BL_10),  //11 1100 0011
+TABDECL(            OP_BL_10),  //11 1100 0100
+TABDECL(            OP_BL_10),  //11 1100 0101
+TABDECL(            OP_BL_10),  //11 1100 0110
+TABDECL(            OP_BL_10),  //11 1100 0111
+TABDECL(            OP_BL_10),  //11 1100 1000
+TABDECL(            OP_BL_10),  //11 1100 1001
+TABDECL(            OP_BL_10),  //11 1100 1010
+TABDECL(            OP_BL_10),  //11 1100 1011
+TABDECL(            OP_BL_10),  //11 1100 1100
+TABDECL(            OP_BL_10),  //11 1100 1101
+TABDECL(            OP_BL_10),  //11 1100 1110
+TABDECL(            OP_BL_10),  //11 1100 1111
 
-            OP_BL_10,  //11 1101 0000
-            OP_BL_10,  //11 1101 0001
-            OP_BL_10,  //11 1101 0010
-            OP_BL_10,  //11 1101 0011
-            OP_BL_10,  //11 1101 0100
-            OP_BL_10,  //11 1101 0101
-            OP_BL_10,  //11 1101 0110
-            OP_BL_10,  //11 1101 0111
-            OP_BL_10,  //11 1101 1000
-            OP_BL_10,  //11 1101 1001
-            OP_BL_10,  //11 1101 1010
-            OP_BL_10,  //11 1101 1011
-            OP_BL_10,  //11 1101 1100
-            OP_BL_10,  //11 1101 1101
-            OP_BL_10,  //11 1101 1110
-            OP_BL_10,  //11 1101 1111
+TABDECL(            OP_BL_10),  //11 1101 0000
+TABDECL(            OP_BL_10),  //11 1101 0001
+TABDECL(            OP_BL_10),  //11 1101 0010
+TABDECL(            OP_BL_10),  //11 1101 0011
+TABDECL(            OP_BL_10),  //11 1101 0100
+TABDECL(            OP_BL_10),  //11 1101 0101
+TABDECL(            OP_BL_10),  //11 1101 0110
+TABDECL(            OP_BL_10),  //11 1101 0111
+TABDECL(            OP_BL_10),  //11 1101 1000
+TABDECL(            OP_BL_10),  //11 1101 1001
+TABDECL(            OP_BL_10),  //11 1101 1010
+TABDECL(            OP_BL_10),  //11 1101 1011
+TABDECL(            OP_BL_10),  //11 1101 1100
+TABDECL(            OP_BL_10),  //11 1101 1101
+TABDECL(            OP_BL_10),  //11 1101 1110
+TABDECL(            OP_BL_10),  //11 1101 1111
 
-            OP_BL_THUMB,  //11 1110 0000
-            OP_BL_THUMB,  //11 1110 0001
-            OP_BL_THUMB,  //11 1110 0010
-            OP_BL_THUMB,  //11 1110 0011
-            OP_BL_THUMB,  //11 1110 0100
-            OP_BL_THUMB,  //11 1110 0101
-            OP_BL_THUMB,  //11 1110 0110
-            OP_BL_THUMB,  //11 1110 0111
-            OP_BL_THUMB,  //11 1110 1000
-            OP_BL_THUMB,  //11 1110 1001
-            OP_BL_THUMB,  //11 1110 1010
-            OP_BL_THUMB,  //11 1110 1011
-            OP_BL_THUMB,  //11 1110 1100
-            OP_BL_THUMB,  //11 1110 1101
-            OP_BL_THUMB,  //11 1110 1110
-            OP_BL_THUMB,  //11 1110 1111
+TABDECL(            OP_BL_THUMB),  //11 1110 0000
+TABDECL(            OP_BL_THUMB),  //11 1110 0001
+TABDECL(            OP_BL_THUMB),  //11 1110 0010
+TABDECL(            OP_BL_THUMB),  //11 1110 0011
+TABDECL(            OP_BL_THUMB),  //11 1110 0100
+TABDECL(            OP_BL_THUMB),  //11 1110 0101
+TABDECL(            OP_BL_THUMB),  //11 1110 0110
+TABDECL(            OP_BL_THUMB),  //11 1110 0111
+TABDECL(            OP_BL_THUMB),  //11 1110 1000
+TABDECL(            OP_BL_THUMB),  //11 1110 1001
+TABDECL(            OP_BL_THUMB),  //11 1110 1010
+TABDECL(            OP_BL_THUMB),  //11 1110 1011
+TABDECL(            OP_BL_THUMB),  //11 1110 1100
+TABDECL(            OP_BL_THUMB),  //11 1110 1101
+TABDECL(            OP_BL_THUMB),  //11 1110 1110
+TABDECL(            OP_BL_THUMB),  //11 1110 1111
 
-            OP_BL_THUMB,  //11 1111 0000
-            OP_BL_THUMB,  //11 1111 0001
-            OP_BL_THUMB,  //11 1111 0010
-            OP_BL_THUMB,  //11 1111 0011
-            OP_BL_THUMB,  //11 1111 0100
-            OP_BL_THUMB,  //11 1111 0101
-            OP_BL_THUMB,  //11 1111 0110
-            OP_BL_THUMB,  //11 1111 0111
-            OP_BL_THUMB,  //11 1111 1000
-            OP_BL_THUMB,  //11 1111 1001
-            OP_BL_THUMB,  //11 1111 1010
-            OP_BL_THUMB,  //11 1111 1011
-            OP_BL_THUMB,  //11 1111 1100
-            OP_BL_THUMB,  //11 1111 1101
-            OP_BL_THUMB,  //11 1111 1110
-            OP_BL_THUMB,  //11 1111 1111
+TABDECL(            OP_BL_THUMB),  //11 1111 0000
+TABDECL(            OP_BL_THUMB),  //11 1111 0001
+TABDECL(            OP_BL_THUMB),  //11 1111 0010
+TABDECL(            OP_BL_THUMB),  //11 1111 0011
+TABDECL(            OP_BL_THUMB),  //11 1111 0100
+TABDECL(            OP_BL_THUMB),  //11 1111 0101
+TABDECL(            OP_BL_THUMB),  //11 1111 0110
+TABDECL(            OP_BL_THUMB),  //11 1111 0111
+TABDECL(            OP_BL_THUMB),  //11 1111 1000
+TABDECL(            OP_BL_THUMB),  //11 1111 1001
+TABDECL(            OP_BL_THUMB),  //11 1111 1010
+TABDECL(            OP_BL_THUMB),  //11 1111 1011
+TABDECL(            OP_BL_THUMB),  //11 1111 1100
+TABDECL(            OP_BL_THUMB),  //11 1111 1101
+TABDECL(            OP_BL_THUMB),  //11 1111 1110
+TABDECL(            OP_BL_THUMB),  //11 1111 1111
 }; //1089
  
diff --git a/desmume/src/windows/DeSmuME_2005.vcproj b/desmume/src/windows/DeSmuME_2005.vcproj
index f8c3679a7..a5560c526 100644
--- a/desmume/src/windows/DeSmuME_2005.vcproj
+++ b/desmume/src/windows/DeSmuME_2005.vcproj
@@ -614,7 +614,7 @@
 				>
 			</File>
 			<File
-				RelativePath="..\gdbstub\gdbstub.c"
+				RelativePath="..\gdbstub\gdbstub.cpp"
 				>
 			</File>
 			<File
diff --git a/desmume/src/windows/DeSmuME_2008.vcproj b/desmume/src/windows/DeSmuME_2008.vcproj
index 4515c83b3..05ce077a3 100644
--- a/desmume/src/windows/DeSmuME_2008.vcproj
+++ b/desmume/src/windows/DeSmuME_2008.vcproj
@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="shift_jis"?>
 <VisualStudioProject
 	ProjectType="Visual C++"
-	Version="9,00"
+	Version="9.00"
 	Name="DeSmuME_VS2008"
 	ProjectGUID="{9F5F72A1-D3A5-4918-B460-E076B16D10A9}"
 	RootNamespace="DeSmuME"
@@ -197,7 +197,6 @@
 			IntermediateDirectory="$(SolutionDir)\.VS2008\$(ConfigurationName)\$(PlatformName)"
 			ConfigurationType="1"
 			InheritedPropertySheets="$(VCInstallDir)VCProjectDefaults\UpgradeFromVC71.vsprops"
-			WholeProgramOptimization="1"
 			>
 			<Tool
 				Name="VCPreBuildEventTool"
@@ -219,23 +218,21 @@
 			/>
 			<Tool
 				Name="VCCLCompilerTool"
+				Optimization="2"
 				InlineFunctionExpansion="2"
 				EnableIntrinsicFunctions="true"
 				FavorSizeOrSpeed="1"
-				OmitFramePointers="true"
 				EnableFiberSafeOptimizations="true"
 				WholeProgramOptimization="true"
 				AdditionalIncludeDirectories="..;.\zlib123;.\zziplib"
 				PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2\&quot;;WIN32;HAVE_LIBZ;HAVE_LIBZZIP;BETA_VERSION"
-				StringPooling="true"
 				ExceptionHandling="0"
 				BufferSecurityCheck="false"
 				EnableEnhancedInstructionSet="0"
-				FloatingPointModel="2"
 				WarningLevel="1"
 				DebugInformationFormat="3"
-				CallingConvention="1"
-				CompileAs="0"
+				CallingConvention="0"
+				CompileAs="1"
 			/>
 			<Tool
 				Name="VCManagedResourceCompilerTool"
@@ -306,6 +303,7 @@
 			/>
 			<Tool
 				Name="VCCLCompilerTool"
+				Optimization="2"
 				InlineFunctionExpansion="2"
 				EnableIntrinsicFunctions="true"
 				FavorSizeOrSpeed="1"
@@ -399,7 +397,7 @@
 				EnableFiberSafeOptimizations="true"
 				WholeProgramOptimization="true"
 				AdditionalIncludeDirectories="..;.\zlib123;.\zziplib"
-				PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2 SSE2\&quot;;WIN32;HAVE_LIBZ;HAVE_LIBZZIP;SSE2;BETA_VERSION"
+				PreprocessorDefinitions="_CRT_SECURE_NO_DEPRECATE;VERSION=\&quot;0.8.0b2 SSE2\&quot;;WIN32;SSE2;BETA_VERSION"
 				StringPooling="true"
 				ExceptionHandling="0"
 				BufferSecurityCheck="false"
@@ -421,12 +419,13 @@
 			/>
 			<Tool
 				Name="VCLinkerTool"
-				AdditionalDependencies="opengl32.lib glu32.lib ws2_32.lib user32.lib gdi32.lib dxguid.lib shell32.lib comdlg32.lib dxerr.lib dsound.lib dinput8.lib ddraw.lib zlib-2008-x32.lib zziplib-2008-x32.lib"
+				AdditionalDependencies="opengl32.lib glu32.lib ws2_32.lib user32.lib gdi32.lib dxguid.lib shell32.lib comdlg32.lib dxerr.lib dsound.lib dinput8.lib ddraw.lib"
 				OutputFile="$(OutDir)\$(ProjectName)_sse2.exe"
 				AdditionalLibraryDirectories=".\zlib123;.\zziplib"
 				GenerateDebugInformation="true"
 				RandomizedBaseAddress="1"
 				DataExecutionPrevention="0"
+				Profile="true"
 			/>
 			<Tool
 				Name="VCALinkTool"
@@ -479,6 +478,7 @@
 			/>
 			<Tool
 				Name="VCCLCompilerTool"
+				Optimization="2"
 				InlineFunctionExpansion="2"
 				EnableIntrinsicFunctions="true"
 				FavorSizeOrSpeed="1"
@@ -512,6 +512,7 @@
 				RandomizedBaseAddress="1"
 				DataExecutionPrevention="0"
 				TargetMachine="17"
+				Profile="true"
 			/>
 			<Tool
 				Name="VCALinkTool"
@@ -610,7 +611,7 @@
 				>
 			</File>
 			<File
-				RelativePath="..\gdbstub\gdbstub.c"
+				RelativePath="..\gdbstub\gdbstub.cpp"
 				>
 			</File>
 			<File
@@ -637,7 +638,7 @@
 					>
 					<Tool
 						Name="VCCLCompilerTool"
-						CompileAs="0"
+						CompileAs="1"
 					/>
 				</FileConfiguration>
 				<FileConfiguration
@@ -747,14 +748,6 @@
 						Name="MASM"
 					/>
 				</FileConfiguration>
-				<FileConfiguration
-					Name="Release|Win32"
-					ExcludedFromBuild="true"
-					>
-					<Tool
-						Name="MASM"
-					/>
-				</FileConfiguration>
 				<FileConfiguration
 					Name="Release|x64"
 					ExcludedFromBuild="true"
@@ -811,26 +804,10 @@
 			<File
 				RelativePath="..\ROMReader.cpp"
 				>
-				<FileConfiguration
-					Name="Release (SSE2)|Win32"
-					>
-					<Tool
-						Name="VCCLCompilerTool"
-						CallingConvention="1"
-					/>
-				</FileConfiguration>
 			</File>
 			<File
 				RelativePath="..\saves.cpp"
 				>
-				<FileConfiguration
-					Name="Release (SSE2)|Win32"
-					>
-					<Tool
-						Name="VCCLCompilerTool"
-						CallingConvention="1"
-					/>
-				</FileConfiguration>
 			</File>
 			<File
 				RelativePath=".\snddx.cpp"
@@ -852,10 +829,6 @@
 				RelativePath="..\wifi.cpp"
 				>
 			</File>
-			<Filter
-				Name="windows"
-				>
-			</Filter>
 		</Filter>
 		<Filter
 			Name="Header Files"
@@ -1010,6 +983,10 @@
 				RelativePath=".\oamView.h"
 				>
 			</File>
+			<File
+				RelativePath=".\OGLRender.h"
+				>
+			</File>
 			<File
 				RelativePath=".\palView.h"
 				>
@@ -1018,6 +995,10 @@
 				RelativePath="..\registers.h"
 				>
 			</File>
+			<File
+				RelativePath="..\render3D.h"
+				>
+			</File>
 			<File
 				RelativePath=".\resource.h"
 				>