Reduce code required for some flag calculations in two opcode's. (Shouldn't break things but best too do more testing before adding to release branch).
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@ -1162,8 +1162,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL()
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}\
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cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\
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cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\
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cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(tmp, cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(tmp, cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \
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return a; \
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}
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@ -334,8 +334,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG()
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cpu->CPSR.bits.N = BIT31(res);
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cpu->CPSR.bits.Z = res == 0;
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cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(tmp, a, res);
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cpu->CPSR.bits.V = SIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(tmp, a, res);
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cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(a, b, res);
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cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, b, res);
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return 3;
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}
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