From ed782533b88773430c259c89ed3062a82aa5046a Mon Sep 17 00:00:00 2001 From: normmatt234 Date: Wed, 31 Dec 2008 11:24:55 +0000 Subject: [PATCH] Reduce code required for some flag calculations in two opcode's. (Shouldn't break things but best too do more testing before adding to release branch). --- desmume/src/arm_instructions.cpp | 4 ++-- desmume/src/thumb_instructions.cpp | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/desmume/src/arm_instructions.cpp b/desmume/src/arm_instructions.cpp index d2b0f1b9d..3b57093bb 100644 --- a/desmume/src/arm_instructions.cpp +++ b/desmume/src/arm_instructions.cpp @@ -1162,8 +1162,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_IMM_VAL() }\ cpu->CPSR.bits.N = BIT31(cpu->R[REG_POS(i,12)]);\ cpu->CPSR.bits.Z = (cpu->R[REG_POS(i,12)]==0);\ - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\ - cpu->CPSR.bits.V = SIGNED_OVERFLOW(shift_op, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(v, tmp, cpu->R[REG_POS(i,12)]);\ + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(tmp, cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \ + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(tmp, cpu->CPSR.bits.C, cpu->R[REG_POS(i,12)]); \ return a; \ } diff --git a/desmume/src/thumb_instructions.cpp b/desmume/src/thumb_instructions.cpp index 9b365b14e..e6efdc87b 100644 --- a/desmume/src/thumb_instructions.cpp +++ b/desmume/src/thumb_instructions.cpp @@ -334,8 +334,8 @@ TEMPLATE static u32 FASTCALL OP_ADC_REG() cpu->CPSR.bits.N = BIT31(res); cpu->CPSR.bits.Z = res == 0; - cpu->CPSR.bits.C = UNSIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | UNSIGNED_OVERFLOW(tmp, a, res); - cpu->CPSR.bits.V = SIGNED_OVERFLOW(b, (u32) cpu->CPSR.bits.C, tmp) | SIGNED_OVERFLOW(tmp, a, res); + cpu->CPSR.bits.C = !UNSIGNED_UNDERFLOW(a, b, res); + cpu->CPSR.bits.V = SIGNED_UNDERFLOW(a, b, res); return 3; }