core: fix a bug in sqrt (and probably div) control register emulation which permitted user to overwrite busy flag. fixes games with sensitivities to div/sqrt timing which would sometimes break when interrupted during their math busy wait loop (sm64)
This commit is contained in:
zeromus
parent
9b5bac0646
commit
ed58f6e1f3
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@ -1,7 +1,4 @@
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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Copyright (C) 2007 shash
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Copyright (C) 2007-2009 DeSmuME team
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@ -935,12 +932,10 @@ void MMU_Reset()
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MMU.divRunning = 0;
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MMU.divResult = 0;
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MMU.divMod = 0;
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MMU.divCnt = 0;
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MMU.divCycles = 0;
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MMU.sqrtRunning = 0;
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MMU.sqrtResult = 0;
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MMU.sqrtCnt = 0;
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MMU.sqrtCycles = 0;
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MMU.SPI_CNT = 0;
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@ -1026,31 +1021,36 @@ char txt[80];
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static void execsqrt() {
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u32 ret;
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u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0);
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u8 mode = MMU_new.sqrt.mode;
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MMU_new.sqrt.busy = 1;
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if (cnt&1) {
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if (mode) {
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u64 v = T1ReadQuad(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
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ret = (u32)isqrt(v);
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} else {
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u32 v = T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B8);
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ret = (u32)isqrt(v);
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}
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//clear the result while the sqrt unit is busy
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//todo - is this right? is it reasonable?
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, 0);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, cnt | 0x8000);
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MMU.sqrtCycles = nds_timer + 26;
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MMU.sqrtResult = ret;
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MMU.sqrtCnt = (cnt & 0x7FFF);
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MMU.sqrtRunning = TRUE;
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NDS_Reschedule();
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}
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static void execdiv() {
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u16 cnt = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280);
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s64 num,den;
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s64 res,mod;
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u8 mode = MMU_new.div.mode;
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MMU_new.div.busy = 1;
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MMU_new.div.div0 = 0;
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switch(cnt&3)
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switch(mode)
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{
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case 0:
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num = (s64) (s32) T1ReadLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x290);
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@ -1075,14 +1075,12 @@ static void execdiv() {
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{
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res = ((num < 0) ? 1 : -1);
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mod = num;
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cnt |= 0x4000;
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cnt &= 0x7FFF;
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MMU_new.div.div0 = 1;
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}
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else
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{
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res = num / den;
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mod = num % den;
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cnt &= 0x3FFF;
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}
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DIVLOG("DIV %08X%08X / %08X%08X = %08X%08X\r\n", (u32)(num>>32), (u32)num,
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@ -1093,11 +1091,9 @@ static void execdiv() {
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, 0);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, 0);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, 0);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280, ((cnt & 0xBFFF) | 0x8000));
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MMU.divResult = res;
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MMU.divMod = mod;
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MMU.divCnt = (cnt & 0x7FFF);
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MMU.divRunning = TRUE;
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NDS_Reschedule();
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}
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@ -2141,6 +2137,11 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
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switch(adr)
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{
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case REG_SQRTCNT: printf("ERROR 8bit SQRTCNT WRITE\n"); return;
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case REG_SQRTCNT+1: printf("ERROR 8bit SQRTCNT WRITE\n"); return;
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case REG_SQRTCNT+2: printf("ERROR 8bit SQRTCNT WRITE\n"); return;
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case REG_SQRTCNT+3: printf("ERROR 8bit SQRTCNT WRITE\n"); return;
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case REG_DISPA_DISP3DCNT:
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{
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u32 &disp3dcnt = MainScreen.gpu->dispx_st->dispA_DISP3DCNT.val;
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@ -2406,40 +2407,50 @@ void FASTCALL _MMU_ARM9_write16(u32 adr, u16 val)
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}
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// Alpha test reference value - Parameters:1
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case 0x04000340:
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case eng_3D_ALPHA_TEST_REF:
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{
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((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x340>>1] = val;
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gfx3d_glAlphaFunc(val);
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return;
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}
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// Clear background color setup - Parameters:2
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case 0x04000350:
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case eng_3D_CLEAR_COLOR:
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{
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((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x350>>1] = val;
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gfx3d_glClearColor(val);
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return;
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}
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// Clear background depth setup - Parameters:2
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case 0x04000354:
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case eng_3D_CLEAR_DEPTH:
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{
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((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x354>>1] = val;
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gfx3d_glClearDepth(val);
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return;
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}
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// Fog Color - Parameters:4b
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case 0x04000358:
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case eng_3D_FOG_COLOR:
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{
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((u16 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x358>>1] = val;
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gfx3d_glFogColor(val);
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return;
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}
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case 0x0400035C:
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case eng_3D_FOG_OFFSET:
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{
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((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][0x40]))[0x35C>>1] = val;
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gfx3d_glFogOffset(val);
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return;
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}
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case REG_DIVCNT:
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MMU_new.div.write16(val);
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execdiv();
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return;
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case REG_SQRTCNT:
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MMU_new.sqrt.write16(val);
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execsqrt();
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return;
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case REG_DISPA_BLDCNT:
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GPU_setBLDCNT(MainScreen.gpu,val) ;
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break ;
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@ -2924,6 +2935,10 @@ void FASTCALL _MMU_ARM9_write32(u32 adr, u32 val)
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switch(adr)
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{
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case REG_SQRTCNT: printf("ERROR 32bit SQRTCNT WRITE\n"); return;
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case REG_DIVCNT: printf("ERROR 32bit DIVCNT WRITE\n"); return;
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case eng_3D_GXSTAT:
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MMU_new.gxstat.write32(val);
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break;
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@ -3239,6 +3254,15 @@ u8 FASTCALL _MMU_ARM9_read08(u32 adr)
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switch(adr)
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{
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case REG_SQRTCNT: printf("ERROR 8bit SQRTCNT READ\n"); return 0;
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case REG_SQRTCNT+1: printf("ERROR 8bit SQRTCNT READ\n"); return 0;
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case REG_SQRTCNT+2: printf("ERROR 8bit SQRTCNT READ\n"); return 0;
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case REG_SQRTCNT+3: printf("ERROR 8bit SQRTCNT READ\n"); return 0;
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case REG_DIVCNT: printf("ERROR 8bit DIVCNT READ\n"); return 0;
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case REG_DIVCNT+1: printf("ERROR 8bit DIVCNT READ\n"); return 0;
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case REG_DIVCNT+2: printf("ERROR 8bit DIVCNT READ\n"); return 0;
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case REG_DIVCNT+3: printf("ERROR 8bit DIVCNT READ\n"); return 0;
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case eng_3D_GXSTAT:
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return MMU_new.gxstat.read(8,adr);
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}
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@ -3271,8 +3295,9 @@ u16 FASTCALL _MMU_ARM9_read16(u32 adr)
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// Address is an IO register
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switch(adr)
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{
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case eng_3D_GXSTAT:
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return MMU_new.gxstat.read(16,adr);
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case REG_SQRTCNT: return MMU_new.sqrt.read16();
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case REG_DIVCNT: return MMU_new.div.read16();
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case eng_3D_GXSTAT: return MMU_new.gxstat.read(16,adr);
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// ============================================= 3D
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case eng_3D_RAM_COUNT:
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@ -3352,50 +3377,53 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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switch(adr)
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{
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case 0x04000640:
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case 0x04000644:
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case 0x04000648:
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case 0x0400064C:
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case 0x04000650:
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case 0x04000654:
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case 0x04000658:
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case 0x0400065C:
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case 0x04000660:
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case 0x04000664:
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case 0x04000668:
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case 0x0400066C:
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case 0x04000670:
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case 0x04000674:
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case 0x04000678:
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case 0x0400067C:
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case REG_SQRTCNT: printf("ERROR 32bit SQRTCNT READ\n"); return 0;
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case REG_DIVCNT: printf("ERROR 32bit DIVCNT READ\n"); return 0;
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case eng_3D_CLIPMTX_RESULT:
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case eng_3D_CLIPMTX_RESULT+4:
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case eng_3D_CLIPMTX_RESULT+8:
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case eng_3D_CLIPMTX_RESULT+12:
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case eng_3D_CLIPMTX_RESULT+16:
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case eng_3D_CLIPMTX_RESULT+20:
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case eng_3D_CLIPMTX_RESULT+24:
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case eng_3D_CLIPMTX_RESULT+28:
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case eng_3D_CLIPMTX_RESULT+32:
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case eng_3D_CLIPMTX_RESULT+36:
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case eng_3D_CLIPMTX_RESULT+40:
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case eng_3D_CLIPMTX_RESULT+44:
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case eng_3D_CLIPMTX_RESULT+48:
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case eng_3D_CLIPMTX_RESULT+52:
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case eng_3D_CLIPMTX_RESULT+56:
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case eng_3D_CLIPMTX_RESULT+60:
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{
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//LOG("4000640h..67Fh - CLIPMTX_RESULT - Read Current Clip Coordinates Matrix (R)");
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return gfx3d_GetClipMatrix ((adr-0x04000640)/4);
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}
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case 0x04000680:
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case 0x04000684:
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case 0x04000688:
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case 0x0400068C:
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case 0x04000690:
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case 0x04000694:
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case 0x04000698:
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case 0x0400069C:
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case 0x040006A0:
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case eng_3D_VECMTX_RESULT:
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case eng_3D_VECMTX_RESULT+4:
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case eng_3D_VECMTX_RESULT+8:
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case eng_3D_VECMTX_RESULT+12:
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case eng_3D_VECMTX_RESULT+16:
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case eng_3D_VECMTX_RESULT+20:
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case eng_3D_VECMTX_RESULT+24:
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case eng_3D_VECMTX_RESULT+28:
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case eng_3D_VECMTX_RESULT+32:
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{
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//LOG("4000680h..6A3h - VECMTX_RESULT - Read Current Directional Vector Matrix (R)");
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return gfx3d_GetDirectionalMatrix ((adr-0x04000680)/4);
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}
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case 0x4000604:
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case eng_3D_RAM_COUNT:
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{
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return (gfx3d_GetNumPolys()) | ((gfx3d_GetNumVertex()) << 16);
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//LOG ("read32 - RAM_COUNT -> 0x%X", ((u32 *)(MMU.MMU_MEM[ARMCPU_ARM9][(adr>>20)&0xFF]))[(adr&MMU.MMU_MASK[ARMCPU_ARM9][(adr>>20)&0xFF])>>2]);
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}
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case 0x04000620:
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case 0x04000624:
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case 0x04000628:
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case 0x0400062C:
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case eng_3D_POS_RESULT:
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case eng_3D_POS_RESULT+4:
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case eng_3D_POS_RESULT+8:
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case eng_3D_POS_RESULT+12:
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{
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return gfx3d_glGetPosRes((adr & 0xF) >> 2);
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}
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@ -3420,18 +3448,8 @@ u32 FASTCALL _MMU_ARM9_read32(u32 adr)
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u32 val = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], (adr + 2) & 0xFFF);
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return MMU.timer[ARMCPU_ARM9][(adr&0xF)>>2] | (val<<16);
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}
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/*
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case 0x04000640 : // TODO (clear): again, ???
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LOG("read proj\r\n");
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return 0;
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case 0x04000680 :
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LOG("read roat\r\n");
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return 0;
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case 0x04000620 :
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LOG("point res\r\n");
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return 0;
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*/
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case REG_GCDATAIN:
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case REG_GCDATAIN:
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return MMU_readFromGC<ARMCPU_ARM9>();
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}
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return T1ReadLong_guaranteedAligned(MMU.MMU_MEM[ARMCPU_ARM9][0x40], adr & MMU.MMU_MASK[ARMCPU_ARM9][(adr >> 20)]);
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@ -1,7 +1,4 @@
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/* Copyright (C) 2006 yopyop
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yopyop156@ifrance.com
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yopyop156.ifrance.com
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Copyright (C) 2007 shash
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Copyright (C) 2007-2009 DeSmuME team
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@ -30,6 +27,7 @@
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#include "registers.h"
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#include "mc.h"
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#include "bits.h"
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#include "readwrite.h"
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#ifdef HAVE_LUA
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#include "lua-engine.h"
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#endif
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@ -77,7 +75,9 @@ enum EDMADestinationUpdate
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EDMADestinationUpdate_IncrementReload = 3,
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};
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//TODO
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//n.b. this may be a bad idea, for complex registers like the dma control register.
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//we need to know exactly what part was written to, instead of assuming all 32bits were written.
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class TRegister_32
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{
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public:
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@ -131,6 +131,60 @@ struct TGXSTAT : public TRegister_32
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void triggerDma(EDMAMode mode);
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class DivController
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{
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public:
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DivController()
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: mode(0), busy(0)
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{}
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void exec();
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u8 mode, busy, div0;
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u16 read16() { return mode|(busy<<15)|(div0<<14); }
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void write16(u16 val) {
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mode = val&3;
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//todo - do we clear the div0 flag here or is that strictly done by the divider unit?
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}
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void savestate(EMUFILE* os)
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{
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write8le(&mode,os);
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write8le(&busy,os);
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write8le(&div0,os);
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}
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bool loadstate(EMUFILE* is, int version)
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{
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int ret = 1;
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ret &= read8le(&mode,is);
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ret &= read8le(&busy,is);
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ret &= read8le(&div0,is);
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return ret==1;
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}
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};
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class SqrtController
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{
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public:
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SqrtController()
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: mode(0), busy(0)
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{}
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void exec();
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u8 mode, busy;
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u16 read16() { return mode|(busy<<15); }
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void write16(u16 val) { mode = val&1; }
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void savestate(EMUFILE* os)
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{
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write8le(&mode,os);
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write8le(&busy,os);
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}
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bool loadstate(EMUFILE* is, int version)
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{
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int ret=1;
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ret &= read8le(&mode,is);
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ret &= read8le(&busy,is);
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return ret==1;
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}
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};
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class DmaController
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{
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public:
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@ -334,12 +388,10 @@ struct MMU_struct
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BOOL divRunning;
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s64 divResult;
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s64 divMod;
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u32 divCnt;
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u64 divCycles;
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BOOL sqrtRunning;
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u32 sqrtResult;
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u32 sqrtCnt;
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u64 sqrtCycles;
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u16 SPI_CNT;
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@ -365,6 +417,8 @@ struct MMU_struct_new
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BackupDevice backupDevice;
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DmaController dma[2][4];
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TGXSTAT gxstat;
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SqrtController sqrt;
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DivController div;
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void write_dma(const int proc, const int size, const u32 adr, const u32 val);
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u32 read_dma(const int proc, const int size, const u32 adr);
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@ -1777,11 +1777,11 @@ struct TSequenceItem_divider : public TSequenceItem
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void exec()
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{
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IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[2]++);
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MMU_new.div.busy = 0;
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A0, (u32)MMU.divResult);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A4, (u32)(MMU.divResult >> 32));
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2A8, (u32)MMU.divMod);
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T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2AC, (u32)(MMU.divMod >> 32));
|
||||
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x280, MMU.divCnt);
|
||||
MMU.divRunning = FALSE;
|
||||
}
|
||||
|
||||
|
|
@ -1804,8 +1804,8 @@ struct TSequenceItem_sqrtunit : public TSequenceItem
|
|||
FORCEINLINE void exec()
|
||||
{
|
||||
IF_DEVELOPER(DEBUG_statistics.sequencerExecutionCounters[3]++);
|
||||
MMU_new.sqrt.busy = 0;
|
||||
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B4, MMU.sqrtResult);
|
||||
T1WriteLong(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x2B0, MMU.sqrtCnt);
|
||||
MMU.sqrtRunning = FALSE;
|
||||
}
|
||||
|
||||
|
|
@ -2254,7 +2254,7 @@ bool nds_loadstate(EMUFILE* is, int size)
|
|||
|
||||
//#define LOG_ARM9
|
||||
//#define LOG_ARM7
|
||||
//static bool dolog = true;
|
||||
//bool dolog = true;
|
||||
|
||||
FORCEINLINE void arm9log()
|
||||
{
|
||||
|
|
@ -2267,8 +2267,8 @@ FORCEINLINE void arm9log()
|
|||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM9.instruction)](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, dasmbuf);
|
||||
|
||||
printf("%05d %12lld 9:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
|
||||
currFrameCounter, nds_timer,
|
||||
printf("%05d:%03d %12lld 9:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
|
||||
currFrameCounter, nds.VCount, nds_timer,
|
||||
NDS_ARM9.instruct_adr,NDS_ARM9.instruction, dasmbuf,
|
||||
NDS_ARM9.R[0], NDS_ARM9.R[1], NDS_ARM9.R[2], NDS_ARM9.R[3], NDS_ARM9.R[4], NDS_ARM9.R[5], NDS_ARM9.R[6], NDS_ARM9.R[7],
|
||||
NDS_ARM9.R[8], NDS_ARM9.R[9], NDS_ARM9.R[10], NDS_ARM9.R[11], NDS_ARM9.R[12], NDS_ARM9.R[13], NDS_ARM9.R[14], NDS_ARM9.R[15]);
|
||||
|
|
@ -2287,8 +2287,8 @@ FORCEINLINE void arm7log()
|
|||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM7.instruction)](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, dasmbuf);
|
||||
|
||||
printf("%05d %12lld 7:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
|
||||
currFrameCounter, nds_timer,
|
||||
printf("%05d:%03d %12lld 7:%08X %08X %-30s R00:%08X R01:%08X R02:%08X R03:%08X R04:%08X R05:%08X R06:%08X R07:%08X R08:%08X R09:%08X R10:%08X R11:%08X R12:%08X R13:%08X R14:%08X R15:%08X\n",
|
||||
currFrameCounter, nds.VCount, nds_timer,
|
||||
NDS_ARM7.instruct_adr,NDS_ARM7.instruction, dasmbuf,
|
||||
NDS_ARM7.R[0], NDS_ARM7.R[1], NDS_ARM7.R[2], NDS_ARM7.R[3], NDS_ARM7.R[4], NDS_ARM7.R[5], NDS_ARM7.R[6], NDS_ARM7.R[7],
|
||||
NDS_ARM7.R[8], NDS_ARM7.R[9], NDS_ARM7.R[10], NDS_ARM7.R[11], NDS_ARM7.R[12], NDS_ARM7.R[13], NDS_ARM7.R[14], NDS_ARM7.R[15]);
|
||||
|
|
|
|||
|
|
@ -28,6 +28,7 @@
|
|||
|
||||
//well. just for the sake of consistency
|
||||
int write8le(u8 b, EMUFILE *fp);
|
||||
inline int write8le(u8* b, EMUFILE *fp) { return write8le(*b,fp); }
|
||||
int write16le(u16 b, EMUFILE* os);
|
||||
int write32le(u32 b, EMUFILE* os);
|
||||
int write64le(u64 b, EMUFILE* os);
|
||||
|
|
|
|||
|
|
@ -205,12 +205,10 @@ SFORMAT SF_MMU[]={
|
|||
{ "MDV1", 4, 1, &MMU.divRunning},
|
||||
{ "MDV2", 8, 1, &MMU.divResult},
|
||||
{ "MDV3", 8, 1, &MMU.divMod},
|
||||
{ "MDV4", 4, 1, &MMU.divCnt},
|
||||
{ "MDV5", 8, 1, &MMU.divCycles},
|
||||
|
||||
{ "MSQ1", 4, 1, &MMU.sqrtRunning},
|
||||
{ "MSQ2", 4, 1, &MMU.sqrtResult},
|
||||
{ "MSQ3", 4, 1, &MMU.sqrtCnt},
|
||||
{ "MSQ4", 8, 1, &MMU.sqrtCycles},
|
||||
|
||||
//begin memory chips
|
||||
|
|
@ -254,7 +252,7 @@ SFORMAT SF_MOVIE[]={
|
|||
|
||||
static void mmu_savestate(EMUFILE* os)
|
||||
{
|
||||
u32 version = 3;
|
||||
u32 version = 4;
|
||||
write32le(version,os);
|
||||
|
||||
//version 2:
|
||||
|
|
@ -272,6 +270,10 @@ static void mmu_savestate(EMUFILE* os)
|
|||
MMU_timing.arm7dataFetch.savestate(os, version);
|
||||
MMU_timing.arm9codeCache.savestate(os, version);
|
||||
MMU_timing.arm9dataCache.savestate(os, version);
|
||||
|
||||
//version 4:
|
||||
MMU_new.sqrt.savestate(os);
|
||||
MMU_new.div.savestate(os);
|
||||
}
|
||||
|
||||
SFORMAT SF_WIFI[]={
|
||||
|
|
@ -414,13 +416,11 @@ static bool mmu_loadstate(EMUFILE* is, int size)
|
|||
if(is->fail()) return false;
|
||||
}
|
||||
|
||||
if(version < 2)
|
||||
return true;
|
||||
if(version < 2) return true;
|
||||
|
||||
bool ok = MMU_new.backupDevice.load_state(is);
|
||||
|
||||
if(version < 3)
|
||||
return true;
|
||||
if(version < 3) return true;
|
||||
|
||||
ok &= MMU_new.gxstat.loadstate(is);
|
||||
|
||||
|
|
@ -435,6 +435,11 @@ static bool mmu_loadstate(EMUFILE* is, int size)
|
|||
ok &= MMU_timing.arm9codeCache.loadstate(is, version);
|
||||
ok &= MMU_timing.arm9dataCache.loadstate(is, version);
|
||||
|
||||
if(version < 4) return true;
|
||||
|
||||
ok &= MMU_new.sqrt.loadstate(is,version);
|
||||
ok &= MMU_new.div.loadstate(is,version);
|
||||
|
||||
return ok;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue