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MMU: support 8-bit write to REG_IPCSYNC

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lifehackerhansol 2024-11-14 14:49:17 -08:00
parent 1192bf6f2c
commit c1624b2b33
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GPG Key ID: 80FB184AFC0B3B0E
1 changed files with 30 additions and 1 deletions
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29
desmume/src/MMU.cpp
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@ -3755,6 +3755,20 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val)
MMU_new.gxstat.write(8,adr,val);
break;
case REG_IPCSYNC:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180);
ipcsync &= 0xFF00;
ipcsync |= (val & 0xFF);
MMU_IPCSync(ARMCPU_ARM9, ipcsync);
}
case REG_IPCSYNC+1:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180);
ipcsync &= 0x00FF;
ipcsync |= ((val & 0xFF) << 8);
MMU_IPCSync(ARMCPU_ARM9, ipcsync);
}
case REG_AUXSPICNT:
case REG_AUXSPICNT+1:
write_auxspicnt(ARMCPU_ARM9, 8, adr & 1, val);
@ -5596,6 +5610,21 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val)
printf("Unsupported 8bit write to timer registers");
return;
case REG_IPCSYNC:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180);
ipcsync &= 0xFF00;
ipcsync |= (val & 0xFF);
MMU_IPCSync(ARMCPU_ARM7, ipcsync);
}
case REG_IPCSYNC+1:
{
u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180);
ipcsync &= 0x00FF;
ipcsync |= ((val & 0xFF) << 8);
MMU_IPCSync(ARMCPU_ARM7, ipcsync);
}
case REG_AUXSPIDATA:
{
//if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF; //zero 20-aug-2013 - this seems pointless