From c1624b2b335e8203e58b6863bea89c87bdf4d4f6 Mon Sep 17 00:00:00 2001 From: lifehackerhansol Date: Thu, 14 Nov 2024 14:49:17 -0800 Subject: [PATCH] MMU: support 8-bit write to REG_IPCSYNC --- desmume/src/MMU.cpp | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/desmume/src/MMU.cpp b/desmume/src/MMU.cpp index a09cc24b5..28cadaa30 100644 --- a/desmume/src/MMU.cpp +++ b/desmume/src/MMU.cpp @@ -3754,7 +3754,21 @@ void FASTCALL _MMU_ARM9_write08(u32 adr, u8 val) case eng_3D_GXSTAT: MMU_new.gxstat.write(8,adr,val); break; - + + case REG_IPCSYNC: + { + u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180); + ipcsync &= 0xFF00; + ipcsync |= (val & 0xFF); + MMU_IPCSync(ARMCPU_ARM9, ipcsync); + } + case REG_IPCSYNC+1: + { + u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM9][0x40], 0x180); + ipcsync &= 0x00FF; + ipcsync |= ((val & 0xFF) << 8); + MMU_IPCSync(ARMCPU_ARM9, ipcsync); + } case REG_AUXSPICNT: case REG_AUXSPICNT+1: write_auxspicnt(ARMCPU_ARM9, 8, adr & 1, val); @@ -5596,6 +5610,21 @@ void FASTCALL _MMU_ARM7_write08(u32 adr, u8 val) printf("Unsupported 8bit write to timer registers"); return; + case REG_IPCSYNC: + { + u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180); + ipcsync &= 0xFF00; + ipcsync |= (val & 0xFF); + MMU_IPCSync(ARMCPU_ARM7, ipcsync); + } + case REG_IPCSYNC+1: + { + u16 ipcsync = T1ReadWord(MMU.MMU_MEM[ARMCPU_ARM7][0x40], 0x180); + ipcsync &= 0x00FF; + ipcsync |= ((val & 0xFF) << 8); + MMU_IPCSync(ARMCPU_ARM7, ipcsync); + } + case REG_AUXSPIDATA: { //if(val!=0) MMU.AUX_SPI_CMD = val & 0xFF; //zero 20-aug-2013 - this seems pointless