- Removed the bug report link with a define, to avoid reports from betas/external builds
- Added the version on window bar to recognize versions from screenshots - Added "high-level" check for DMAs and Timer for minor (really minor) speed up - Changed instruction execution to 16 at a time blocks (tested and stable) - Really minor memory access speed up (mainly added for clarity), gives up to 33% gain - Added transparency and fixed material alpha support and alpha testing on the 3D core - Changed how depth initial values are calculated (fixes SM64DS skybox) - Changed written pixels check on the 3D core to use the depth buffer, as I'll need the stencil buffer for shadows - Added my real name to my nick, as I prefer my work properly credited :P
This commit is contained in:
parent
dfaaadbef7
commit
b37b7dff49
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@ -11,7 +11,7 @@ delfare
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Guillaume Duhamel
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Normmatt
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Romain Vallet
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shash
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Bernat Muñoz (shash)
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Theo Berkau
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thoduv
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Tim Seidel (Mighty Max)
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@ -1,9 +1,18 @@
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0.8 -> ?
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Mac OS X:
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General/Core:
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- Added "high-level" check for DMAs and Timer for minor (really minor) speed up [shash]
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- Changed instruction execution to 16 at a time blocks (tested and stable) [shash]
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- Really minor memory access speed up (mainly added for clarity) [shash]
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- Added transparency and fixed material alpha support and alpha testing on the 3D core [shash]
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- Changed how depth initial values are calculated (fixes SM64DS skybox) [shash]
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Mac OS X port:
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- Fixed: Filenames and paths with unicode characters now work. [Jeff]
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- Fixed: Load state from file button works again. [Jeff]
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- Save State panel now pauses emulation while the file selection box is open. [Jeff]
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Windows port:
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- Removed the bug report link with a define, to avoid reports from betas/external builds [shash]
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- Added the version on window bar to recognize versions from screenshots [shash]
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0.7.3 -> 0.8
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Cocoa:
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- Save State As function now works. [Jeff B]
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@ -582,7 +582,7 @@ u8 FASTCALL MMU_read8(u32 proc, u32 adr)
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}
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#endif
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return MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]];
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return MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]];
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}
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@ -838,15 +838,15 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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adr &= 0x0FFFFFFF;
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// This is bad, remove it
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if(proc == ARMCPU_ARM7)
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// This is bad, remove it
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if(proc == ARMCPU_ARM7)
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{
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if ((adr>=0x04000400)&&(adr<0x0400051D))
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{
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if ((adr>=0x04000400)&&(adr<0x0400051D))
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{
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SPU_WriteByte(adr, val);
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return;
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}
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SPU_WriteByte(adr, val);
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return;
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}
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}
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if (adr & 0xFF800000 == 0x04800000)
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{
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@ -1188,7 +1188,8 @@ void FASTCALL MMU_write8(u32 proc, u32 adr, u8 val)
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break;
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}
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MMU.MMU_MEM[proc][(adr>>20)&0xFF][adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF]]=val;
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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MMU.MMU_MEM[proc][adr>>20][adr&MMU.MMU_MASK[proc][adr>>20]]=val;
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}
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u16 partie = 1;
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@ -1639,44 +1640,55 @@ void FASTCALL MMU_write16(u32 proc, u32 adr, u16 val)
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T1WriteWord(MMU.MMU_MEM[proc][0x40], 0x184, T1ReadWord(MMU.MMU_MEM[proc][0x40], 0x184) | (val & 0xBFF4));
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}
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return;
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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case REG_TM3CNTL :
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case REG_TM0CNTL :
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case REG_TM1CNTL :
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case REG_TM2CNTL :
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case REG_TM3CNTL :
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MMU.timerReload[proc][(adr>>2)&3] = val;
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return;
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case REG_TM0CNTH :
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case REG_TM1CNTH :
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case REG_TM2CNTH :
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case REG_TM3CNTH :
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case REG_TM0CNTH :
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case REG_TM1CNTH :
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case REG_TM2CNTH :
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case REG_TM3CNTH :
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{
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int timerIndex = ((adr-2)>>2)&0x3;
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int mask = ((val&0x80)>>7) << (timerIndex+(proc<<2));
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MMU.CheckTimers = (MMU.CheckTimers & (~mask)) | mask;
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if(val&0x80)
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{
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MMU.timer[proc][((adr-2)>>2)&0x3] = MMU.timerReload[proc][((adr-2)>>2)&0x3];
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MMU.timer[proc][timerIndex] = MMU.timerReload[proc][((adr-2)>>2)&0x3];
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}
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MMU.timerON[proc][((adr-2)>>2)&0x3] = val & 0x80;
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MMU.timerON[proc][((adr-2)>>2)&0x3] = val & 0x80;
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switch(val&7)
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{
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case 0 :
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MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 0+1;//proc;
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break;
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case 1 :
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MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 6+1;//proc;
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break;
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case 2 :
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MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 8+1;//proc;
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break;
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case 3 :
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MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 10+1;//proc;
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break;
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default :
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MMU.timerMODE[proc][((adr-2)>>2)&0x3] = 0xFFFF;
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break;
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case 0 :
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MMU.timerMODE[proc][timerIndex] = 0+1;//proc;
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break;
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case 1 :
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MMU.timerMODE[proc][timerIndex] = 6+1;//proc;
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break;
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case 2 :
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MMU.timerMODE[proc][timerIndex] = 8+1;//proc;
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break;
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case 3 :
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MMU.timerMODE[proc][timerIndex] = 10+1;//proc;
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break;
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default :
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MMU.timerMODE[proc][timerIndex] = 0xFFFF;
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break;
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}
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if(!(val & 0x80))
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MMU.timerRUN[proc][((adr-2)>>2)&0x3] = FALSE;
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MMU.timerRUN[proc][timerIndex] = FALSE;
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T1WriteWord(MMU.MMU_MEM[proc][0x40], adr & 0xFFF, val);
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return;
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case REG_DISPA_DISPCNT+2 :
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}
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case REG_DISPA_DISPCNT+2 :
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{
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//execute = FALSE;
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u32 v = (T1ReadLong(MMU.MMU_MEM[proc][0x40], 0) & 0xFFFF) | ((u32) val << 16);
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return;
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//case REG_AUXSPICNT : execute = FALSE;
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default :
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T1WriteWord(MMU.MMU_MEM[proc][0x40], adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF], val);
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T1WriteWord(MMU.MMU_MEM[proc][0x40], adr&MMU.MMU_MASK[proc][adr>>20], val);
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return;
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}
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}
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T1WriteWord(MMU.MMU_MEM[proc][(adr>>20)&0xFF], adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF], val);
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// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
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T1WriteWord(MMU.MMU_MEM[proc][adr>>20], adr&MMU.MMU_MASK[proc][adr>>20], val);
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}
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@ -1832,22 +1846,21 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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adr &= 0x0FFFFFFF;
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// This is bad, remove it
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if(proc == ARMCPU_ARM7)
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// This is bad, remove it
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if(proc == ARMCPU_ARM7)
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{
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if ((adr>=0x04000400)&&(adr<0x0400051D))
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{
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if ((adr>=0x04000400)&&(adr<0x0400051D))
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{
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SPU_WriteLong(adr, val);
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return;
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}
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SPU_WriteLong(adr, val);
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return;
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}
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}
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if (adr & 0xFF800000 == 0x04800000) {
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/* access to non regular hw registers */
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/* return to not overwrite valid data */
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return ;
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} ;
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if (adr & 0xFF800000 == 0x04800000) {
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/* access to non regular hw registers */
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/* return to not overwrite valid data */
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return ;
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}
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if((adr>>24)==4)
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{
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@ -2291,88 +2304,8 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
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}
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break;
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}
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/*
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// Commented out, as this doesn't use the plug-in system, neither works
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case cmd_3D_MTX_MODE // 0x04000440 :
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if (proc == ARMCPU_ARM9) gl_MTX_MODE(val);
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return;
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case cmd_3D_MTX_PUSH // 0x04000444 :
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case cmd_3D_MTX_POP // 0x04000448 :
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case cmd_3D_MTX_STORE // 0x0400044C :
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case cmd_3D_MTX_RESTORE // 0x04000450 :
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if (proc == ARMCPU_ARM9) gl_print_cmd(adr);
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return;
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case cmd_3D_MTX_IDENTITY // 0x04000454 :
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if (proc == ARMCPU_ARM9) gl_MTX_IDENTITY();
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return;
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case cmd_3D_MTX_LOAD_4x4 // 0x04000458 :
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if (proc == ARMCPU_ARM9) gl_MTX_LOAD_4x4(val);
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return;
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case cmd_3D_MTX_LOAD_4x3 // 0x0400045C :
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if (proc == ARMCPU_ARM9) gl_MTX_LOAD_4x3(val);
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return;
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case cmd_3D_MTX_MULT_4x4 // 0x04000460 :
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if (proc == ARMCPU_ARM9) gl_MTX_MULT_4x4(val);
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return;
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case cmd_3D_MTX_MULT_4x3 // 0x04000464 :
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if (proc == ARMCPU_ARM9) gl_MTX_MULT_4x3(val);
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return;
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case cmd_3D_MTX_MULT_3x3 // 0x04000468 :
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if (proc == ARMCPU_ARM9) gl_MTX_MULT_3x3(val);
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return;
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case cmd_3D_MTX_SCALE // 0x0400046C :
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case cmd_3D_MTX_TRANS // 0x04000470 :
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case cmd_3D_COLOR // 0x04000480 :
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case cmd_3D_NORMA // 0x04000484 :
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if (proc == ARMCPU_ARM9) gl_print_cmd(adr);
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return;
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case cmd_3D_TEXCOORD // 0x04000488 :
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if (proc == ARMCPU_ARM9) gl_TEXCOORD(val);
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return;
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case cmd_3D_VTX_16 // 0x0400048C :
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if (proc == ARMCPU_ARM9) gl_VTX_16(val);
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return;
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case cmd_3D_VTX_10 // 0x04000490 :
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if (proc == ARMCPU_ARM9) gl_VTX_10(val);
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return;
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case cmd_3D_VTX_XY // 0x04000494 :
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if (proc == ARMCPU_ARM9) gl_VTX_XY(val);
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return;
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case cmd_3D_VTX_XZ // 0x04000498 :
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if (proc == ARMCPU_ARM9) gl_VTX_XZ(val);
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return;
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case cmd_3D_VTX_YZ // 0x0400049C :
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if (proc == ARMCPU_ARM9) gl_VTX_YZ(val);
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return;
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case cmd_3D_VTX_DIFF // 0x040004A0 :
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if (proc == ARMCPU_ARM9) gl_VTX_DIFF(val);
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||||
return;
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case cmd_3D_POLYGON_ATTR // 0x040004A4 :
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case cmd_3D_TEXIMAGE_PARAM // 0x040004A8 :
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||||
case cmd_3D_PLTT_BASE // 0x040004AC :
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case cmd_3D_DIF_AMB // 0x040004C0 :
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case cmd_3D_SPE_EMI // 0x040004C4 :
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||||
case cmd_3D_LIGHT_VECTOR // 0x040004C8 :
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case cmd_3D_LIGHT_COLOR // 0x040004CC :
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case cmd_3D_SHININESS // 0x040004D0 :
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||||
if (proc == ARMCPU_ARM9) gl_print_cmd(adr);
|
||||
return;
|
||||
case cmd_3D_BEGIN_VTXS // 0x04000500 :
|
||||
if (proc == ARMCPU_ARM9) gl_VTX_begin(val);
|
||||
return;
|
||||
case cmd_3D_END_VTXS // 0x04000504 :
|
||||
if (proc == ARMCPU_ARM9) gl_VTX_end();
|
||||
return;
|
||||
case cmd_3D_SWAP_BUFFERS // 0x04000540 :
|
||||
case cmd_3D_VIEWPORT // 0x04000580 :
|
||||
case cmd_3D_BOX_TEST // 0x040005C0 :
|
||||
case cmd_3D_POS_TEST // 0x040005C4 :
|
||||
case cmd_3D_VEC_TEST // 0x040005C8 :
|
||||
if (proc == ARMCPU_ARM9) gl_print_cmd(adr);
|
||||
return;
|
||||
*/
|
||||
case REG_DISPA_DISPCNT :
|
||||
if(proc == ARMCPU_ARM9) GPU_setVideoProp(MainScreen.gpu, val);
|
||||
case REG_DISPA_DISPCNT :
|
||||
if(proc == ARMCPU_ARM9) GPU_setVideoProp(MainScreen.gpu, val);
|
||||
|
||||
//GPULOG("MAIN INIT 32B %08X\r\n", val);
|
||||
T1WriteLong(MMU.MMU_MEM[proc][0x40], 0, val);
|
||||
|
@ -2423,41 +2356,48 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
|
|||
case REG_IF :
|
||||
MMU.reg_IF[proc] &= (~val);
|
||||
return;
|
||||
case REG_TM0CNTL :
|
||||
case REG_TM1CNTL :
|
||||
case REG_TM2CNTL :
|
||||
case REG_TM3CNTL :
|
||||
MMU.timerReload[proc][(adr>>2)&0x3] = (u16)val;
|
||||
|
||||
case REG_TM0CNTL:
|
||||
case REG_TM1CNTL:
|
||||
case REG_TM2CNTL:
|
||||
case REG_TM3CNTL:
|
||||
{
|
||||
int timerIndex = (adr>>2)&0x3;
|
||||
int mask = ((val & 0x800000)>>(16+7)) << (timerIndex+(proc<<2));
|
||||
MMU.CheckTimers = (MMU.CheckTimers & (~mask)) | mask;
|
||||
|
||||
MMU.timerReload[proc][timerIndex] = (u16)val;
|
||||
if(val&0x800000)
|
||||
{
|
||||
MMU.timer[proc][(adr>>2)&0x3] = MMU.timerReload[proc][(adr>>2)&0x3];
|
||||
MMU.timer[proc][timerIndex] = MMU.timerReload[proc][(adr>>2)&0x3];
|
||||
}
|
||||
MMU.timerON[proc][(adr>>2)&0x3] = val & 0x800000;
|
||||
MMU.timerON[proc][timerIndex] = val & 0x800000;
|
||||
switch((val>>16)&7)
|
||||
{
|
||||
case 0 :
|
||||
MMU.timerMODE[proc][(adr>>2)&0x3] = 0+1;//proc;
|
||||
MMU.timerMODE[proc][timerIndex] = 0+1;//proc;
|
||||
break;
|
||||
case 1 :
|
||||
MMU.timerMODE[proc][(adr>>2)&0x3] = 6+1;//proc;
|
||||
MMU.timerMODE[proc][timerIndex] = 6+1;//proc;
|
||||
break;
|
||||
case 2 :
|
||||
MMU.timerMODE[proc][(adr>>2)&0x3] = 8+1;//proc;
|
||||
MMU.timerMODE[proc][timerIndex] = 8+1;//proc;
|
||||
break;
|
||||
case 3 :
|
||||
MMU.timerMODE[proc][(adr>>2)&0x3] = 10+1;//proc;
|
||||
MMU.timerMODE[proc][timerIndex] = 10+1;//proc;
|
||||
break;
|
||||
default :
|
||||
MMU.timerMODE[proc][(adr>>2)&0x3] = 0xFFFF;
|
||||
MMU.timerMODE[proc][timerIndex] = 0xFFFF;
|
||||
break;
|
||||
}
|
||||
if(!(val & 0x800000))
|
||||
{
|
||||
MMU.timerRUN[proc][(adr>>2)&0x3] = FALSE;
|
||||
MMU.timerRUN[proc][timerIndex] = FALSE;
|
||||
}
|
||||
T1WriteLong(MMU.MMU_MEM[proc][0x40], adr & 0xFFF, val);
|
||||
return;
|
||||
case REG_DIVDENOM :
|
||||
}
|
||||
case REG_DIVDENOM :
|
||||
{
|
||||
u16 cnt;
|
||||
s64 num = 0;
|
||||
|
@ -2841,11 +2781,13 @@ void FASTCALL MMU_write32(u32 proc, u32 adr, u32 val)
|
|||
//case 0x21FDFF0 : if(val==0) execute = FALSE;
|
||||
//case 0x21FDFB0 : if(val==0) execute = FALSE;
|
||||
default :
|
||||
T1WriteLong(MMU.MMU_MEM[proc][0x40], adr & MMU.MMU_MASK[proc][(adr>>20)&0xFF], val);
|
||||
T1WriteLong(MMU.MMU_MEM[proc][0x40], adr & MMU.MMU_MASK[proc][adr>>20], val);
|
||||
return;
|
||||
}
|
||||
}
|
||||
T1WriteLong(MMU.MMU_MEM[proc][(adr>>20)&0xFF], adr&MMU.MMU_MASK[proc][(adr>>20)&0xFF], val);
|
||||
|
||||
// Removed the &0xFF as they are implicit with the adr&0x0FFFFFFFF [shash]
|
||||
T1WriteLong(MMU.MMU_MEM[proc][adr>>20], adr&MMU.MMU_MASK[proc][adr>>20], val);
|
||||
}
|
||||
|
||||
|
||||
|
@ -2887,6 +2829,7 @@ void FASTCALL MMU_doDMA(u32 proc, u32 num)
|
|||
|
||||
MMU.DMACycle[proc][num] = taille + nds.cycles;
|
||||
MMU.DMAing[proc][num] = TRUE;
|
||||
MMU.CheckDMAs |= (1<<(num+(proc<<2)));
|
||||
|
||||
DMALOG("proc %d, dma %d src %08X dst %08X start %d taille %d repeat %s %08X\r\n",
|
||||
proc, num, src, dst, MMU.DMAStartTime[proc][num], taille,
|
||||
|
|
|
@ -97,7 +97,9 @@ typedef struct {
|
|||
memory_chip_t fw;
|
||||
memory_chip_t bupmem;
|
||||
|
||||
nds_dscard dscard[2];
|
||||
nds_dscard dscard[2];
|
||||
u32 CheckTimers;
|
||||
u32 CheckDMAs;
|
||||
|
||||
} MMU_struct;
|
||||
|
||||
|
|
|
@ -823,62 +823,74 @@ int NDS_LoadFirmware(const char *filename)
|
|||
u32
|
||||
NDS_exec(s32 nb, BOOL force)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
nb += nds.cycles;//(nds.cycles>>26)<<26;
|
||||
|
||||
for(; (nb >= nds.cycles) && ((force)||(execute)); )
|
||||
{
|
||||
if(nds.ARM9Cycle<=nds.cycles)
|
||||
{
|
||||
for (j = 0; j < 4 && (!force); j++)
|
||||
{
|
||||
if(nds.ARM9Cycle<=nds.cycles)
|
||||
{
|
||||
#ifdef LOG_ARM9
|
||||
if(logcount==3){
|
||||
if(NDS_ARM9.CPSR.bits.T)
|
||||
des_thumb_instructions_set[(NDS_ARM9.instruction)>>6](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, logbuf);
|
||||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM9.instruction)](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, logbuf);
|
||||
sprintf(logbuf, "%s\t%08X\n\t R00: %08X, R01: %08X, R02: %08X, R03: %08X, R04: %08X, R05: %08X, R06: %08X, R07: %08X,\n\t R08: %08X, R09: %08X, R10: %08X, R11: %08X, R12: %08X, R13: %08X, R14: %08X, R15: %08X,\n\t CPSR: %08X , SPSR: %08X",
|
||||
logbuf, NDS_ARM9.instruction, NDS_ARM9.R[0], NDS_ARM9.R[1], NDS_ARM9.R[2], NDS_ARM9.R[3], NDS_ARM9.R[4], NDS_ARM9.R[5], NDS_ARM9.R[6], NDS_ARM9.R[7],
|
||||
NDS_ARM9.R[8], NDS_ARM9.R[9], NDS_ARM9.R[10], NDS_ARM9.R[11], NDS_ARM9.R[12], NDS_ARM9.R[13], NDS_ARM9.R[14], NDS_ARM9.R[15],
|
||||
NDS_ARM9.CPSR, NDS_ARM9.SPSR);
|
||||
LOG(logbuf);
|
||||
}
|
||||
if(logcount==3){
|
||||
if(NDS_ARM9.CPSR.bits.T)
|
||||
des_thumb_instructions_set[(NDS_ARM9.instruction)>>6](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, logbuf);
|
||||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM9.instruction)](NDS_ARM9.instruct_adr, NDS_ARM9.instruction, logbuf);
|
||||
sprintf(logbuf, "%s\t%08X\n\t R00: %08X, R01: %08X, R02: %08X, R03: %08X, R04: %08X, R05: %08X, R06: %08X, R07: %08X,\n\t R08: %08X, R09: %08X, R10: %08X, R11: %08X, R12: %08X, R13: %08X, R14: %08X, R15: %08X,\n\t CPSR: %08X , SPSR: %08X",
|
||||
logbuf, NDS_ARM9.instruction, NDS_ARM9.R[0], NDS_ARM9.R[1], NDS_ARM9.R[2], NDS_ARM9.R[3], NDS_ARM9.R[4], NDS_ARM9.R[5], NDS_ARM9.R[6], NDS_ARM9.R[7],
|
||||
NDS_ARM9.R[8], NDS_ARM9.R[9], NDS_ARM9.R[10], NDS_ARM9.R[11], NDS_ARM9.R[12], NDS_ARM9.R[13], NDS_ARM9.R[14], NDS_ARM9.R[15],
|
||||
NDS_ARM9.CPSR, NDS_ARM9.SPSR);
|
||||
LOG(logbuf);
|
||||
}
|
||||
#endif
|
||||
if(NDS_ARM9.waitIRQ)
|
||||
nds.ARM9Cycle += 100;
|
||||
else
|
||||
//nds.ARM9Cycle += NDS_ARM9.exec();
|
||||
nds.ARM9Cycle += armcpu_exec(&NDS_ARM9);
|
||||
}
|
||||
for (i = 0; i < 4 && (!force); i++)
|
||||
{
|
||||
if(NDS_ARM9.waitIRQ)
|
||||
nds.ARM9Cycle += 100;
|
||||
else
|
||||
//nds.ARM9Cycle += NDS_ARM9.exec();
|
||||
nds.ARM9Cycle += armcpu_exec(&NDS_ARM9);
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef EXPERIMENTAL_WIFI
|
||||
|
||||
if((nds.ARM7Cycle % 0x3F03) == 0)
|
||||
{
|
||||
/* 3F03 arm7 cyles = ~1usec */
|
||||
WIFI_usTrigger(&wifiMac) ;
|
||||
}
|
||||
if((nds.ARM7Cycle % 0x3F03) == 0)
|
||||
{
|
||||
/* 3F03 arm7 cyles = ~1usec */
|
||||
WIFI_usTrigger(&wifiMac) ;
|
||||
}
|
||||
#endif
|
||||
if(nds.ARM7Cycle<=nds.cycles)
|
||||
{
|
||||
if(nds.ARM7Cycle<=nds.cycles)
|
||||
{
|
||||
#ifdef LOG_ARM7
|
||||
if(logcount==1){
|
||||
if(NDS_ARM7.CPSR.bits.T)
|
||||
des_thumb_instructions_set[(NDS_ARM7.instruction)>>6](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, logbuf);
|
||||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM7.instruction)](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, logbuf);
|
||||
sprintf(logbuf, "%s\n\t R00: %08X, R01: %08X, R02: %08X, R03: %08X, R04: %08X, R05: %08X, R06: %08X, R07: %08X,\n\t R08: %08X, R09: %08X, R10: %08X, R11: %08X, R12: %08X, R13: %08X, R14: %08X, R15: %08X,\n\t CPSR: %08X , SPSR: %08X",
|
||||
logbuf, NDS_ARM7.R[0], NDS_ARM7.R[1], NDS_ARM7.R[2], NDS_ARM7.R[3], NDS_ARM7.R[4], NDS_ARM7.R[5], NDS_ARM7.R[6], NDS_ARM7.R[7],
|
||||
NDS_ARM7.R[8], NDS_ARM7.R[9], NDS_ARM7.R[10], NDS_ARM7.R[11], NDS_ARM7.R[12], NDS_ARM7.R[13], NDS_ARM7.R[14], NDS_ARM7.R[15],
|
||||
NDS_ARM7.CPSR, NDS_ARM7.SPSR);
|
||||
LOG(logbuf);
|
||||
}
|
||||
if(logcount==1){
|
||||
if(NDS_ARM7.CPSR.bits.T)
|
||||
des_thumb_instructions_set[(NDS_ARM7.instruction)>>6](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, logbuf);
|
||||
else
|
||||
des_arm_instructions_set[INDEX(NDS_ARM7.instruction)](NDS_ARM7.instruct_adr, NDS_ARM7.instruction, logbuf);
|
||||
sprintf(logbuf, "%s\n\t R00: %08X, R01: %08X, R02: %08X, R03: %08X, R04: %08X, R05: %08X, R06: %08X, R07: %08X,\n\t R08: %08X, R09: %08X, R10: %08X, R11: %08X, R12: %08X, R13: %08X, R14: %08X, R15: %08X,\n\t CPSR: %08X , SPSR: %08X",
|
||||
logbuf, NDS_ARM7.R[0], NDS_ARM7.R[1], NDS_ARM7.R[2], NDS_ARM7.R[3], NDS_ARM7.R[4], NDS_ARM7.R[5], NDS_ARM7.R[6], NDS_ARM7.R[7],
|
||||
NDS_ARM7.R[8], NDS_ARM7.R[9], NDS_ARM7.R[10], NDS_ARM7.R[11], NDS_ARM7.R[12], NDS_ARM7.R[13], NDS_ARM7.R[14], NDS_ARM7.R[15],
|
||||
NDS_ARM7.CPSR, NDS_ARM7.SPSR);
|
||||
LOG(logbuf);
|
||||
}
|
||||
#endif
|
||||
if(NDS_ARM7.waitIRQ)
|
||||
nds.ARM7Cycle += 100;
|
||||
else
|
||||
//nds.ARM7Cycle += (NDS_ARM7.exec()<<1);
|
||||
nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1);
|
||||
}
|
||||
nds.cycles = (nds.ARM9Cycle<nds.ARM7Cycle)?nds.ARM9Cycle : nds.ARM7Cycle;
|
||||
for (i = 0; i < 4 && (!force); i++)
|
||||
{
|
||||
if(NDS_ARM7.waitIRQ)
|
||||
nds.ARM7Cycle += 100;
|
||||
else
|
||||
//nds.ARM7Cycle += (NDS_ARM7.exec()<<1);
|
||||
nds.ARM7Cycle += (armcpu_exec(&NDS_ARM7)<<1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
nds.cycles = (nds.ARM9Cycle<nds.ARM7Cycle)?nds.ARM9Cycle : nds.ARM7Cycle;
|
||||
|
||||
//debug();
|
||||
|
||||
|
@ -1006,39 +1018,32 @@ NDS_exec(s32 nb, BOOL force)
|
|||
nds.ARM9Cycle -= (560190<<1);
|
||||
nds.ARM7Cycle -= (560190<<1);
|
||||
nb -= (560190<<1);
|
||||
if(MMU.timerON[0][0])
|
||||
nds.timerCycle[0][0] -= (560190<<1);
|
||||
if(MMU.timerON[0][1])
|
||||
nds.timerCycle[0][1] -= (560190<<1);
|
||||
if(MMU.timerON[0][2])
|
||||
nds.timerCycle[0][2] -= (560190<<1);
|
||||
if(MMU.timerON[0][3])
|
||||
nds.timerCycle[0][3] -= (560190<<1);
|
||||
|
||||
if(MMU.timerON[1][0])
|
||||
nds.timerCycle[1][0] -= (560190<<1);
|
||||
if(MMU.timerON[1][1])
|
||||
nds.timerCycle[1][1] -= (560190<<1);
|
||||
if(MMU.timerON[1][2])
|
||||
nds.timerCycle[1][2] -= (560190<<1);
|
||||
if(MMU.timerON[1][3])
|
||||
nds.timerCycle[1][3] -= (560190<<1);
|
||||
if(MMU.DMAing[0][0])
|
||||
MMU.DMACycle[0][0] -= (560190<<1);
|
||||
if(MMU.DMAing[0][1])
|
||||
MMU.DMACycle[0][1] -= (560190<<1);
|
||||
if(MMU.DMAing[0][2])
|
||||
MMU.DMACycle[0][2] -= (560190<<1);
|
||||
if(MMU.DMAing[0][3])
|
||||
MMU.DMACycle[0][3] -= (560190<<1);
|
||||
if(MMU.DMAing[1][0])
|
||||
MMU.DMACycle[1][0] -= (560190<<1);
|
||||
if(MMU.DMAing[1][1])
|
||||
MMU.DMACycle[1][1] -= (560190<<1);
|
||||
if(MMU.DMAing[1][2])
|
||||
MMU.DMACycle[1][2] -= (560190<<1);
|
||||
if(MMU.DMAing[1][3])
|
||||
MMU.DMACycle[1][3] -= (560190<<1);
|
||||
|
||||
if (MMU.CheckTimers)
|
||||
{
|
||||
if(MMU.timerON[0][0]) nds.timerCycle[0][0] -= (560190<<1);
|
||||
if(MMU.timerON[0][1]) nds.timerCycle[0][1] -= (560190<<1);
|
||||
if(MMU.timerON[0][2]) nds.timerCycle[0][2] -= (560190<<1);
|
||||
if(MMU.timerON[0][3]) nds.timerCycle[0][3] -= (560190<<1);
|
||||
|
||||
if(MMU.timerON[1][0]) nds.timerCycle[1][0] -= (560190<<1);
|
||||
if(MMU.timerON[1][1]) nds.timerCycle[1][1] -= (560190<<1);
|
||||
if(MMU.timerON[1][2]) nds.timerCycle[1][2] -= (560190<<1);
|
||||
if(MMU.timerON[1][3]) nds.timerCycle[1][3] -= (560190<<1);
|
||||
}
|
||||
|
||||
if (MMU.CheckDMAs)
|
||||
{
|
||||
if(MMU.DMAing[0][0]) MMU.DMACycle[0][0] -= (560190<<1);
|
||||
if(MMU.DMAing[0][1]) MMU.DMACycle[0][1] -= (560190<<1);
|
||||
if(MMU.DMAing[0][2]) MMU.DMACycle[0][2] -= (560190<<1);
|
||||
if(MMU.DMAing[0][3]) MMU.DMACycle[0][3] -= (560190<<1);
|
||||
|
||||
if(MMU.DMAing[1][0]) MMU.DMACycle[1][0] -= (560190<<1);
|
||||
if(MMU.DMAing[1][1]) MMU.DMACycle[1][1] -= (560190<<1);
|
||||
if(MMU.DMAing[1][2]) MMU.DMACycle[1][2] -= (560190<<1);
|
||||
if(MMU.DMAing[1][3]) MMU.DMACycle[1][3] -= (560190<<1);
|
||||
}
|
||||
}
|
||||
|
||||
T1WriteWord(ARM9Mem.ARM9_REG, 6, nds.VCount);
|
||||
|
@ -1065,387 +1070,403 @@ NDS_exec(s32 nb, BOOL force)
|
|||
T1WriteWord(MMU.ARM7_REG, 4, T1ReadWord(MMU.ARM7_REG, 4) & 0xFFFB);
|
||||
}
|
||||
}
|
||||
/* assume the timers have not expired */
|
||||
nds.timerOver[0][0] = 0;
|
||||
nds.timerOver[0][1] = 0;
|
||||
nds.timerOver[0][2] = 0;
|
||||
nds.timerOver[0][3] = 0;
|
||||
nds.timerOver[1][0] = 0;
|
||||
nds.timerOver[1][1] = 0;
|
||||
nds.timerOver[1][2] = 0;
|
||||
nds.timerOver[1][3] = 0;
|
||||
if(MMU.timerON[0][0])
|
||||
{
|
||||
if(MMU.timerRUN[0][0])
|
||||
{
|
||||
switch(MMU.timerMODE[0][0])
|
||||
{
|
||||
case 0xFFFF :
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][0])>>MMU.timerMODE[0][0];
|
||||
nds.old = MMU.timer[0][0];
|
||||
MMU.timer[0][0] += nds.diff;
|
||||
nds.timerCycle[0][0] += (nds.diff << MMU.timerMODE[0][0]);
|
||||
nds.timerOver[0][0] = nds.old>MMU.timer[0][0];
|
||||
if(nds.timerOver[0][0])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x102) & 0x40)
|
||||
NDS_makeARM9Int(3);
|
||||
MMU.timer[0][0] = MMU.timerReload[0][0];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][0] = TRUE;
|
||||
nds.timerCycle[0][0] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][1])
|
||||
{
|
||||
if(MMU.timerRUN[0][1])
|
||||
{
|
||||
switch(MMU.timerMODE[0][1])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][0])
|
||||
{
|
||||
++(MMU.timer[0][1]);
|
||||
nds.timerOver[0][1] = !MMU.timer[0][1];
|
||||
if (nds.timerOver[0][1])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x106) & 0x40)
|
||||
NDS_makeARM9Int(4);
|
||||
MMU.timer[0][1] = MMU.timerReload[0][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][1])>>MMU.timerMODE[0][1];
|
||||
nds.old = MMU.timer[0][1];
|
||||
MMU.timer[0][1] += nds.diff;
|
||||
nds.timerCycle[0][1] += nds.diff << MMU.timerMODE[0][1];
|
||||
nds.timerOver[0][1] = nds.old>MMU.timer[0][1];
|
||||
if(nds.timerOver[0][1])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x106) & 0x40)
|
||||
NDS_makeARM9Int(4);
|
||||
MMU.timer[0][1] = MMU.timerReload[0][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][1] = TRUE;
|
||||
nds.timerCycle[0][1] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][2])
|
||||
{
|
||||
if(MMU.timerRUN[0][2])
|
||||
{
|
||||
switch(MMU.timerMODE[0][2])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][1])
|
||||
{
|
||||
++(MMU.timer[0][2]);
|
||||
nds.timerOver[0][2] = !MMU.timer[0][2];
|
||||
if (nds.timerOver[0][2])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM9Int(5);
|
||||
MMU.timer[0][2] = MMU.timerReload[0][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][2])>>MMU.timerMODE[0][2];
|
||||
nds.old = MMU.timer[0][2];
|
||||
MMU.timer[0][2] += nds.diff;
|
||||
nds.timerCycle[0][2] += nds.diff << MMU.timerMODE[0][2];
|
||||
nds.timerOver[0][2] = nds.old>MMU.timer[0][2];
|
||||
if(nds.timerOver[0][2])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM9Int(5);
|
||||
MMU.timer[0][2] = MMU.timerReload[0][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][2] = TRUE;
|
||||
nds.timerCycle[0][2] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][3])
|
||||
{
|
||||
if(MMU.timerRUN[0][3])
|
||||
{
|
||||
switch(MMU.timerMODE[0][3])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][2])
|
||||
{
|
||||
++(MMU.timer[0][3]);
|
||||
nds.timerOver[0][3] = !MMU.timer[0][3];
|
||||
if (nds.timerOver[0][3])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM9Int(6);
|
||||
MMU.timer[0][3] = MMU.timerReload[0][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][3])>>MMU.timerMODE[0][3];
|
||||
nds.old = MMU.timer[0][3];
|
||||
MMU.timer[0][3] += nds.diff;
|
||||
nds.timerCycle[0][3] += nds.diff << MMU.timerMODE[0][3];
|
||||
nds.timerOver[0][3] = nds.old>MMU.timer[0][3];
|
||||
if(nds.timerOver[0][3])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM9Int(6);
|
||||
MMU.timer[0][3] = MMU.timerReload[0][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][3] = TRUE;
|
||||
nds.timerCycle[0][3] = nds.cycles;
|
||||
}
|
||||
}
|
||||
|
||||
if(MMU.timerON[1][0])
|
||||
{
|
||||
if(MMU.timerRUN[1][0])
|
||||
{
|
||||
switch(MMU.timerMODE[1][0])
|
||||
{
|
||||
case 0xFFFF :
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][0])>>MMU.timerMODE[1][0];
|
||||
nds.old = MMU.timer[1][0];
|
||||
MMU.timer[1][0] += nds.diff;
|
||||
nds.timerCycle[1][0] += nds.diff << MMU.timerMODE[1][0];
|
||||
nds.timerOver[1][0] = nds.old>MMU.timer[1][0];
|
||||
if(nds.timerOver[1][0])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x102) & 0x40)
|
||||
NDS_makeARM7Int(3);
|
||||
MMU.timer[1][0] = MMU.timerReload[1][0];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][0] = TRUE;
|
||||
nds.timerCycle[1][0] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][1])
|
||||
{
|
||||
if(MMU.timerRUN[1][1])
|
||||
{
|
||||
switch(MMU.timerMODE[1][1])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][0])
|
||||
{
|
||||
++(MMU.timer[1][1]);
|
||||
nds.timerOver[1][1] = !MMU.timer[1][1];
|
||||
if (nds.timerOver[1][1])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x106) & 0x40)
|
||||
NDS_makeARM7Int(4);
|
||||
MMU.timer[1][1] = MMU.timerReload[1][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][1])>>MMU.timerMODE[1][1];
|
||||
nds.old = MMU.timer[1][1];
|
||||
MMU.timer[1][1] += nds.diff;
|
||||
nds.timerCycle[1][1] += nds.diff << MMU.timerMODE[1][1];
|
||||
nds.timerOver[1][1] = nds.old>MMU.timer[1][1];
|
||||
if(nds.timerOver[1][1])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x106) & 0x40)
|
||||
NDS_makeARM7Int(4);
|
||||
MMU.timer[1][1] = MMU.timerReload[1][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][1] = TRUE;
|
||||
nds.timerCycle[1][1] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][2])
|
||||
{
|
||||
if(MMU.timerRUN[1][2])
|
||||
{
|
||||
switch(MMU.timerMODE[1][2])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][1])
|
||||
{
|
||||
++(MMU.timer[1][2]);
|
||||
nds.timerOver[1][2] = !MMU.timer[1][2];
|
||||
if (nds.timerOver[1][2])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM7Int(5);
|
||||
MMU.timer[1][2] = MMU.timerReload[1][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][2])>>MMU.timerMODE[1][2];
|
||||
nds.old = MMU.timer[1][2];
|
||||
MMU.timer[1][2] += nds.diff;
|
||||
nds.timerCycle[1][2] += nds.diff << MMU.timerMODE[1][2];
|
||||
nds.timerOver[1][2] = nds.old>MMU.timer[1][2];
|
||||
if(nds.timerOver[1][2])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM7Int(5);
|
||||
MMU.timer[1][2] = MMU.timerReload[1][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][2] = TRUE;
|
||||
nds.timerCycle[1][2] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][3])
|
||||
{
|
||||
if(MMU.timerRUN[1][3])
|
||||
{
|
||||
switch(MMU.timerMODE[1][3])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][2])
|
||||
{
|
||||
++(MMU.timer[1][3]);
|
||||
nds.timerOver[1][3] = !MMU.timer[1][3];
|
||||
if (nds.timerOver[1][3])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM7Int(6);
|
||||
MMU.timer[1][3] += MMU.timerReload[1][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][3])>>MMU.timerMODE[1][3];
|
||||
nds.old = MMU.timer[1][3];
|
||||
MMU.timer[1][3] += nds.diff;
|
||||
nds.timerCycle[1][3] += nds.diff << MMU.timerMODE[1][3];
|
||||
nds.timerOver[1][3] = nds.old>MMU.timer[1][3];
|
||||
if(nds.timerOver[1][3])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM7Int(6);
|
||||
MMU.timer[1][3] += MMU.timerReload[1][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][3] = TRUE;
|
||||
nds.timerCycle[1][3] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if (MMU.CheckTimers)
|
||||
{
|
||||
/* assume the timers have not expired */
|
||||
nds.timerOver[0][0] = 0;
|
||||
nds.timerOver[0][1] = 0;
|
||||
nds.timerOver[0][2] = 0;
|
||||
nds.timerOver[0][3] = 0;
|
||||
nds.timerOver[1][0] = 0;
|
||||
nds.timerOver[1][1] = 0;
|
||||
nds.timerOver[1][2] = 0;
|
||||
nds.timerOver[1][3] = 0;
|
||||
if(MMU.timerON[0][0])
|
||||
{
|
||||
if(MMU.timerRUN[0][0])
|
||||
{
|
||||
switch(MMU.timerMODE[0][0])
|
||||
{
|
||||
case 0xFFFF :
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][0])>>MMU.timerMODE[0][0];
|
||||
nds.old = MMU.timer[0][0];
|
||||
MMU.timer[0][0] += nds.diff;
|
||||
nds.timerCycle[0][0] += (nds.diff << MMU.timerMODE[0][0]);
|
||||
nds.timerOver[0][0] = nds.old>MMU.timer[0][0];
|
||||
if(nds.timerOver[0][0])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x102) & 0x40)
|
||||
NDS_makeARM9Int(3);
|
||||
MMU.timer[0][0] = MMU.timerReload[0][0];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][0] = TRUE;
|
||||
nds.timerCycle[0][0] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][1])
|
||||
{
|
||||
if(MMU.timerRUN[0][1])
|
||||
{
|
||||
switch(MMU.timerMODE[0][1])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][0])
|
||||
{
|
||||
++(MMU.timer[0][1]);
|
||||
nds.timerOver[0][1] = !MMU.timer[0][1];
|
||||
if (nds.timerOver[0][1])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x106) & 0x40)
|
||||
NDS_makeARM9Int(4);
|
||||
MMU.timer[0][1] = MMU.timerReload[0][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][1])>>MMU.timerMODE[0][1];
|
||||
nds.old = MMU.timer[0][1];
|
||||
MMU.timer[0][1] += nds.diff;
|
||||
nds.timerCycle[0][1] += nds.diff << MMU.timerMODE[0][1];
|
||||
nds.timerOver[0][1] = nds.old>MMU.timer[0][1];
|
||||
if(nds.timerOver[0][1])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x106) & 0x40)
|
||||
NDS_makeARM9Int(4);
|
||||
MMU.timer[0][1] = MMU.timerReload[0][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][1] = TRUE;
|
||||
nds.timerCycle[0][1] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][2])
|
||||
{
|
||||
if(MMU.timerRUN[0][2])
|
||||
{
|
||||
switch(MMU.timerMODE[0][2])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][1])
|
||||
{
|
||||
++(MMU.timer[0][2]);
|
||||
nds.timerOver[0][2] = !MMU.timer[0][2];
|
||||
if (nds.timerOver[0][2])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM9Int(5);
|
||||
MMU.timer[0][2] = MMU.timerReload[0][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][2])>>MMU.timerMODE[0][2];
|
||||
nds.old = MMU.timer[0][2];
|
||||
MMU.timer[0][2] += nds.diff;
|
||||
nds.timerCycle[0][2] += nds.diff << MMU.timerMODE[0][2];
|
||||
nds.timerOver[0][2] = nds.old>MMU.timer[0][2];
|
||||
if(nds.timerOver[0][2])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM9Int(5);
|
||||
MMU.timer[0][2] = MMU.timerReload[0][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][2] = TRUE;
|
||||
nds.timerCycle[0][2] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[0][3])
|
||||
{
|
||||
if(MMU.timerRUN[0][3])
|
||||
{
|
||||
switch(MMU.timerMODE[0][3])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[0][2])
|
||||
{
|
||||
++(MMU.timer[0][3]);
|
||||
nds.timerOver[0][3] = !MMU.timer[0][3];
|
||||
if (nds.timerOver[0][3])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM9Int(6);
|
||||
MMU.timer[0][3] = MMU.timerReload[0][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[0][3])>>MMU.timerMODE[0][3];
|
||||
nds.old = MMU.timer[0][3];
|
||||
MMU.timer[0][3] += nds.diff;
|
||||
nds.timerCycle[0][3] += nds.diff << MMU.timerMODE[0][3];
|
||||
nds.timerOver[0][3] = nds.old>MMU.timer[0][3];
|
||||
if(nds.timerOver[0][3])
|
||||
{
|
||||
if(T1ReadWord(ARM9Mem.ARM9_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM9Int(6);
|
||||
MMU.timer[0][3] = MMU.timerReload[0][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[0][3] = TRUE;
|
||||
nds.timerCycle[0][3] = nds.cycles;
|
||||
}
|
||||
}
|
||||
|
||||
if(MMU.timerON[1][0])
|
||||
{
|
||||
if(MMU.timerRUN[1][0])
|
||||
{
|
||||
switch(MMU.timerMODE[1][0])
|
||||
{
|
||||
case 0xFFFF :
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][0])>>MMU.timerMODE[1][0];
|
||||
nds.old = MMU.timer[1][0];
|
||||
MMU.timer[1][0] += nds.diff;
|
||||
nds.timerCycle[1][0] += nds.diff << MMU.timerMODE[1][0];
|
||||
nds.timerOver[1][0] = nds.old>MMU.timer[1][0];
|
||||
if(nds.timerOver[1][0])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x102) & 0x40)
|
||||
NDS_makeARM7Int(3);
|
||||
MMU.timer[1][0] = MMU.timerReload[1][0];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][0] = TRUE;
|
||||
nds.timerCycle[1][0] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][1])
|
||||
{
|
||||
if(MMU.timerRUN[1][1])
|
||||
{
|
||||
switch(MMU.timerMODE[1][1])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][0])
|
||||
{
|
||||
++(MMU.timer[1][1]);
|
||||
nds.timerOver[1][1] = !MMU.timer[1][1];
|
||||
if (nds.timerOver[1][1])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x106) & 0x40)
|
||||
NDS_makeARM7Int(4);
|
||||
MMU.timer[1][1] = MMU.timerReload[1][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][1])>>MMU.timerMODE[1][1];
|
||||
nds.old = MMU.timer[1][1];
|
||||
MMU.timer[1][1] += nds.diff;
|
||||
nds.timerCycle[1][1] += nds.diff << MMU.timerMODE[1][1];
|
||||
nds.timerOver[1][1] = nds.old>MMU.timer[1][1];
|
||||
if(nds.timerOver[1][1])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x106) & 0x40)
|
||||
NDS_makeARM7Int(4);
|
||||
MMU.timer[1][1] = MMU.timerReload[1][1];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][1] = TRUE;
|
||||
nds.timerCycle[1][1] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][2])
|
||||
{
|
||||
if(MMU.timerRUN[1][2])
|
||||
{
|
||||
switch(MMU.timerMODE[1][2])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][1])
|
||||
{
|
||||
++(MMU.timer[1][2]);
|
||||
nds.timerOver[1][2] = !MMU.timer[1][2];
|
||||
if (nds.timerOver[1][2])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM7Int(5);
|
||||
MMU.timer[1][2] = MMU.timerReload[1][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][2])>>MMU.timerMODE[1][2];
|
||||
nds.old = MMU.timer[1][2];
|
||||
MMU.timer[1][2] += nds.diff;
|
||||
nds.timerCycle[1][2] += nds.diff << MMU.timerMODE[1][2];
|
||||
nds.timerOver[1][2] = nds.old>MMU.timer[1][2];
|
||||
if(nds.timerOver[1][2])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10A) & 0x40)
|
||||
NDS_makeARM7Int(5);
|
||||
MMU.timer[1][2] = MMU.timerReload[1][2];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][2] = TRUE;
|
||||
nds.timerCycle[1][2] = nds.cycles;
|
||||
}
|
||||
}
|
||||
if(MMU.timerON[1][3])
|
||||
{
|
||||
if(MMU.timerRUN[1][3])
|
||||
{
|
||||
switch(MMU.timerMODE[1][3])
|
||||
{
|
||||
case 0xFFFF :
|
||||
if(nds.timerOver[1][2])
|
||||
{
|
||||
++(MMU.timer[1][3]);
|
||||
nds.timerOver[1][3] = !MMU.timer[1][3];
|
||||
if (nds.timerOver[1][3])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM7Int(6);
|
||||
MMU.timer[1][3] += MMU.timerReload[1][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
default :
|
||||
{
|
||||
nds.diff = (nds.cycles - nds.timerCycle[1][3])>>MMU.timerMODE[1][3];
|
||||
nds.old = MMU.timer[1][3];
|
||||
MMU.timer[1][3] += nds.diff;
|
||||
nds.timerCycle[1][3] += nds.diff << MMU.timerMODE[1][3];
|
||||
nds.timerOver[1][3] = nds.old>MMU.timer[1][3];
|
||||
if(nds.timerOver[1][3])
|
||||
{
|
||||
if(T1ReadWord(MMU.ARM7_REG, 0x10E) & 0x40)
|
||||
NDS_makeARM7Int(6);
|
||||
MMU.timer[1][3] += MMU.timerReload[1][3];
|
||||
}
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
MMU.timerRUN[1][3] = TRUE;
|
||||
nds.timerCycle[1][3] = nds.cycles;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (MMU.CheckDMAs)
|
||||
{
|
||||
|
||||
if((MMU.DMAing[0][0])&&(MMU.DMACycle[0][0]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*0), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*0)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][0])&(1<<30)) NDS_makeARM9Int(8);
|
||||
MMU.DMAing[0][0] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][1])&&(MMU.DMACycle[0][1]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*1), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*1)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][1])&(1<<30)) NDS_makeARM9Int(9);
|
||||
MMU.DMAing[0][1] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][2])&&(MMU.DMACycle[0][2]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*2), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*2)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][2])&(1<<30)) NDS_makeARM9Int(10);
|
||||
MMU.DMAing[0][2] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][3])&&(MMU.DMACycle[0][3]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*3), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*3)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][3])&(1<<30)) NDS_makeARM9Int(11);
|
||||
MMU.DMAing[0][3] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][0])&&(MMU.DMACycle[1][0]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*0), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*0)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][0])&(1<<30)) NDS_makeARM7Int(8);
|
||||
MMU.DMAing[1][0] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][1])&&(MMU.DMACycle[1][1]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*1), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*1)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][1])&(1<<30)) NDS_makeARM7Int(9);
|
||||
MMU.DMAing[1][1] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][2])&&(MMU.DMACycle[1][2]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*2), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*2)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][2])&(1<<30)) NDS_makeARM7Int(10);
|
||||
MMU.DMAing[1][2] = FALSE;
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][3])&&(MMU.DMACycle[1][3]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*3), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*3)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][3])&(1<<30)) NDS_makeARM7Int(11);
|
||||
MMU.DMAing[1][3] = FALSE;
|
||||
}
|
||||
if((MMU.DMAing[0][0])&&(MMU.DMACycle[0][0]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*0), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*0)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][0])&(1<<30)) NDS_makeARM9Int(8);
|
||||
MMU.DMAing[0][0] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(0+(0<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][1])&&(MMU.DMACycle[0][1]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*1), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*1)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][1])&(1<<30)) NDS_makeARM9Int(9);
|
||||
MMU.DMAing[0][1] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(1+(0<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][2])&&(MMU.DMACycle[0][2]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*2), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*2)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][2])&(1<<30)) NDS_makeARM9Int(10);
|
||||
MMU.DMAing[0][2] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(2+(0<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[0][3])&&(MMU.DMACycle[0][3]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*3), T1ReadLong(ARM9Mem.ARM9_REG, 0xB8 + (0xC*3)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[0][3])&(1<<30)) NDS_makeARM9Int(11);
|
||||
MMU.DMAing[0][3] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(3+(0<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][0])&&(MMU.DMACycle[1][0]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*0), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*0)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][0])&(1<<30)) NDS_makeARM7Int(8);
|
||||
MMU.DMAing[1][0] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(0+(1<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][1])&&(MMU.DMACycle[1][1]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*1), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*1)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][1])&(1<<30)) NDS_makeARM7Int(9);
|
||||
MMU.DMAing[1][1] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(1+(1<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][2])&&(MMU.DMACycle[1][2]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*2), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*2)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][2])&(1<<30)) NDS_makeARM7Int(10);
|
||||
MMU.DMAing[1][2] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(2+(1<<2)));
|
||||
}
|
||||
|
||||
if((MMU.DMAing[1][3])&&(MMU.DMACycle[1][3]<=nds.cycles))
|
||||
{
|
||||
T1WriteLong(MMU.ARM7_REG, 0xB8 + (0xC*3), T1ReadLong(MMU.ARM7_REG, 0xB8 + (0xC*3)) & 0x7FFFFFFF);
|
||||
if((MMU.DMACrt[1][3])&(1<<30)) NDS_makeARM7Int(11);
|
||||
MMU.DMAing[1][3] = FALSE;
|
||||
MMU.CheckDMAs &= ~(1<<(3+(1<<2)));
|
||||
}
|
||||
}
|
||||
|
||||
if((MMU.reg_IF[0]&MMU.reg_IE[0]) && (MMU.reg_IME[0]))
|
||||
{
|
||||
|
|
|
@ -36,7 +36,7 @@ BOOL CALLBACK AboutBox_Proc (HWND dialog, UINT message,WPARAM wparam,LPARAM lpar
|
|||
{
|
||||
case WM_INITDIALOG:
|
||||
{
|
||||
SetDlgItemText(dialog, IDC_AUTHORS_LIST, "Original author\n---------------\nyopyop\n\nCurrent team\n------------\nAllustar\namponzi\nape\ndelfare\nGuillaume Duhamel\nNormmatt\nRomain Vallet\nshash\nTheo Berkau\nthoduv\nTim Seidel (Mighty Max)\nDamien Nozay (damdoum)\nPascal Giard (evilynux)\nBen Jaques (masscat)\nJeff Bland\n\nContributors\n------------\nAnthony Molinaro\nsnkmad");
|
||||
SetDlgItemText(dialog, IDC_AUTHORS_LIST, "Original author\n---------------\nyopyop\n\nCurrent team\n------------\nAllustar\namponzi\nape\ndelfare\nGuillaume Duhamel\nNormmatt\nRomain Vallet\nBernat Muñoz (shash)\nTheo Berkau\nthoduv\nTim Seidel (Mighty Max)\nDamien Nozay (damdoum)\nPascal Giard (evilynux)\nBen Jaques (masscat)\nJeff Bland\n\nContributors\n------------\nAnthony Molinaro\nsnkmad");
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
@ -24,26 +24,18 @@
|
|||
#include <string.h>
|
||||
|
||||
#ifndef DESMUME_COCOA
|
||||
|
||||
#define WIN32_LEAN_AND_MEAN
|
||||
#include <windows.h>
|
||||
#include <gl\gl.h>
|
||||
#include "..\debug.h"
|
||||
#include "..\MMU.h"
|
||||
#include "..\bits.h"
|
||||
#include "..\matrix.h"
|
||||
|
||||
#define WIN32_LEAN_AND_MEAN
|
||||
#include <windows.h>
|
||||
#include <gl/gl.h>
|
||||
#else
|
||||
#include <OpenGL/gl.h>
|
||||
#include <OpenGL/glext.h>
|
||||
#endif
|
||||
|
||||
#include <OpenGL/gl.h>
|
||||
#include <OpenGL/glext.h>
|
||||
#include "../debug.h"
|
||||
#include "../MMU.h"
|
||||
#include "../bits.h"
|
||||
#include "../matrix.h"
|
||||
|
||||
#endif
|
||||
|
||||
#include "OGLRender.h"
|
||||
|
||||
|
||||
|
@ -51,7 +43,7 @@
|
|||
#define fix10_2float(v) (((float)((s32)(v))) / (float)(1<<9))
|
||||
|
||||
static unsigned char GPU_screen3D [256*256*3]={0};
|
||||
static unsigned char GPU_screen3DMask [256*256]={0};
|
||||
static float GPU_screen3Ddepth [256*256]={0};
|
||||
|
||||
// Acceleration tables
|
||||
static float* float16table = NULL;
|
||||
|
@ -104,6 +96,7 @@ static float fogColor[4] = {0.f};
|
|||
static float fogOffset = 0.f;
|
||||
static float alphaTestRef = 0.01f;
|
||||
|
||||
static float alphaTestBase = 0.1f;
|
||||
static unsigned long clCmd = 0;
|
||||
static unsigned long clInd = 0;
|
||||
static unsigned long clInd2 = 0;
|
||||
|
@ -116,6 +109,11 @@ static unsigned int vtxFormat;
|
|||
static unsigned int textureFormat=0, texturePalette=0;
|
||||
static unsigned int lastTextureFormat=0, lastTexturePalette=0;
|
||||
|
||||
static int diffuse[4] = {0},
|
||||
ambient[4] = {0},
|
||||
specular[4] = {0},
|
||||
emission[4] = {0};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int color; // Color in hardware format
|
||||
|
@ -165,16 +163,16 @@ char NDS_glInit(void)
|
|||
return 0;
|
||||
#endif
|
||||
|
||||
glEnable(GL_DEPTH_TEST);
|
||||
glEnable(GL_TEXTURE_2D);
|
||||
glEnable(GL_ALPHA_TEST);
|
||||
glEnable(GL_STENCIL_TEST);
|
||||
|
||||
glAlphaFunc (GL_GREATER, 0.01f);
|
||||
glStencilOp (GL_KEEP, GL_KEEP, GL_INCR);
|
||||
glClearColor (0.0f, 0.0f, 0.0f, 0.0f);
|
||||
glClearColor (0.f, 0.f, 0.f, 1.f);
|
||||
glColor3f (1.f, 1.f, 1.f);
|
||||
|
||||
glEnable (GL_NORMALIZE);
|
||||
glEnable (GL_DEPTH_TEST);
|
||||
glEnable (GL_TEXTURE_2D);
|
||||
|
||||
glAlphaFunc (GL_GREATER, 0.1f);
|
||||
glEnable (GL_ALPHA_TEST);
|
||||
|
||||
glGenTextures (1, (GLuint*)&oglTextureID);
|
||||
|
||||
glViewport(0, 0, 256, 192);
|
||||
|
@ -221,6 +219,20 @@ char NDS_glInit(void)
|
|||
return 1;
|
||||
}
|
||||
|
||||
void SetMaterialAlpha (int alphaValue)
|
||||
{
|
||||
diffuse[3] = alphaValue;
|
||||
ambient[3] = alphaValue;
|
||||
specular[3] = alphaValue;
|
||||
emission[3] = alphaValue;
|
||||
|
||||
glMaterialiv (GL_FRONT_AND_BACK, GL_AMBIENT, ambient);
|
||||
glMaterialiv (GL_FRONT_AND_BACK, GL_DIFFUSE, diffuse);
|
||||
|
||||
glMaterialiv (GL_FRONT_AND_BACK, GL_SPECULAR, specular);
|
||||
glMaterialiv (GL_FRONT_AND_BACK, GL_EMISSION, emission);
|
||||
}
|
||||
|
||||
void NDS_glViewPort(unsigned long v)
|
||||
{
|
||||
if(beginCalled)
|
||||
|
@ -280,7 +292,8 @@ void NDS_glClearDepth(unsigned long v)
|
|||
v &= 0x7FFFF;
|
||||
depth24b = (v*0x200)+((v+1)/0x8000);
|
||||
|
||||
glClearDepth(depth24b / ((float)(1<<24)));
|
||||
// Using 23 instead of 24 fixes SM 64 DS
|
||||
glClearDepth(depth24b / ((float)(1<<23)));
|
||||
|
||||
if(beginCalled)
|
||||
glBegin(vtxFormat);
|
||||
|
@ -952,14 +965,16 @@ void NDS_glBegin(unsigned long v)
|
|||
{
|
||||
glPolygonMode (GL_FRONT, GL_FILL);
|
||||
glPolygonMode (GL_BACK, GL_FILL);
|
||||
/*
|
||||
colorRGB[0] = 1.f;
|
||||
colorRGB[1] = 1.f;
|
||||
colorRGB[2] = 1.f;
|
||||
*/
|
||||
|
||||
colorRGB[3] = colorAlpha;
|
||||
glColor4iv ((GLint*)colorRGB);
|
||||
if (lightMask)
|
||||
{
|
||||
SetMaterialAlpha (colorAlpha);
|
||||
}
|
||||
else
|
||||
{
|
||||
colorRGB[3] = colorAlpha;
|
||||
glColor4iv ((GLint*)colorRGB);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
|
@ -1093,18 +1108,18 @@ int NDS_glGetNumVertex (void)
|
|||
|
||||
void NDS_glGetLine (int line, unsigned short * dst)
|
||||
{
|
||||
int i;
|
||||
u8 *screen3D = (u8 *)&GPU_screen3D [(192-(line%192))*256*3],
|
||||
*screen3DMask = (u8 *)&GPU_screen3DMask [(192-(line%192))*256];
|
||||
int i;
|
||||
u8 *screen3D = (u8 *)&GPU_screen3D [(192-(line%192))*256*3];
|
||||
float *screen3Ddepth = &GPU_screen3Ddepth [(192-(line%192))*256];
|
||||
|
||||
for(i = 0; i < 256; i++)
|
||||
{
|
||||
u32 r = screen3D[i*3+0],
|
||||
g = screen3D[i*3+1],
|
||||
b = screen3D[i*3+2];
|
||||
|
||||
if (screen3DMask[i] > 0)
|
||||
if (screen3Ddepth[i] < 1.f)
|
||||
{
|
||||
u32 r = screen3D[i*3+0],
|
||||
g = screen3D[i*3+1],
|
||||
b = screen3D[i*3+2];
|
||||
|
||||
dst[i] = (((r>>3)<<10) | ((g>>3)<<5) | (b>>3));
|
||||
}
|
||||
}
|
||||
|
@ -1122,8 +1137,8 @@ void NDS_glFlush(unsigned long v)
|
|||
clInd = 0;
|
||||
|
||||
glFlush();
|
||||
glReadPixels(0,0,256,192,GL_BGR_EXT, GL_UNSIGNED_BYTE,GPU_screen3D);
|
||||
glReadPixels(0,0,256,192,GL_STENCIL_INDEX, GL_UNSIGNED_BYTE,GPU_screen3DMask);
|
||||
glReadPixels(0,0,256,192,GL_DEPTH_COMPONENT, GL_FLOAT, GPU_screen3Ddepth);
|
||||
glReadPixels(0,0,256,192,GL_BGR_EXT, GL_UNSIGNED_BYTE, GPU_screen3D);
|
||||
|
||||
numVertex = 0;
|
||||
|
||||
|
@ -1137,8 +1152,6 @@ void NDS_glFlush(unsigned long v)
|
|||
|
||||
void NDS_glPolygonAttrib (unsigned long val)
|
||||
{
|
||||
//u32 polygonID = (val>>24)&63;
|
||||
|
||||
// Light enable/disable
|
||||
lightMask = (val&0xF);
|
||||
|
||||
|
@ -1169,14 +1182,15 @@ void NDS_glPolygonAttrib (unsigned long val)
|
|||
*/
|
||||
void NDS_glMaterial0 (unsigned long val)
|
||||
{
|
||||
int diffuse[4] = { (val&0x1F) << 26,
|
||||
((val>>5)&0x1F) << 26,
|
||||
((val>>10)&0x1F) << 26,
|
||||
0x7fffffff },
|
||||
ambient[4] = { ((val>>16)&0x1F) << 26,
|
||||
((val>>21)&0x1F) << 26,
|
||||
((val>>26)&0x1F) << 26,
|
||||
0x7fffffff };
|
||||
diffuse[0] = ((val&0x1F) << 26) | 0x03FFFFFF;
|
||||
diffuse[1] = (((val>>5)&0x1F) << 26) | 0x03FFFFFF;
|
||||
diffuse[2] = (((val>>10)&0x1F) << 26) | 0x03FFFFFF;
|
||||
diffuse[3] = 0x7fffffff;
|
||||
|
||||
ambient[0] = (((val>>16)&0x1F) << 26) | 0x03FFFFFF;
|
||||
ambient[1] = (((val>>21)&0x1F) << 26) | 0x03FFFFFF;
|
||||
ambient[2] = (((val>>26)&0x1F) << 26) | 0x03FFFFFF;
|
||||
ambient[3] = 0x7fffffff;
|
||||
|
||||
if (BIT15(val))
|
||||
{
|
||||
|
@ -1201,14 +1215,15 @@ void NDS_glMaterial0 (unsigned long val)
|
|||
|
||||
void NDS_glMaterial1 (unsigned long val)
|
||||
{
|
||||
int specular[4] = { (val&0x1F) << 26,
|
||||
((val>>5)&0x1F) << 26,
|
||||
((val>>10)&0x1F) << 26,
|
||||
0x7fffffff },
|
||||
emission[4] = { ((val>>16)&0x1F) << 26,
|
||||
((val>>21)&0x1F) << 26,
|
||||
((val>>26)&0x1F) << 26,
|
||||
0x7fffffff };
|
||||
specular[0] = ((val&0x1F) << 26) | 0x03FFFFFF;
|
||||
specular[1] = (((val>>5)&0x1F) << 26) | 0x03FFFFFF;
|
||||
specular[2] = (((val>>10)&0x1F) << 26) | 0x03FFFFFF;
|
||||
specular[3] = 0x7fffffff;
|
||||
|
||||
emission[0] = (((val>>16)&0x1F) << 26) | 0x03FFFFFF;
|
||||
emission[1] = (((val>>21)&0x1F) << 26) | 0x03FFFFFF;
|
||||
emission[2] = (((val>>26)&0x1F) << 26) | 0x03FFFFFF;
|
||||
emission[3] = 0x7fffffff;
|
||||
|
||||
if (beginCalled)
|
||||
{
|
||||
|
@ -1351,11 +1366,26 @@ void NDS_glControl(unsigned long v)
|
|||
|
||||
if(v&(1<<2))
|
||||
{
|
||||
glAlphaFunc (GL_GREATER, 0.01f);
|
||||
glAlphaFunc (GL_GREATER, alphaTestBase);
|
||||
}
|
||||
else
|
||||
{
|
||||
glAlphaFunc (GL_GREATER, alphaTestRef);
|
||||
glAlphaFunc (GL_GREATER, 0.1f);
|
||||
}
|
||||
|
||||
if(v&(1<<3))
|
||||
{
|
||||
glBlendFunc (GL_SRC_ALPHA, GL_ONE_MINUS_SRC_ALPHA);
|
||||
glEnable (GL_BLEND);
|
||||
}
|
||||
else
|
||||
{
|
||||
glDisable (GL_BLEND);
|
||||
}
|
||||
|
||||
if (v&(1<<14))
|
||||
{
|
||||
LOG ("Enabled BITMAP background mode");
|
||||
}
|
||||
|
||||
if(beginCalled)
|
||||
|
|
|
@ -452,7 +452,7 @@ DWORD WINAPI run( LPVOID lpParameter)
|
|||
if(curticks >= fpsticks + freq)
|
||||
{
|
||||
fps = fpsframecount;
|
||||
sprintf(txt,"DeSmuME %d", fps);
|
||||
sprintf(txt,"DeSmuME v%s (%d)", VERSION, fps);
|
||||
SetWindowText(hwnd, txt);
|
||||
fpsframecount = 0;
|
||||
QueryPerformanceCounter((LARGE_INTEGER *)&fpsticks);
|
||||
|
@ -770,6 +770,10 @@ int WINAPI WinMain (HINSTANCE hThisInstance,
|
|||
CheckMenuItem(menu, frameskiprate + IDC_FRAMESKIP0, MF_BYCOMMAND | MF_CHECKED);
|
||||
}
|
||||
|
||||
#ifdef BETA_VERSION
|
||||
EnableMenuItem (menu, IDM_SUBMITBUGREPORT, MF_GRAYED);
|
||||
#endif
|
||||
|
||||
sndcoretype = GetPrivateProfileInt("Sound","SoundCore", SNDCORE_DIRECTX, IniName);
|
||||
sndbuffersize = GetPrivateProfileInt("Sound","SoundBufferSize", 735 * 4, IniName);
|
||||
|
||||
|
@ -1573,6 +1577,7 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
|
|||
case IDM_WEBSITE:
|
||||
ShellExecute(NULL, "open", "http://desmume.sourceforge.net", NULL, NULL, SW_SHOWNORMAL);
|
||||
return 0;
|
||||
|
||||
case IDM_FORUM:
|
||||
ShellExecute(NULL, "open", "http://forums.desmume.org/index.php", NULL, NULL, SW_SHOWNORMAL);
|
||||
return 0;
|
||||
|
@ -1586,9 +1591,13 @@ LRESULT CALLBACK WindowProcedure (HWND hwnd, UINT message, WPARAM wParam, LPARAM
|
|||
|
||||
break;
|
||||
}
|
||||
|
||||
#ifndef BETA_VERSION
|
||||
case IDM_SUBMITBUGREPORT:
|
||||
ShellExecute(NULL, "open", "http://sourceforge.net/tracker/?func=add&group_id=164579&atid=832291", NULL, NULL, SW_SHOWNORMAL);
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
case IDC_ROTATE0:
|
||||
GPU_rotation = 0;
|
||||
GPU_width = 256;
|
||||
|
|
Loading…
Reference in New Issue